7,11c7,11
< host_inst_rate 69606 # Simulator instruction rate (inst/s)
< host_op_rate 88987 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 18296996 # Simulator tick rate (ticks/s)
< host_mem_usage 240272 # Number of bytes of host memory used
< host_seconds 3922.77 # Real time elapsed on the host
---
> host_inst_rate 120484 # Simulator instruction rate (inst/s)
> host_op_rate 154032 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 31671128 # Simulator tick rate (ticks/s)
> host_mem_usage 240520 # Number of bytes of host memory used
> host_seconds 2266.26 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 472896 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 7389 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory
> system.physmem.bytes_read::total 472896 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s)
370a378
> system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses
371a380
> system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses
372a382
> system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses
373a384
> system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency
374a386
> system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency
375a388
> system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency
402a416
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses
403a418
> system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses
404a420
> system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses
405a422
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency
406a424
> system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency
407a426
> system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency
462a482
> system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses
463a484
> system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses
464a486
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses
465a488
> system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses
466a490
> system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses
467a492
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency
468a494
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency
469a496
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency
470a498
> system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency
471a500
> system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency
508a538
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
509a540
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
510a542
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
511a544
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
512a546
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112 # average ReadReq mshr miss latency
513a548
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336 # average WriteReq mshr miss latency
514a550
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency
515a552
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency
583a621
> system.cpu.l2cache.ReadReq_miss_rate::total 0.258647 # miss rate for ReadReq accesses
584a623
> system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
585a625
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.994006 # miss rate for ReadExReq accesses
587a628
> system.cpu.l2cache.demand_miss_rate::total 0.359234 # miss rate for demand accesses
589a631
> system.cpu.l2cache.overall_miss_rate::total 0.359234 # miss rate for overall accesses
591a634
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34292.611795 # average ReadReq miss latency
592a636
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34476.055339 # average ReadExReq miss latency
594a639
> system.cpu.l2cache.demand_avg_miss_latency::total 34362.043502 # average overall miss latency
596a642
> system.cpu.l2cache.overall_avg_miss_latency::total 34362.043502 # average overall miss latency
641a688
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255350 # mshr miss rate for ReadReq accesses
642a690
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
643a692
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994006 # mshr miss rate for ReadExReq accesses
645a695
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses
647a698
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses
649a701
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829 # average ReadReq mshr miss latency
650a703
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
651a705
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556 # average ReadExReq mshr miss latency
653a708
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency
655a711
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency
< host_inst_rate 69606 # Simulator instruction rate (inst/s)
< host_op_rate 88987 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 18296996 # Simulator tick rate (ticks/s)
< host_mem_usage 240272 # Number of bytes of host memory used
< host_seconds 3922.77 # Real time elapsed on the host
---
> host_inst_rate 120484 # Simulator instruction rate (inst/s)
> host_op_rate 154032 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 31671128 # Simulator tick rate (ticks/s)
> host_mem_usage 240520 # Number of bytes of host memory used
> host_seconds 2266.26 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 472896 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 7389 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory
> system.physmem.bytes_read::total 472896 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s)
370a378
> system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses
371a380
> system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses
372a382
> system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses
373a384
> system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency
374a386
> system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency
375a388
> system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency
402a416
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses
403a418
> system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses
404a420
> system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses
405a422
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency
406a424
> system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency
407a426
> system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency
462a482
> system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses
463a484
> system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses
464a486
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses
465a488
> system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses
466a490
> system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses
467a492
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency
468a494
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency
469a496
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency
470a498
> system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency
471a500
> system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency
508a538
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
509a540
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
510a542
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
511a544
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
512a546
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112 # average ReadReq mshr miss latency
513a548
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336 # average WriteReq mshr miss latency
514a550
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency
515a552
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency
583a621
> system.cpu.l2cache.ReadReq_miss_rate::total 0.258647 # miss rate for ReadReq accesses
584a623
> system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
585a625
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.994006 # miss rate for ReadExReq accesses
587a628
> system.cpu.l2cache.demand_miss_rate::total 0.359234 # miss rate for demand accesses
589a631
> system.cpu.l2cache.overall_miss_rate::total 0.359234 # miss rate for overall accesses
591a634
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34292.611795 # average ReadReq miss latency
592a636
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34476.055339 # average ReadExReq miss latency
594a639
> system.cpu.l2cache.demand_avg_miss_latency::total 34362.043502 # average overall miss latency
596a642
> system.cpu.l2cache.overall_avg_miss_latency::total 34362.043502 # average overall miss latency
641a688
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255350 # mshr miss rate for ReadReq accesses
642a690
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
643a692
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994006 # mshr miss rate for ReadExReq accesses
645a695
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses
647a698
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses
649a701
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829 # average ReadReq mshr miss latency
650a703
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
651a705
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556 # average ReadExReq mshr miss latency
653a708
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency
655a711
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency