3,5c3,5
< sim_seconds 0.124349 # Number of seconds simulated
< sim_ticks 124348696500 # Number of ticks simulated
< final_tick 124348696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.124341 # Number of seconds simulated
> sim_ticks 124340889500 # Number of ticks simulated
> final_tick 124340889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 233440 # Simulator instruction rate (inst/s)
< host_op_rate 280271 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 106315167 # Simulator tick rate (ticks/s)
< host_mem_usage 292792 # Number of bytes of host memory used
< host_seconds 1169.62 # Real time elapsed on the host
---
> host_inst_rate 229813 # Simulator instruction rate (inst/s)
> host_op_rate 275917 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 104656772 # Simulator tick rate (ticks/s)
> host_mem_usage 292960 # Number of bytes of host memory used
> host_seconds 1188.08 # Real time elapsed on the host
16,37c16,37
< system.physmem.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 1887808 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 14649536 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 167872 # Number of bytes read from this memory
< system.physmem.bytes_read::total 16705216 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1887808 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1887808 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 29497 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 228899 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 2623 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 261019 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 15181566 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 117810129 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 1350010 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 134341706 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 15181566 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 15181566 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 15181566 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 117810129 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 1350010 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 134341706 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 261020 # Number of read requests accepted
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 1894400 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 14645312 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 169216 # Number of bytes read from this memory
> system.physmem.bytes_read::total 16708928 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1894400 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 29600 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 228833 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 2644 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 261077 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 15235535 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 117783555 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 1360904 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 134379994 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 15235535 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 15235535 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 15235535 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 117783555 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 1360904 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 134379994 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 261078 # Number of read requests accepted
39c39
< system.physmem.readBursts 261020 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 261078 # Number of DRAM read bursts, including those serviced by the write queue
41c41
< system.physmem.bytesReadDRAM 16705280 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 16708992 # Total number of bytes read from DRAM
44c44
< system.physmem.bytesReadSys 16705280 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 16708992 # Total read bytes from the system interface side
49,57c49,57
< system.physmem.perBankRdBursts::0 1258 # Per bank write bursts
< system.physmem.perBankRdBursts::1 69987 # Per bank write bursts
< system.physmem.perBankRdBursts::2 1297 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10756 # Per bank write bursts
< system.physmem.perBankRdBursts::4 42907 # Per bank write bursts
< system.physmem.perBankRdBursts::5 121816 # Per bank write bursts
< system.physmem.perBankRdBursts::6 153 # Per bank write bursts
< system.physmem.perBankRdBursts::7 252 # Per bank write bursts
< system.physmem.perBankRdBursts::8 224 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 1259 # Per bank write bursts
> system.physmem.perBankRdBursts::1 69989 # Per bank write bursts
> system.physmem.perBankRdBursts::2 1294 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10805 # Per bank write bursts
> system.physmem.perBankRdBursts::4 42847 # Per bank write bursts
> system.physmem.perBankRdBursts::5 121814 # Per bank write bursts
> system.physmem.perBankRdBursts::6 160 # Per bank write bursts
> system.physmem.perBankRdBursts::7 259 # Per bank write bursts
> system.physmem.perBankRdBursts::8 225 # Per bank write bursts
59c59
< system.physmem.perBankRdBursts::10 7773 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 7823 # Per bank write bursts
61,63c61,63
< system.physmem.perBankRdBursts::12 1213 # Per bank write bursts
< system.physmem.perBankRdBursts::13 743 # Per bank write bursts
< system.physmem.perBankRdBursts::14 657 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 1216 # Per bank write bursts
> system.physmem.perBankRdBursts::13 747 # Per bank write bursts
> system.physmem.perBankRdBursts::14 656 # Per bank write bursts
83c83
< system.physmem.totGap 124348687000 # Total gap between requests
---
> system.physmem.totGap 124340880000 # Total gap between requests
90c90
< system.physmem.readPktSize::6 261020 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 261078 # Read request sizes (log2)
98,111c98,111
< system.physmem.rdQLenPdf::0 204123 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 43351 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 12113 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 303 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 238 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 212 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 172 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 241 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 121 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 204158 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 43358 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 12121 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 247 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 209 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 181 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 123 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 61 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see
194,211c194,211
< system.physmem.bytesPerActivate::samples 67933 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 245.871432 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 180.817049 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 200.519544 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 18227 26.83% 26.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 22195 32.67% 59.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 11448 16.85% 76.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6857 10.09% 86.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4767 7.02% 93.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2062 3.04% 96.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1306 1.92% 98.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 411 0.61% 99.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 660 0.97% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 67933 # Bytes accessed per row activation
< system.physmem.totQLat 4577430956 # Total ticks spent queuing
< system.physmem.totMemAccLat 9471555956 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1305100000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 17536.71 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 67983 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 245.745201 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 180.705876 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 200.483366 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 18259 26.86% 26.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 22263 32.75% 59.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 11383 16.74% 76.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 6868 10.10% 86.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4760 7.00% 93.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2080 3.06% 96.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1310 1.93% 98.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 394 0.58% 99.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 666 0.98% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 67983 # Bytes accessed per row activation
> system.physmem.totQLat 4612072505 # Total ticks spent queuing
> system.physmem.totMemAccLat 9507285005 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1305390000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 17665.50 # Average queueing delay per DRAM burst
213,214c213,214
< system.physmem.avgMemAccLat 36286.71 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 134.34 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 36415.50 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 134.38 # Average DRAM read bandwidth in MiByte/s
216c216
< system.physmem.avgRdBWSys 134.34 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 134.38 # Average system read bandwidth in MiByte/s
224c224
< system.physmem.readRowHits 193077 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 193085 # Number of row buffer hits during reads
226c226
< system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads
228,232c228,232
< system.physmem.avgGap 476395.25 # Average gap between requests
< system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 450269820 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 239312700 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1773761640 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 476259.51 # Average gap between requests
> system.physmem.pageHitRate 73.96 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 450291240 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 239324085 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1773768780 # Energy for read commands per rank (pJ)
234,251c234,251
< system.physmem_0.refreshEnergy 9689184960.000002 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 4649576640 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 227532000 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 45899424420 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 3643060800 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 957889500 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 67530012480 # Total energy per rank (pJ)
< system.physmem_0.averagePower 543.069721 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 113559853415 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 155359000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 4100146000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 3415967750 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 9487195385 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 6533205335 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 100656823030 # Time in different power states
< system.physmem_1.actEnergy 34836060 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 18489240 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 89914020 # Energy for read commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 9681809280.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4644193560 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 227236800 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 45907805700 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 3604922400 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 978458700 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 67507810545 # Total energy per rank (pJ)
> system.physmem_0.averagePower 542.925264 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 113563299646 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 155533000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 4097020000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 3501663750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 9387944632 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 6524904104 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 100673824014 # Time in different power states
> system.physmem_1.actEnergy 35171640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 18667605 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 90321000 # Energy for read commands per rank (pJ)
253,273c253,273
< system.physmem_1.refreshEnergy 3070741440.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 722151240 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 123038400 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 10175174880 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 3785444640 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 22033476180 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 40053946380 # Total energy per rank (pJ)
< system.physmem_1.averagePower 322.109899 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 122443240524 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 197934000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1303004000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 90271203500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 9858082832 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 404517976 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 22313954192 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 35976625 # Number of BP lookups
< system.cpu.branchPred.condPredicted 19268286 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 984581 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 17895680 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13922117 # Number of BTB hits
---
> system.physmem_1.refreshEnergy 3119298000.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 731861760 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 127236960 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 10304428080 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 3803073120 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 21964091670 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 40194673995 # Total energy per rank (pJ)
> system.physmem_1.averagePower 323.261913 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 122403387505 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 207240000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1323736000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 89902145500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 9903979079 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 406525995 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 22597262926 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 36038003 # Number of BP lookups
> system.cpu.branchPred.condPredicted 19334387 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 996297 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17830996 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13933502 # Number of BTB hits
275,281c275,281
< system.cpu.branchPred.BTBHitPct 77.795965 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6952257 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 2517536 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 2473662 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 43874 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 129189 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 78.142029 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6950609 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 4465 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 2515874 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 2470358 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 45516 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 129389 # Number of mispredicted indirect branches.
283c283
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
313c313
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
343c343
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
373c373
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
404,405c404,405
< system.cpu.pwrStateResidencyTicks::ON 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 248697394 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 248681780 # number of cpu cycles simulated
408,421c408,421
< system.cpu.fetch.icacheStallCycles 13177926 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 309504909 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 35976625 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 23348036 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 231160130 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1995425 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 1604 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 3168 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 82224377 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 34576 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 245340603 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.517503 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.300446 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 13212448 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 309769989 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 36038003 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 23354469 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 231113604 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 2018885 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 1934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 3406 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 82291256 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 35072 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 245340926 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.517468 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.300338 # Number of instructions fetched each cycle (Total)
423,426c423,426
< system.cpu.fetch.rateDist::0 84898952 34.60% 34.60% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 40504202 16.51% 51.11% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 28011427 11.42% 62.53% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 91926022 37.47% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 84879866 34.60% 34.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 40535888 16.52% 51.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 28014472 11.42% 62.54% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 91910700 37.46% 100.00% # Number of instructions fetched each cycle (Total)
430,458c430,458
< system.cpu.fetch.rateDist::total 245340603 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.144660 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.244504 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 27511038 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 94682480 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 97198198 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 25085064 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 863823 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 6682260 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 348414004 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 3355254 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 863823 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 44231004 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 38750016 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 289461 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 104525811 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 56680488 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 344543449 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 1457117 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 7869034 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 94704 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 8433947 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 28409379 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 3429059 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 394730853 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2217537837 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 335903225 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 192790660 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 245340926 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.144916 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.245648 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 27542743 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 94606230 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 97234991 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 25081957 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 875005 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 12946400 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 134756 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 348426325 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 3406644 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 875005 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 44284460 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 38724844 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 289442 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 104535895 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 56631280 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 344535849 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 1483850 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 7863336 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 96546 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 8390481 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 28393613 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 3430855 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 394784790 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2217316444 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 335868704 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 192847846 # Number of floating rename lookups
460,477c460,477
< system.cpu.rename.UndoneMaps 22500805 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 11602 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 11569 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 59464824 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 89978946 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 84398563 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 2367642 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1978869 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 343240723 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 22618 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 339371435 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 952430 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 15451741 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 36726619 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 245340603 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.383266 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.138851 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 22554742 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 11609 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 11576 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 59430212 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 89918066 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 84391902 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 2366315 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1969070 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 343213178 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 22626 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 339325700 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 951900 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 15424204 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 36793818 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 245340926 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.383078 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.139070 # Number of insts issued each cycle
479,485c479,485
< system.cpu.iq.issued_per_cycle::0 64256390 26.19% 26.19% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 77349427 31.53% 57.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 59666013 24.32% 82.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 34385256 14.02% 96.05% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 8895869 3.63% 99.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 775150 0.32% 99.99% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 12498 0.01% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 64299867 26.21% 26.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 77319752 31.52% 57.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 59651654 24.31% 82.04% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 34378652 14.01% 96.05% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 8900677 3.63% 99.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 777968 0.32% 99.99% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 12356 0.01% 100.00% # Number of insts issued each cycle
491c491
< system.cpu.iq.issued_per_cycle::total 245340603 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 245340926 # Number of insts issued each cycle
493,527c493,527
< system.cpu.iq.fu_full::IntAlu 8783262 6.81% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 7311 0.01% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 160118 0.12% 6.94% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 165260 0.13% 7.06% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 81600 0.06% 7.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 59605 0.05% 7.17% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 821029 0.64% 7.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 312918 0.24% 8.05% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 382736 0.30% 8.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 27486319 21.30% 29.64% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 41316597 32.01% 61.66% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 30690860 23.78% 85.44% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 18793838 14.56% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 8768859 6.80% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 7313 0.01% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 162373 0.13% 6.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 163818 0.13% 7.06% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 81957 0.06% 7.12% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 59658 0.05% 7.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 818593 0.63% 7.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 313085 0.24% 8.04% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 382100 0.30% 8.34% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.34% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 27482783 21.31% 29.65% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 41323323 32.04% 61.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 30643180 23.76% 85.44% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 18783688 14.56% 100.00% # attempts to use FU when none available
531,532c531,532
< system.cpu.iq.FU_type_0::IntAlu 108168046 31.87% 31.87% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2148103 0.63% 32.51% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 108181018 31.88% 31.88% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2148109 0.63% 32.51% # Type of FU issued
553,565c553,565
< system.cpu.iq.FU_type_0::SimdFloatAdd 6799230 2.00% 34.51% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 8596305 2.53% 37.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 3207463 0.95% 37.99% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 1592644 0.47% 38.46% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 20838397 6.14% 44.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 7175267 2.11% 46.71% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140594 2.10% 48.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 46512276 13.71% 62.57% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 55971076 16.49% 79.07% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemRead 43494028 12.82% 91.88% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemWrite 27552709 8.12% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatAdd 6799471 2.00% 34.52% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 8597209 2.53% 37.05% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 3207374 0.95% 38.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 1592649 0.47% 38.47% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 20858202 6.15% 44.61% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 7175067 2.11% 46.73% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140627 2.10% 48.83% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 175298 0.05% 48.88% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 46505269 13.71% 62.59% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 55942906 16.49% 79.08% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 43451689 12.81% 91.88% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemWrite 27550812 8.12% 100.00% # Type of FU issued
568,580c568,580
< system.cpu.iq.FU_type_0::total 339371435 # Type of FU issued
< system.cpu.iq.rate 1.364596 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 129061453 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.380296 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 766002730 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 235175743 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 219154982 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 288094626 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 123554211 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 116970856 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 298827396 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 169605492 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5587628 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 339325700 # Type of FU issued
> system.cpu.iq.rate 1.364498 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 128990730 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.380138 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 765966009 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 235211704 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 219112487 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 287968947 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 123463225 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 116939299 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 298793937 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 169522493 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5585313 # Number of loads that had data forwarded from stores
582,585c582,585
< system.cpu.iew.lsq.thread0.squashedLoads 4246671 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 7079 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 2022946 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 4185791 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 7155 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 14925 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 2016285 # Number of stores squashed
588,589c588,589
< system.cpu.iew.lsq.thread0.rescheduledLoads 158625 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 537538 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 158671 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 539433 # Number of times an access to memory failed due to the cache being blocked
591,594c591,594
< system.cpu.iew.iewSquashCycles 863823 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 1349690 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1747618 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 343264743 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 875005 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1351770 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1745589 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 343237205 # Number of instructions dispatched to IQ
596,607c596,607
< system.cpu.iew.iewDispLoadInsts 89978946 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 84398563 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 11585 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 6720 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 1741103 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 14875 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 437791 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 454404 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 892195 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 337380808 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 89446151 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1990627 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 89918066 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 84391902 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 11593 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 6365 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 1739416 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 14925 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 447604 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 457294 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 904898 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 337307001 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 89393919 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 2018699 # Number of squashed instructions skipped in execute
609,620c609,620
< system.cpu.iew.exec_nop 1402 # number of nop insts executed
< system.cpu.iew.exec_refs 172577891 # number of memory reference insts executed
< system.cpu.iew.exec_branches 31542264 # Number of branches executed
< system.cpu.iew.exec_stores 83131740 # Number of stores executed
< system.cpu.iew.exec_rate 1.356592 # Inst execution rate
< system.cpu.iew.wb_sent 336269596 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 336125838 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 153087171 # num instructions producing a value
< system.cpu.iew.wb_consumers 267302196 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.351545 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.572712 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 14157457 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 1401 # number of nop insts executed
> system.cpu.iew.exec_refs 172494904 # number of memory reference insts executed
> system.cpu.iew.exec_branches 31547244 # Number of branches executed
> system.cpu.iew.exec_stores 83100985 # Number of stores executed
> system.cpu.iew.exec_rate 1.356380 # Inst execution rate
> system.cpu.iew.wb_sent 336195874 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 336051786 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 153071265 # num instructions producing a value
> system.cpu.iew.wb_consumers 267284033 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.351333 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.572691 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 14115058 # The number of squashed insts skipped by commit
622,625c622,625
< system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 243149020 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.348195 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.043585 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 861860 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 243135580 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.348269 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.043603 # Number of insts commited each cycle
627,635c627,635
< system.cpu.commit.committed_per_cycle::0 113393055 46.64% 46.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 66012492 27.15% 73.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 21342156 8.78% 82.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 13170021 5.42% 87.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 8181798 3.36% 91.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 4369731 1.80% 93.14% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 2981979 1.23% 94.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 2444680 1.01% 95.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 11253108 4.63% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 113362923 46.63% 46.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 66036162 27.16% 73.79% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 21343595 8.78% 82.56% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 13169605 5.42% 87.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 8174730 3.36% 91.34% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 4365960 1.80% 93.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 2981752 1.23% 94.36% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 2446011 1.01% 95.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 11254842 4.63% 100.00% # Number of insts commited each cycle
639c639
< system.cpu.commit.committed_per_cycle::total 243149020 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 243135580 # Number of insts commited each cycle
689,693c689,693
< system.cpu.commit.bw_lim_events 11253108 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 573863058 # The number of ROB reads
< system.cpu.rob.rob_writes 686133284 # The number of ROB writes
< system.cpu.timesIdled 39270 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 3356791 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 11254842 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 573805485 # The number of ROB reads
> system.cpu.rob.rob_writes 686062388 # The number of ROB writes
> system.cpu.timesIdled 39277 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 3340854 # Total number of cycles that the CPU has spent unscheduled due to idling
696,706c696,706
< system.cpu.cpi 0.910855 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.910855 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.097869 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.097869 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 325196483 # number of integer regfile reads
< system.cpu.int_regfile_writes 134110146 # number of integer regfile writes
< system.cpu.fp_regfile_reads 186451278 # number of floating regfile reads
< system.cpu.fp_regfile_writes 131762607 # number of floating regfile writes
< system.cpu.cc_regfile_reads 1279524952 # number of cc regfile reads
< system.cpu.cc_regfile_writes 79965424 # number of cc regfile writes
< system.cpu.misc_regfile_reads 1056166666 # number of misc regfile reads
---
> system.cpu.cpi 0.910798 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.910798 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.097938 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.097938 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 325088854 # number of integer regfile reads
> system.cpu.int_regfile_writes 134066659 # number of integer regfile writes
> system.cpu.fp_regfile_reads 186464530 # number of floating regfile reads
> system.cpu.fp_regfile_writes 131741747 # number of floating regfile writes
> system.cpu.cc_regfile_reads 1279144313 # number of cc regfile reads
> system.cpu.cc_regfile_writes 80001955 # number of cc regfile writes
> system.cpu.misc_regfile_reads 1055862294 # number of misc regfile reads
708,715c708,715
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 1542800 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.844324 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 161972906 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1543312 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 104.951498 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 90889000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.844324 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 1544317 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.844251 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 161914838 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1544829 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 104.810848 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 91273000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.844251 # Average occupied blocks per requestor
719,720c719,720
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
725,735c725,735
< system.cpu.dcache.tags.tag_accesses 333232684 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 333232684 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 80960207 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 80960207 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 80921128 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 80921128 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 69704 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 69704 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 333130269 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 333130269 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 80902071 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 80902071 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 80921196 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 80921196 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 69698 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 69698 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits
738,747c738,747
< system.cpu.dcache.demand_hits::cpu.data 161881335 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 161881335 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 161951039 # number of overall hits
< system.cpu.dcache.overall_hits::total 161951039 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2740251 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2740251 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1131571 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1131571 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 161823267 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 161823267 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 161892965 # number of overall hits
> system.cpu.dcache.overall_hits::total 161892965 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2746434 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2746434 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1131503 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1131503 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 13 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 13 # number of SoftPFReq misses
750,757c750,757
< system.cpu.dcache.demand_misses::cpu.data 3871822 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3871822 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3871840 # number of overall misses
< system.cpu.dcache.overall_misses::total 3871840 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 47426688500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 47426688500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9189520410 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9189520410 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 3877937 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3877937 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3877950 # number of overall misses
> system.cpu.dcache.overall_misses::total 3877950 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 47498967000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 47498967000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9188860405 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9188860405 # number of WriteReq miss cycles
760,765c760,765
< system.cpu.dcache.demand_miss_latency::cpu.data 56616208910 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 56616208910 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 56616208910 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 56616208910 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 83700458 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 83700458 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 56687827405 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 56687827405 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 56687827405 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 56687827405 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 83648505 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 83648505 # number of ReadReq accesses(hits+misses)
768,771c768,771
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 69722 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 69722 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 69711 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 69711 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses)
774,783c774,783
< system.cpu.dcache.demand_accesses::cpu.data 165753157 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 165753157 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 165822879 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 165822879 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032739 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.032739 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013791 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.013791 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 165701204 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 165701204 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 165770915 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 165770915 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032833 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.032833 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013790 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013790 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000186 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.000186 # miss rate for SoftPFReq accesses
786,793c786,793
< system.cpu.dcache.demand_miss_rate::cpu.data 0.023359 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.023359 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.023349 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.023349 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17307.424940 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17307.424940 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8121.028561 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 8121.028561 # average WriteReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.023403 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.023403 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.023393 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.023393 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17294.778247 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17294.778247 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8120.933312 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 8120.933312 # average WriteReq miss latency
796,799c796,799
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14622.626998 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14622.626998 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14622.559018 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14622.559018 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14618.037221 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14618.037221 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.988217 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14617.988217 # average overall miss latency
801c801
< system.cpu.dcache.blocked_cycles::no_targets 1097340 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 1101938 # number of cycles access was blocked
803c803
< system.cpu.dcache.blocked::no_targets 136170 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 136754 # number of cycles access was blocked
805,811c805,811
< system.cpu.dcache.avg_blocked_cycles::no_targets 8.058603 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 1542800 # number of writebacks
< system.cpu.dcache.writebacks::total 1542800 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1417655 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1417655 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910848 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 910848 # number of WriteReq MSHR hits
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 8.057812 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 1544317 # number of writebacks
> system.cpu.dcache.writebacks::total 1544317 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1422290 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1422290 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910806 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 910806 # number of WriteReq MSHR hits
814,839c814,839
< system.cpu.dcache.demand_mshr_hits::cpu.data 2328503 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2328503 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2328503 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2328503 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322596 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1322596 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220723 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 220723 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1543319 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1543319 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1543330 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1543330 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27069234000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 27069234000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844364193 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844364193 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1270000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1270000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913598193 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 28913598193 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28914868193 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28914868193 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015802 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015802 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 2333096 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2333096 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2333096 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2333096 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1324144 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1324144 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220697 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 220697 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 7 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1544841 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1544841 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1544848 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1544848 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27090401500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 27090401500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844259187 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844259187 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 932500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 932500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28934660687 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 28934660687 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28935593187 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28935593187 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015830 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015830 # mshr miss rate for ReadReq accesses
842,865c842,865
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.009307 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20466.744191 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20466.744191 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.012708 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.012708 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115454.545455 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115454.545455 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18734.686862 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18734.686862 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.376227 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.376227 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 725912 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.812539 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 81490807 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 726424 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 112.180775 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 347441500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.812539 # Average occupied blocks per requestor
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000100 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009323 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.009323 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009319 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.009319 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20458.803197 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20458.803197 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.521326 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.521326 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 133214.285714 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 133214.285714 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18729.863259 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18729.863259 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18730.382010 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 18730.382010 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 727442 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.812488 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 81555981 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 727954 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 112.034526 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 348938500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.812488 # Average occupied blocks per requestor
869,873c869,873
< system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 97 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 98 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 67 # Occupied blocks per task id
875,916c875,916
< system.cpu.icache.tags.tag_accesses 165175152 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 165175152 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 81490807 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 81490807 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 81490807 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 81490807 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 81490807 # number of overall hits
< system.cpu.icache.overall_hits::total 81490807 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 733549 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 733549 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 733549 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 733549 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 733549 # number of overall misses
< system.cpu.icache.overall_misses::total 733549 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 8424023442 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 8424023442 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 8424023442 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 8424023442 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 8424023442 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 8424023442 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 82224356 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 82224356 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 82224356 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 82224356 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 82224356 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 82224356 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008921 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.008921 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.008921 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.008921 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.008921 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.008921 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.927375 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 11483.927375 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 11483.927375 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 11483.927375 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 138949 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 4383 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 165310431 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 165310431 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 81555981 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 81555981 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 81555981 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 81555981 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 81555981 # number of overall hits
> system.cpu.icache.overall_hits::total 81555981 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 735249 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 735249 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 735249 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 735249 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 735249 # number of overall misses
> system.cpu.icache.overall_misses::total 735249 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 8470113937 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 8470113937 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 8470113937 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 8470113937 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 8470113937 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 8470113937 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 82291230 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 82291230 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 82291230 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 82291230 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 82291230 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 82291230 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008935 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008935 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008935 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008935 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008935 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008935 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11520.061825 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 11520.061825 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 11520.061825 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 11520.061825 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 144128 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 153 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 4365 # number of cycles access was blocked
918,955c918,955
< system.cpu.icache.avg_blocked_cycles::no_mshrs 31.701802 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 725912 # number of writebacks
< system.cpu.icache.writebacks::total 725912 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7108 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 7108 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 7108 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 7108 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 7108 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 7108 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726441 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 726441 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 726441 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 726441 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 726441 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 726441 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7897580451 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 7897580451 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7897580451 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 7897580451 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7897580451 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 7897580451 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008835 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.008835 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.008835 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10871.606161 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10871.606161 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 403113 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 403204 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 83 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 33.019015 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 51 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 727442 # number of writebacks
> system.cpu.icache.writebacks::total 727442 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7277 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 7277 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 7277 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 7277 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 7277 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 7277 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 727972 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 727972 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 727972 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 727972 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 727972 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 727972 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7937418446 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 7937418446 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7937418446 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 7937418446 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7937418446 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 7937418446 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008846 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.008846 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.008846 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10903.466680 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10903.466680 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10903.466680 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 10903.466680 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10903.466680 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 10903.466680 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 402290 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 402345 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue
958,959c958,959
< system.cpu.l2cache.prefetcher.pfSpanPage 28036 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.prefetcher.pfSpanPage 28015 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
961,964c961,964
< system.cpu.l2cache.tags.tagsinuse 5234.159238 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1826320 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 6292 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 290.260648 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 5251.876732 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1819467 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 6313 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 288.209568 # Average number of references to valid blocks.
966,972c966,972
< system.cpu.l2cache.tags.occ_blocks::writebacks 5154.317005 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 79.842232 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.314595 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004873 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.319468 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 172 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 6120 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 5160.149937 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 91.726796 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.314951 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005599 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.320549 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 185 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 6128 # Occupied blocks per task id
976,990c976,991
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 90 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 747 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 544 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010498 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373535 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 70559178 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 70559178 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 968252 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 968252 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1046027 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1046027 # number of WritebackClean hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 547 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 740 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 550 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4130 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011292 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.374023 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 70659625 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 70659625 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 968794 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 968794 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1048519 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1048519 # number of WritebackClean hits
993,1018c994,1019
< system.cpu.l2cache.ReadExReq_hits::cpu.data 219941 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 219941 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696850 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 696850 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094381 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1094381 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 696850 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1314322 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2011172 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 696850 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1314322 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2011172 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 789 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 789 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29509 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 29509 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228201 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 228201 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 29509 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 258499 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 29509 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses
< system.cpu.l2cache.overall_misses::total 258499 # number of overall misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 219908 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 219908 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 698283 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 698283 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1095997 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1095997 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 698283 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1315905 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2014188 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 698283 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1315905 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2014188 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 790 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 790 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29612 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 29612 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228134 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 228134 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 29612 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 228924 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 258536 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 29612 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 228924 # number of overall misses
> system.cpu.l2cache.overall_misses::total 258536 # number of overall misses
1021,1078c1022,1079
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69993500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 69993500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2629297500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2629297500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17936282000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 17936282000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2629297500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 18006275500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 20635573000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2629297500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 18006275500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 20635573000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 968252 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 968252 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1046027 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1046027 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 220730 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 220730 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726359 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 726359 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322582 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1322582 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 726359 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1543312 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2269671 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 726359 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1543312 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2269671 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.944444 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.944444 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003575 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.003575 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040626 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040626 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172542 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172542 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040626 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.113893 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040626 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.113893 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2529.411765 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2529.411765 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88711.660330 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88711.660330 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89101.545291 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89101.545291 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78598.612627 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78598.612627 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79828.444211 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79828.444211 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70196000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 70196000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2658292500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2658292500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17944343500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 17944343500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2658292500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 18014539500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20672832000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2658292500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 18014539500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20672832000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 968794 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 968794 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1048519 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1048519 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 220698 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 220698 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 727895 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 727895 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1324131 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1324131 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 727895 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1544829 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2272724 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 727895 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1544829 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2272724 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003580 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.003580 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040682 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040682 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172290 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172290 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040682 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.148187 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.113756 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040682 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.148187 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.113756 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2388.888889 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2388.888889 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88855.696203 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88855.696203 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89770.785492 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89770.785492 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78657.032709 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78657.032709 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79961.135006 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79961.135006 # average overall miss latency
1085,1086c1086,1087
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 56 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 56 # number of ReadExReq MSHR hits
---
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 55 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 55 # number of ReadExReq MSHR hits
1089,1090c1090,1091
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 35 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits
---
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 36 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 36 # number of ReadSharedReq MSHR hits
1097,1130c1098,1131
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54181 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 54181 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 733 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 733 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29498 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29498 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228166 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228166 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 29498 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 228899 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 258397 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 29498 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 228899 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54181 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 312578 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203172843 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 265000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 265000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63769500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63769500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2451726000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2451726000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16564497500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16564497500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2451726000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16628267000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19079993000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2451726000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16628267000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19283165843 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54077 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 54077 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 735 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 735 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29601 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29601 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228098 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228098 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 29601 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 228833 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 258434 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 29601 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 228833 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54077 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 312511 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203156315 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 279000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 279000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64169000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64169000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2480103000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2480103000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16573484500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16573484500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2480103000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16637653500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19117756500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2480103000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16637653500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19320912815 # number of overall MSHR miss cycles
1133,1145c1134,1146
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003321 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003321 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040611 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172516 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172516 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.113848 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003330 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003330 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040667 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172262 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172262 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.113711 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for overall accesses
1147,1169c1148,1170
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.137720 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3749.890977 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15588.235294 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15588.235294 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86997.953615 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86997.953615 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83114.990847 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83114.990847 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72598.448060 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72598.448060 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73839.839472 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61690.732691 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 4538483 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268732 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254880 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 51558 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51557 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.137505 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3756.797067 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87304.761905 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87304.761905 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83784.432958 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83784.432958 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72659.490658 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72659.490658 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73975.392170 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61824.744777 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 4544579 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2271779 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 51433 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51432 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1171,1192c1172,1193
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 2049022 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 968252 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1300460 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 55547 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 726441 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322582 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2178711 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629460 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6808171 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92945280 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 290456448 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 55629 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 2325318 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.131791 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.338265 # Request fanout histogram
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 2052102 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 968794 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1302965 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 55467 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 220698 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 220698 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 727972 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324131 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2183308 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4634013 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6817321 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93141504 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197705344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 290846848 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 55544 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 4928 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 2328287 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.131576 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.338031 # Request fanout histogram
1194,1195c1195,1196
< system.cpu.toL2Bus.snoop_fanout::0 2018862 86.82% 86.82% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 306455 13.18% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2021941 86.84% 86.84% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 306345 13.16% 100.00% # Request fanout histogram
1200,1203c1201,1204
< system.cpu.toL2Bus.snoop_fanout::total 2325318 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4537953500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 3.6 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 1089727365 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2328287 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4544048500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 1092026360 # Layer occupancy (ticks)
1205c1206
< system.cpu.toL2Bus.respLayer1.occupancy 2314999455 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2317274956 # Layer occupancy (ticks)
1207,1208c1208,1209
< system.membus.snoop_filter.tot_requests 261037 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 261096 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 253777 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1213,1222c1214,1223
< system.membus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 260286 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 17 # Transaction distribution
< system.membus.trans_dist::ReadExReq 733 # Transaction distribution
< system.membus.trans_dist::ReadExResp 733 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 260287 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522056 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 522056 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16705216 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 16705216 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 260342 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 18 # Transaction distribution
> system.membus.trans_dist::ReadExReq 735 # Transaction distribution
> system.membus.trans_dist::ReadExResp 735 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 260343 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522173 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 522173 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16708928 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 16708928 # Cumulative packet size per connected master and slave (bytes)
1225c1226
< system.membus.snoop_fanout::samples 261037 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 261096 # Request fanout histogram
1229c1230
< system.membus.snoop_fanout::0 261037 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 261096 100.00% 100.00% # Request fanout histogram
1234,1235c1235,1236
< system.membus.snoop_fanout::total 261037 # Request fanout histogram
< system.membus.reqLayer0.occupancy 316168930 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 261096 # Request fanout histogram
> system.membus.reqLayer0.occupancy 316188421 # Layer occupancy (ticks)
1237c1238
< system.membus.respLayer1.occupancy 1389509080 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1389693354 # Layer occupancy (ticks)