3,5c3,5
< sim_seconds 0.120480 # Number of seconds simulated
< sim_ticks 120480458500 # Number of ticks simulated
< final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.122178 # Number of seconds simulated
> sim_ticks 122177531500 # Number of ticks simulated
> final_tick 122177531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 129515 # Simulator instruction rate (inst/s)
< host_op_rate 155497 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 57149813 # Simulator tick rate (ticks/s)
< host_mem_usage 293332 # Number of bytes of host memory used
< host_seconds 2108.15 # Real time elapsed on the host
---
> host_inst_rate 120262 # Simulator instruction rate (inst/s)
> host_op_rate 144388 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 53814187 # Simulator tick rate (ticks/s)
> host_mem_usage 292180 # Number of bytes of host memory used
> host_seconds 2270.36 # Real time elapsed on the host
16,37c16,37
< system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory
< system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 261052 # Number of read requests accepted
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 1888192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 14650048 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 169280 # Number of bytes read from this memory
> system.physmem.bytes_read::total 16707520 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1888192 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1888192 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 29503 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 228907 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 2645 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 261055 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 15454495 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 119907874 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 1385525 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 136747893 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 15454495 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 15454495 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 15454495 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 119907874 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 1385525 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 136747893 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 261056 # Number of read requests accepted
39c39
< system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 261056 # Number of DRAM read bursts, including those serviced by the write queue
41c41
< system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 16707584 # Total number of bytes read from DRAM
44c44
< system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 16707584 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::0 1258 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 1259 # Per bank write bursts
52c52
< system.physmem.perBankRdBursts::3 10757 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 10759 # Per bank write bursts
54c54
< system.physmem.perBankRdBursts::5 121820 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 121819 # Per bank write bursts
56,57c56,57
< system.physmem.perBankRdBursts::7 266 # Per bank write bursts
< system.physmem.perBankRdBursts::8 224 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 257 # Per bank write bursts
> system.physmem.perBankRdBursts::8 228 # Per bank write bursts
63,64c63,64
< system.physmem.perBankRdBursts::14 656 # Per bank write bursts
< system.physmem.perBankRdBursts::15 609 # Per bank write bursts
---
> system.physmem.perBankRdBursts::14 662 # Per bank write bursts
> system.physmem.perBankRdBursts::15 610 # Per bank write bursts
83c83
< system.physmem.totGap 120480449000 # Total gap between requests
---
> system.physmem.totGap 122177522000 # Total gap between requests
90c90
< system.physmem.readPktSize::6 261052 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 261056 # Read request sizes (log2)
98,111c98,111
< system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 204133 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 43349 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 176 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 19 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see
194,211c194,211
< system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation
< system.physmem.totQLat 2500931533 # Total ticks spent queuing
< system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 67229 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 248.480388 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 181.727737 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 204.056429 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 18253 27.15% 27.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 21438 31.89% 59.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 11486 17.08% 76.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 6691 9.95% 86.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4636 6.90% 92.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2199 3.27% 96.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1378 2.05% 98.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 426 0.63% 98.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 722 1.07% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 67229 # Bytes accessed per row activation
> system.physmem.totQLat 4621160381 # Total ticks spent queuing
> system.physmem.totMemAccLat 9515960381 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1305280000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 17701.80 # Average queueing delay per DRAM burst
213,214c213,214
< system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 36451.80 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 136.75 # Average DRAM read bandwidth in MiByte/s
216c216
< system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 136.75 # Average system read bandwidth in MiByte/s
219,220c219,220
< system.physmem.busUtil 1.08 # Data bus utilization in percentage
< system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 1.07 # Data bus utilization in percentage
> system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads
224c224
< system.physmem.readRowHits 193998 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 193817 # Number of row buffer hits during reads
226c226
< system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 74.24 # Row buffer hit rate for reads
228,232c228,232
< system.physmem.avgGap 461518.97 # Average gap between requests
< system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 468012.69 # Average gap between requests
> system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 445443180 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 236747280 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1773933000 # Energy for read commands per rank (pJ)
234,246c234,251
< system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ)
< system.physmem_0.averagePower 762.514125 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states
< system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 9531222480.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4632019500 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 224464800 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 45099806190 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 3562907040 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 919525950 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 66426265230 # Total energy per rank (pJ)
> system.physmem_0.averagePower 543.686420 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 111434381144 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 154081000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 4033332000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 3253133750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 9278182481 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 6555604606 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 98903197663 # Time in different power states
> system.physmem_1.actEnergy 34636140 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 18382980 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 89999700 # Energy for read commands per rank (pJ)
248,263c253,273
< system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ)
< system.physmem_1.averagePower 683.872818 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states
< system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 35971487 # Number of BP lookups
< system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits
---
> system.physmem_1.refreshEnergy 3038165520.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 716380560 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 121415040 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 10108537890 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 3723173760 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 21583783695 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 39434924925 # Total energy per rank (pJ)
> system.physmem_1.averagePower 322.767403 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 120289757500 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 194586000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1289158000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 88425719250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 9695988513 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 404030000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 22168049737 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 35971486 # Number of BP lookups
> system.cpu.branchPred.condPredicted 19267078 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 984296 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17894197 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13923261 # Number of BTB hits
265,266c275,276
< system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 77.808806 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6951889 # Number of times the RAS was used to get a target.
268c278
< system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 2517219 # Number of indirect predictor lookups.
270,271c280,281
< system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectMisses 43864 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 128904 # Number of mispredicted indirect branches.
273c283
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
303c313
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
333c343
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
363c373
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
394,395c404,405
< system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 240960918 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 244355064 # number of cpu cycles simulated
398,404c408,414
< system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.icacheStallCycles 12854090 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 309386185 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 35971486 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 23348505 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 227028352 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1990311 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 1601 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
406,411c416,421
< system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 3162 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 82203694 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 34298 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 240882453 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.544883 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.296552 # Number of instructions fetched each cycle (Total)
413,416c423,426
< system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 80675861 33.49% 33.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 40201773 16.69% 50.18% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 28081031 11.66% 61.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 91923788 38.16% 100.00% # Number of instructions fetched each cycle (Total)
420,448c430,458
< system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 240882453 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.147210 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.266134 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 26812973 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 90710528 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 98252382 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 24245286 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 861284 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 6686689 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 134210 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 348538542 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 3411137 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 861284 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 43083632 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 37000044 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 289266 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 105269732 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 54378495 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 344597413 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 1451618 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 7112089 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 85489 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 7460814 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 27903739 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 3277402 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 394869828 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2218091968 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 335911643 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 192912802 # Number of floating rename lookups
450c460
< system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 22639780 # Number of HB maps that are undone due to squashing
452,467c462,477
< system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle
---
> system.cpu.rename.tempSerializingInsts 11574 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 57375410 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 89984183 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 84392474 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1977179 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1898949 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 343275804 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 22622 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 339466020 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 967573 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 15486826 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 37253539 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 502 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 240882453 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.409260 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.140571 # Number of insts issued each cycle
469,475c479,485
< system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 60724616 25.21% 25.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 76160793 31.62% 56.83% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 59430978 24.67% 81.50% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 34569007 14.35% 95.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 9283720 3.85% 99.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 678664 0.28% 99.99% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 34675 0.01% 100.00% # Number of insts issued each cycle
481c491
< system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 240882453 # Number of insts issued each cycle
483,484c493,494
< system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9218221 7.75% 7.75% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 7322 0.01% 7.76% # attempts to use FU when none available
503c513
< system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatAdd 238834 0.20% 7.96% # attempts to use FU when none available
505,513c515,523
< system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatCmp 138891 0.12% 8.08% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 70679 0.06% 8.14% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 68365 0.06% 8.19% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 640804 0.54% 8.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 296732 0.25% 8.98% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 541759 0.46% 9.44% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 51504063 43.31% 52.75% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 56187426 47.25% 100.00% # attempts to use FU when none available
517,518c527,528
< system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 108184064 31.87% 31.87% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2148340 0.63% 32.50% # Type of FU issued
537c547
< system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatAdd 6792701 2.00% 34.50% # Type of FU issued
539,540c549,550
< system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCmp 8634973 2.54% 37.05% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 3210554 0.95% 37.99% # Type of FU issued
542,544c552,554
< system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 20863316 6.15% 44.61% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 7179113 2.11% 46.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141894 2.10% 48.83% # Type of FU issued
546,547c556,557
< system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 90024187 26.52% 75.40% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 83518595 24.60% 100.00% # Type of FU issued
550,562c560,572
< system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued
< system.cpu.iq.rate 1.408797 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 339466020 # Type of FU issued
> system.cpu.iq.rate 1.389233 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 118913096 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.350295 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 756328552 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 235151256 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 219171646 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 283366610 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 123646075 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 116917582 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 293624810 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 164754306 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5408815 # Number of loads that had data forwarded from stores
564,565c574,575
< system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 4251908 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 7378 # Number of memory responses ignored because the instruction is squashed
567c577
< system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 2016857 # Number of stores squashed
570,571c580,581
< system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 126936 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 613330 # Number of times an access to memory failed due to the cache being blocked
573,576c583,586
< system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 861284 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1350225 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1508994 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 343299844 # Number of instructions dispatched to IQ
578,582c588,592
< system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewDispLoadInsts 89984183 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 84392474 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 11589 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 7652 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 1502014 # Number of times the LSQ has become full, causing a stall
584,589c594,599
< system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedTakenIncorrect 438026 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 454508 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 892534 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 337437017 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 89435625 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 2029003 # Number of squashed instructions skipped in execute
591,602c601,612
< system.cpu.iew.exec_nop 1419 # number of nop insts executed
< system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed
< system.cpu.iew.exec_branches 31555788 # Number of branches executed
< system.cpu.iew.exec_stores 83127697 # Number of stores executed
< system.cpu.iew.exec_rate 1.400376 # Inst execution rate
< system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 151781597 # num instructions producing a value
< system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 1418 # number of nop insts executed
> system.cpu.iew.exec_refs 172563316 # number of memory reference insts executed
> system.cpu.iew.exec_branches 31556143 # Number of branches executed
> system.cpu.iew.exec_stores 83127691 # Number of stores executed
> system.cpu.iew.exec_rate 1.380929 # Inst execution rate
> system.cpu.iew.wb_sent 336235772 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 336089228 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 151786231 # num instructions producing a value
> system.cpu.iew.wb_consumers 263562514 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.375413 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.575902 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 14164375 # The number of squashed insts skipped by commit
604,607c614,617
< system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 850425 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 238692959 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.373364 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.035708 # Number of insts commited each cycle
609,617c619,627
< system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 107534765 45.05% 45.05% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 67583251 28.31% 73.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 20880103 8.75% 82.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 13256001 5.55% 87.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 8658859 3.63% 91.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 4515867 1.89% 93.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 3014415 1.26% 94.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 2598093 1.09% 95.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 10651605 4.46% 100.00% # Number of insts commited each cycle
621c631
< system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 238692959 # Number of insts commited each cycle
667,671c677,681
< system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 567267171 # The number of ROB reads
< system.cpu.rob.rob_writes 686142351 # The number of ROB writes
< system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 10651605 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 570015418 # The number of ROB reads
> system.cpu.rob.rob_writes 686144847 # The number of ROB writes
> system.cpu.timesIdled 39403 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 3472611 # Total number of cycles that the CPU has spent unscheduled due to idling
674,684c684,694
< system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 325162337 # number of integer regfile reads
< system.cpu.int_regfile_writes 134093699 # number of integer regfile writes
< system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads
< system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes
< system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads
< system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes
< system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads
---
> system.cpu.cpi 0.894951 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.894951 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.117379 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.117379 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 325163205 # number of integer regfile reads
> system.cpu.int_regfile_writes 134094196 # number of integer regfile writes
> system.cpu.fp_regfile_reads 186638267 # number of floating regfile reads
> system.cpu.fp_regfile_writes 131663703 # number of floating regfile writes
> system.cpu.cc_regfile_reads 1279409265 # number of cc regfile reads
> system.cpu.cc_regfile_writes 80058845 # number of cc regfile writes
> system.cpu.misc_regfile_reads 1056731782 # number of misc regfile reads
686,695c696,705
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 1542807 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 1542799 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.841241 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 162053309 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1543311 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 105.003664 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.841241 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999690 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999690 # Average percentage of cache occupancy
697,699c707,709
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id
702,710c712,720
< system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 333480485 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 333480485 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 81040424 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 81040424 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 80921391 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 80921391 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 69631 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 69631 # number of SoftPFReq hits
715,722c725,732
< system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits
< system.cpu.dcache.overall_hits::total 162030636 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 161961815 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 161961815 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 162031446 # number of overall hits
> system.cpu.dcache.overall_hits::total 162031446 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2784008 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2784008 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1131308 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1131308 # number of WriteReq misses
727,742c737,752
< system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses
< system.cpu.dcache.overall_misses::total 3915377 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 3915316 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3915316 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3915334 # number of overall misses
> system.cpu.dcache.overall_misses::total 3915334 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 47872980500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 47872980500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9172353414 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9172353414 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 57045333914 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 57045333914 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 57045333914 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 57045333914 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 83824432 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 83824432 # number of ReadReq accesses(hits+misses)
745,746c755,756
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 69649 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 69649 # number of SoftPFReq accesses(hits+misses)
751,756c761,766
< system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 165877131 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 165877131 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 165946780 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 165946780 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033212 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
767,776c777,786
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8107.742024 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 8107.742024 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14569.790513 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14569.723532 # average overall miss latency
778c788
< system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 1090477 # number of cycles access was blocked
780c790
< system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 136210 # number of cycles access was blocked
782,788c792,798
< system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks
< system.cpu.dcache.writebacks::total 1542807 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 8.005851 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 1542799 # number of writebacks
> system.cpu.dcache.writebacks::total 1542799 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461435 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1461435 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910564 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 910564 # number of WriteReq MSHR hits
791,796c801,806
< system.cpu.dcache.demand_mshr_hits::cpu.data 2372034 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2372034 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2372034 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2372034 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322581 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1322581 # number of ReadReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 2371999 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2371999 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2371999 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2371999 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322573 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1322573 # number of ReadReq MSHR misses
801,814c811,824
< system.cpu.dcache.demand_mshr_misses::cpu.data 1543325 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1543325 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1543336 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1543336 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25407816000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 25407816000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1834277181 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1834277181 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 705000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 705000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27242093181 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 27242093181 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27242798181 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 27242798181 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 1543317 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1543317 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1543328 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1543328 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27142024000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 27142024000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845028694 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845028694 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28987052694 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 28987052694 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28988321694 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28988321694 # number of overall MSHR miss cycles
825,844c835,854
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8309.522257 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8309.522257 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 725593 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.815316 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 81471161 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 726105 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 112.203002 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 334835500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.815316 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999639 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999639 # Average percentage of cache occupancy
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20522.136774 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20522.136774 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8358.228056 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8358.228056 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18782.306353 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18782.306353 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18782.994732 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 18782.994732 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 725588 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.809147 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 81470653 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 726100 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 112.203075 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 346654500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.809147 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999627 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999627 # Average percentage of cache occupancy
852,893c862,903
< system.cpu.icache.tags.tag_accesses 165134244 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 165134244 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 81471161 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 81471161 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 81471161 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 81471161 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 81471161 # number of overall hits
< system.cpu.icache.overall_hits::total 81471161 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 732901 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 732901 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 732901 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 732901 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 732901 # number of overall misses
< system.cpu.icache.overall_misses::total 732901 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 8031652441 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 8031652441 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 8031652441 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 8031652441 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 8031652441 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 8031652441 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 82204062 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 82204062 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 82204062 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 82204062 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 82204062 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 82204062 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008916 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.008916 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.008916 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.008916 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.008916 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.008916 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 10958.713989 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 10958.713989 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 128534 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 4274 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 165133459 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 165133459 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 81470653 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 81470653 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 81470653 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 81470653 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 81470653 # number of overall hits
> system.cpu.icache.overall_hits::total 81470653 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 733019 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 733019 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 733019 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 733019 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 733019 # number of overall misses
> system.cpu.icache.overall_misses::total 733019 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 8417582442 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 8417582442 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 8417582442 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 8417582442 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 8417582442 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 8417582442 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 82203672 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 82203672 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 82203672 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 82203672 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 82203672 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 82203672 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008917 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008917 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008917 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008917 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008917 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008917 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.443733 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 11483.443733 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 11483.443733 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 11483.443733 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 142274 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 4376 # number of cycles access was blocked
895,916c905,926
< system.cpu.icache.avg_blocked_cycles::no_mshrs 30.073467 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 33.333333 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 725593 # number of writebacks
< system.cpu.icache.writebacks::total 725593 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6780 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 6780 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 6780 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 6780 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 6780 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 6780 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726121 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 726121 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 726121 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 726121 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 726121 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 726121 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7527879949 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 7527879949 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7527879949 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 7527879949 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7527879949 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 7527879949 # number of overall MSHR miss cycles
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 32.512340 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 725588 # number of writebacks
> system.cpu.icache.writebacks::total 725588 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6903 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 6903 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 6903 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 6903 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 6903 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 6903 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726116 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 726116 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 726116 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 726116 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 726116 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 726116 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7892899950 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 7892899950 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7892899950 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 7892899950 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7892899950 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 7892899950 # number of overall MSHR miss cycles
923,932c933,942
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 402848 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 402975 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 113 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10870.026208 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10870.026208 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 404432 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 404544 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue
935,936c945,946
< system.cpu.l2cache.prefetcher.pfSpanPage 27937 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.prefetcher.pfSpanPage 28328 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
938,941c948,951
< system.cpu.l2cache.tags.tagsinuse 5253.562311 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1811987 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 6314 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 286.979252 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 5246.342429 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1813751 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 6313 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 287.304134 # Average number of references to valid blocks.
943,947c953,957
< system.cpu.l2cache.tags.occ_blocks::writebacks 5154.206528 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 99.355783 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.314588 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006064 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.320652 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 5152.962075 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 93.380354 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.314512 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005699 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.320211 # Average percentage of cache occupancy
949,950c959,960
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 6122 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 6121 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id
953,958c963,969
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 110 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 555 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1137 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 139 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4125 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 103 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1140 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 141 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id
960,967c971,978
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373657 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 70548606 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 70548606 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 968253 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 968253 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1045699 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1045699 # number of WritebackClean hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373596 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 70548166 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 70548166 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 968244 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 968244 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1045693 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1045693 # number of WritebackClean hits
970,981c981,992
< system.cpu.l2cache.ReadExReq_hits::cpu.data 219932 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 219932 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696525 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 696525 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094373 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1094373 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 696525 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1314305 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2010830 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 696525 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1314305 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2010830 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 219960 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 219960 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696520 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 696520 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094361 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1094361 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 696520 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1314321 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2010841 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 696520 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1314321 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2010841 # number of overall hits
984,985c995,996
< system.cpu.l2cache.ReadExReq_misses::cpu.data 807 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 807 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 779 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 779 # number of ReadExReq misses
988,989c999,1000
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228207 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 228207 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228211 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 228211 # number of ReadSharedReq misses
991,992c1002,1003
< system.cpu.l2cache.demand_misses::cpu.data 229014 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 258529 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 258505 # number of demand (read+write) misses
994,995c1005,1006
< system.cpu.l2cache.overall_misses::cpu.data 229014 # number of overall misses
< system.cpu.l2cache.overall_misses::total 258529 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses
> system.cpu.l2cache.overall_misses::total 258505 # number of overall misses
998,1013c1009,1024
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59970500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 59970500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2262045500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2262045500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16271473000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 16271473000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2262045500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 16331443500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 18593489000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2262045500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 16331443500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 18593489000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 968253 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 968253 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1045699 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1045699 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70551500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 70551500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2627115000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2627115000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18006396500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 18006396500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2627115000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 18076948000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20704063000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2627115000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 18076948000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20704063000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 968244 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 968244 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1045693 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1045693 # number of WritebackClean accesses(hits+misses)
1018,1027c1029,1038
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726040 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 726040 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322580 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1322580 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 726040 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1543319 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2269359 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 726040 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1543319 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2269359 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726035 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 726035 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322572 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1322572 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 726035 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1543311 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2269346 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 726035 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1543311 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2269346 # number of overall (read+write) accesses
1030,1031c1041,1042
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003656 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.003656 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003529 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.003529 # miss rate for ReadExReq accesses
1034,1035c1045,1046
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172547 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172547 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172551 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172551 # miss rate for ReadSharedReq accesses
1037,1038c1048,1049
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.148391 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.113922 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.113912 # miss rate for demand accesses
1040,1041c1051,1052
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.148391 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.113922 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.113912 # miss rate for overall accesses
1044,1055c1055,1066
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74312.887237 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74312.887237 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76640.538709 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76640.538709 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71301.375506 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71301.375506 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76640.538709 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71311.987477 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71920.322285 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76640.538709 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71311.987477 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71920.322285 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90566.752246 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90566.752246 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89009.486702 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89009.486702 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78902.403916 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78902.403916 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89009.486702 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78942.084807 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80091.537881 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89009.486702 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78942.084807 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80091.537881 # average overall miss latency
1062,1075c1073,1086
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 50 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 50 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 36 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 36 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 99 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 99 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54157 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 54157 # number of HardPFReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 49 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 49 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 83 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 83 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 94 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54467 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 54467 # number of HardPFReq MSHR misses
1078,1092c1089,1103
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 757 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 757 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29502 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29502 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228171 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228171 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 29502 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 228928 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 258430 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 29502 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 228928 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54157 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 312587 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 187753381 # number of HardPFReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29504 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29504 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228177 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228177 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 29504 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 228907 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 258411 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 29504 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 228907 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54467 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 312878 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 206471258 # number of HardPFReq MSHR miss cycles
1095,1107c1106,1118
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53315000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53315000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2084473500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2084473500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14900259000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14900259000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2084473500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14953574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17038047500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2084473500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14953574000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17225800881 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64550000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64550000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2449507500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2449507500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16634852500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16634852500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2449507500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16699402500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19148910000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2449507500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16699402500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19355381258 # number of overall MSHR miss cycles
1112,1122c1123,1133
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040637 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172525 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172525 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.113870 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for overall accesses
1124,1126c1135,1137
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.137871 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3790.758771 # average HardPFReq mshr miss latency
1129,1146c1140,1157
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 4537831 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268421 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 51822 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51821 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1148,1152c1159,1163
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 2048687 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 968244 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1300143 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 55841 # Transaction distribution
1157,1165c1168,1176
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 55606 # Total snoops (count)
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 726116 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322572 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177738 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629455 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6807193 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92903808 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511040 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 290414848 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 55922 # Total snoops (count)
1167,1169c1178,1180
< system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 2325285 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.131736 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.338205 # Request fanout histogram
1171,1172c1182,1183
< system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2018962 86.83% 86.83% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 306322 13.17% 100.00% # Request fanout histogram
1177,1180c1188,1191
< system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2325285 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4537302500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 1089460423 # Layer occupancy (ticks)
1182c1193
< system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2314997455 # Layer occupancy (ticks)
1184,1185c1195,1196
< system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 261072 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 253753 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1190,1191c1201,1202
< system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 260294 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 260325 # Transaction distribution
1193,1199c1204,1210
< system.membus.trans_dist::ReadExReq 757 # Transaction distribution
< system.membus.trans_dist::ReadExResp 757 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 730 # Transaction distribution
> system.membus.trans_dist::ReadExResp 730 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 260326 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522127 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 522127 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707520 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 16707520 # Cumulative packet size per connected master and slave (bytes)
1202c1213
< system.membus.snoop_fanout::samples 261068 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 261072 # Request fanout histogram
1206c1217
< system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 261072 100.00% 100.00% # Request fanout histogram
1211,1212c1222,1223
< system.membus.snoop_fanout::total 261068 # Request fanout histogram
< system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 261072 # Request fanout histogram
> system.membus.reqLayer0.occupancy 329884354 # Layer occupancy (ticks)
1214c1225
< system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 1377672131 # Layer occupancy (ticks)