3,5c3,5
< sim_seconds 0.112686 # Number of seconds simulated
< sim_ticks 112686104500 # Number of ticks simulated
< final_tick 112686104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.112687 # Number of seconds simulated
> sim_ticks 112687034500 # Number of ticks simulated
> final_tick 112687034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 125538 # Simulator instruction rate (inst/s)
< host_op_rate 150722 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 51811162 # Simulator tick rate (ticks/s)
< host_mem_usage 327864 # Number of bytes of host memory used
< host_seconds 2174.94 # Real time elapsed on the host
---
> host_inst_rate 126437 # Simulator instruction rate (inst/s)
> host_op_rate 151802 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 52182660 # Simulator tick rate (ticks/s)
> host_mem_usage 327844 # Number of bytes of host memory used
> host_seconds 2159.47 # Real time elapsed on the host
17,19c17,19
< system.physmem.bytes_read::cpu.data 112896 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 167936 # Number of bytes read from this memory
< system.physmem.bytes_read::total 467904 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 112448 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 169152 # Number of bytes read from this memory
> system.physmem.bytes_read::total 468672 # Number of bytes read from this memory
23,36c23,36
< system.physmem.num_reads::cpu.data 1764 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 2624 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 7311 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1660116 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1001863 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 1490299 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4152278 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1660116 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1660116 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1660116 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1001863 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 1490299 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4152278 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7311 # Number of read requests accepted
---
> system.physmem.num_reads::cpu.data 1757 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 2643 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 7323 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1660102 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 997879 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 1501078 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4159059 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1660102 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1660102 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1660102 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 997879 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 1501078 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4159059 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7323 # Number of read requests accepted
38c38
< system.physmem.readBursts 7311 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7323 # Number of DRAM read bursts, including those serviced by the write queue
40c40
< system.physmem.bytesReadDRAM 467904 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 468672 # Total number of bytes read from DRAM
43c43
< system.physmem.bytesReadSys 467904 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 468672 # Total read bytes from the system interface side
55c55
< system.physmem.perBankRdBursts::7 252 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 251 # Per bank write bursts
63c63
< system.physmem.perBankRdBursts::15 542 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 555 # Per bank write bursts
82c82
< system.physmem.totGap 112685946000 # Total gap between requests
---
> system.physmem.totGap 112686876000 # Total gap between requests
89c89
< system.physmem.readPktSize::6 7311 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7323 # Read request sizes (log2)
97,100c97,100
< system.physmem.rdQLenPdf::0 3986 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 4012 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1463 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 286 # What read queue length does an incoming req see
102,111c102,111
< system.physmem.rdQLenPdf::5 200 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 175 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 198 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 151 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::5 210 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 170 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 170 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
193,210c193,210
< system.physmem.bytesPerActivate::samples 1367 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 340.646672 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 198.022122 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 348.529599 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 486 35.55% 35.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 298 21.80% 57.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 139 10.17% 67.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 76 5.56% 73.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 63 4.61% 77.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 51 3.73% 81.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 27 1.98% 83.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 26 1.90% 85.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 201 14.70% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1367 # Bytes accessed per row activation
< system.physmem.totQLat 102208518 # Total ticks spent queuing
< system.physmem.totMemAccLat 239289768 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 36555000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13980.10 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 339.932896 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 197.349943 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 349.457617 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 486 35.45% 35.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 309 22.54% 57.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 132 9.63% 67.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 75 5.47% 73.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 64 4.67% 77.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 48 3.50% 81.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 26 1.90% 83.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 25 1.82% 84.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 206 15.03% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation
> system.physmem.totQLat 95174041 # Total ticks spent queuing
> system.physmem.totMemAccLat 232480291 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 36615000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12996.59 # Average queueing delay per DRAM burst
212,213c212,213
< system.physmem.avgMemAccLat 32730.10 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31746.59 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s
215c215
< system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s
221c221
< system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing
223c223
< system.physmem.readRowHits 5935 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 5943 # Number of row buffer hits during reads
225c225
< system.physmem.readRowHitRate 81.18 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
227,228c227,228
< system.physmem.avgGap 15413205.58 # Average gap between requests
< system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 15388075.38 # Average gap between requests
> system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined
231c231
< system.physmem_0.readEnergy 28657200 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 28641600 # Energy for read commands per rank (pJ)
234,238c234,238
< system.physmem_0.actBackEnergy 3231673425 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 64774920750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 75402575040 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.157389 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 107755851914 # Time in different power states
---
> system.physmem_0.actBackEnergy 3233168820 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 64773630750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 75402764835 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.158858 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 107753956620 # Time in different power states
241c241
< system.physmem_0.memoryStateTime::ACT 1164613086 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1166688380 # Time in different power states
243,245c243,245
< system.physmem_1.actEnergy 5496120 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2998875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 28064400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5526360 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3015375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ)
248,252c248,252
< system.physmem_1.actBackEnergy 3295137510 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 64719250500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 75410827725 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.230627 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 107661884129 # Time in different power states
---
> system.physmem_1.actBackEnergy 3309876000 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 64706325000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 75412749855 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.247655 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 107640832624 # Time in different power states
255c255
< system.physmem_1.memoryStateTime::ACT 1258279621 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1279848380 # Time in different power states
257,261c257,261
< system.cpu.branchPred.lookups 37742989 # Number of BP lookups
< system.cpu.branchPred.condPredicted 20164516 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1746156 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18663196 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 17299233 # Number of BTB hits
---
> system.cpu.branchPred.lookups 37743135 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20164607 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1746155 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18663607 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 17299273 # Number of BTB hits
263,265c263,265
< system.cpu.branchPred.BTBHitPct 92.691697 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7223653 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 92.689870 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7223670 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
384c384
< system.cpu.numCycles 225372210 # number of cpu cycles simulated
---
> system.cpu.numCycles 225374070 # number of cpu cycles simulated
387,399c387,399
< system.cpu.fetch.icacheStallCycles 12439138 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 334051202 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 37742989 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 24522886 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 210855691 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 3510707 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 1284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 89092155 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 21708 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 225054059 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.800470 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.229417 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 12439227 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 334051995 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 37743135 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 24522943 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 210854521 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 3510703 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 1310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 2474 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 89092353 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 21704 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 225052883 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.800484 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.229411 # Number of instructions fetched each cycle (Total)
401,404c401,404
< system.cpu.fetch.rateDist::0 51374086 22.83% 22.83% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 42891136 19.06% 41.89% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 30054592 13.35% 55.24% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 100734245 44.76% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 51372314 22.83% 22.83% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 42891452 19.06% 41.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 30054577 13.35% 55.24% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 100734540 44.76% 100.00% # Number of instructions fetched each cycle (Total)
408,428c408,428
< system.cpu.fetch.rateDist::total 225054059 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.167470 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.482220 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 27837229 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 63912010 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 108618315 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 23065911 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1620594 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 6880048 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 363546099 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 6169805 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1620594 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 45200014 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 17874059 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 342377 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 113380979 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 46636036 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 355768136 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 2890465 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 6610669 # Number of times rename has blocked due to ROB full
---
> system.cpu.fetch.rateDist::total 225052883 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.167469 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.482211 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 27836779 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 63911722 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 108618516 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 23065273 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1620593 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 6880055 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 363544847 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 6170021 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1620593 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 45199707 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 17872689 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 341815 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 113380410 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 46637669 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 355768309 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 2890306 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 6609751 # Number of times rename has blocked due to ROB full
430,436c430,436
< system.cpu.rename.LQFullEvents 7803674 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 21223053 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 2890533 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 403406015 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2534023592 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 350247327 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 194894263 # Number of floating rename lookups
---
> system.cpu.rename.LQFullEvents 7804271 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 21223751 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 2890543 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 403406246 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2534025265 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 350247395 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 194894231 # Number of floating rename lookups
438c438
< system.cpu.rename.UndoneMaps 31175964 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 31176195 # Number of HB maps that are undone due to squashing
441,446c441,446
< system.cpu.rename.skidInsts 55505783 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 92416404 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 88498336 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1661010 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1846418 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 353252226 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.skidInsts 55506509 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 92416612 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 88498373 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1661373 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1847329 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 353252571 # Number of instructions added to the IQ (excludes non-spec)
448,451c448,451
< system.cpu.iq.iqInstsIssued 346438238 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 2301579 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 25468650 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 73725461 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 346438287 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 2302047 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 25468995 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 73729207 # Number of squashed operands that are examined and possibly removed from graph
453,455c453,455
< system.cpu.iq.issued_per_cycle::samples 225054059 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.539356 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.099855 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 225052883 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.539364 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.099868 # Number of insts issued each cycle
457,463c457,463
< system.cpu.iq.issued_per_cycle::0 40665072 18.07% 18.07% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 78300215 34.79% 52.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 60997700 27.10% 79.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 34882254 15.50% 95.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 9557051 4.25% 99.71% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 642945 0.29% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 8822 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 40665148 18.07% 18.07% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 78299865 34.79% 52.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 60995131 27.10% 79.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 34883362 15.50% 95.46% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 9557615 4.25% 99.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 642958 0.29% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 8804 0.00% 100.00% # Number of insts issued each cycle
469c469
< system.cpu.iq.issued_per_cycle::total 225054059 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 225052883 # Number of insts issued each cycle
471,472c471,472
< system.cpu.iq.fu_full::IntAlu 9490410 7.63% 7.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 7314 0.01% 7.64% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9490613 7.63% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 7317 0.01% 7.64% # attempts to use FU when none available
491c491
< system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.84% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatAdd 255761 0.21% 7.84% # attempts to use FU when none available
493,494c493,494
< system.cpu.iq.fu_full::SimdFloatCmp 126866 0.10% 7.95% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 93218 0.07% 8.02% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatCmp 126865 0.10% 7.95% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 93219 0.07% 8.02% # attempts to use FU when none available
496,498c496,498
< system.cpu.iq.fu_full::SimdFloatMisc 721741 0.58% 8.66% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 683043 0.55% 9.44% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatMisc 721837 0.58% 8.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.90% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 683044 0.55% 9.44% # attempts to use FU when none available
500,501c500,501
< system.cpu.iq.fu_full::MemRead 53642366 43.14% 52.58% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 58960700 47.42% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 53642383 43.14% 52.58% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 58959382 47.42% 100.00% # attempts to use FU when none available
505,506c505,506
< system.cpu.iq.FU_type_0::IntAlu 110655140 31.94% 31.94% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2148362 0.62% 32.56% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 110655137 31.94% 31.94% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2148355 0.62% 32.56% # Type of FU issued
525c525
< system.cpu.iq.FU_type_0::SimdFloatAdd 6798396 1.96% 34.52% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatAdd 6798397 1.96% 34.52% # Type of FU issued
527,528c527,528
< system.cpu.iq.FU_type_0::SimdFloatCmp 8668155 2.50% 37.03% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 3332481 0.96% 37.99% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCmp 8668117 2.50% 37.03% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued
530,531c530,531
< system.cpu.iq.FU_type_0::SimdFloatMisc 20930094 6.04% 44.49% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 7182326 2.07% 46.56% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 20930149 6.04% 44.49% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 7182320 2.07% 46.56% # Type of FU issued
534,535c534,535
< system.cpu.iq.FU_type_0::MemRead 91923219 26.53% 75.21% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 85883359 24.79% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 91923270 26.53% 75.21% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 85883354 24.79% 100.00% # Type of FU issued
538,550c538,550
< system.cpu.iq.FU_type_0::total 346438238 # Type of FU issued
< system.cpu.iq.rate 1.537183 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 124346666 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.358929 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 757024395 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 251740362 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 223260150 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 287554385 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 127018791 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 117424955 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 303230405 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 167554499 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5064919 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 346438287 # Type of FU issued
> system.cpu.iq.rate 1.537170 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 124345667 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.358926 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 757022758 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 251740405 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 223260402 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 287554413 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 127019437 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 117424930 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 303229780 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 167554174 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5064825 # Number of loads that had data forwarded from stores
552,555c552,555
< system.cpu.iew.lsq.thread0.squashedLoads 6684129 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 13573 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 10255 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 6122719 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 6684337 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 13570 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 10254 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 6122756 # Number of stores squashed
558,559c558,559
< system.cpu.iew.lsq.thread0.rescheduledLoads 155303 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 607776 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 155338 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 607759 # Number of times an access to memory failed due to the cache being blocked
561,564c561,564
< system.cpu.iew.iewSquashCycles 1620594 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 2118849 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 332046 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 353281117 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 1620593 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 2118874 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 332196 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 353281462 # Number of instructions dispatched to IQ
566,567c566,567
< system.cpu.iew.iewDispLoadInsts 92416404 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 88498336 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 92416612 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 88498373 # Number of dispatched store instructions
570,577c570,577
< system.cpu.iew.iewLSQFullEvents 338505 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 10255 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 1220656 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 439058 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1659714 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 342448377 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 90703712 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 3989861 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewLSQFullEvents 338656 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 10254 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 1220664 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 439075 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1659739 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 342448688 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 90703769 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 3989599 # Number of squashed instructions skipped in execute
580,587c580,587
< system.cpu.iew.exec_refs 175291126 # number of memory reference insts executed
< system.cpu.iew.exec_branches 31752707 # Number of branches executed
< system.cpu.iew.exec_stores 84587414 # Number of stores executed
< system.cpu.iew.exec_rate 1.519479 # Inst execution rate
< system.cpu.iew.wb_sent 340943800 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 340685105 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 153662327 # num instructions producing a value
< system.cpu.iew.wb_consumers 266738216 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 175291174 # number of memory reference insts executed
> system.cpu.iew.exec_branches 31752726 # Number of branches executed
> system.cpu.iew.exec_stores 84587405 # Number of stores executed
> system.cpu.iew.exec_rate 1.519468 # Inst execution rate
> system.cpu.iew.wb_sent 340944051 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 340685332 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 153662647 # num instructions producing a value
> system.cpu.iew.wb_consumers 266737544 # num instructions consuming a value
589,590c589,590
< system.cpu.iew.wb_rate 1.511655 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.576079 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.511644 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.576082 # average fanout of values written-back
592c592
< system.cpu.commit.commitSquashedInsts 23082519 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 23083260 # The number of squashed insts skipped by commit
595,597c595,597
< system.cpu.commit.committed_per_cycle::samples 221328864 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.481109 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.050764 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 221327720 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.481117 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.050757 # Number of insts commited each cycle
599,607c599,607
< system.cpu.commit.committed_per_cycle::0 87530154 39.55% 39.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 70479011 31.84% 71.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 20814829 9.40% 80.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 13433176 6.07% 86.86% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 8801116 3.98% 90.84% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 4514131 2.04% 92.88% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 2986629 1.35% 94.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 2449420 1.11% 95.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 10320398 4.66% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 87528718 39.55% 39.55% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 70478843 31.84% 71.39% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 20814822 9.40% 80.80% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 13433890 6.07% 86.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 8801339 3.98% 90.84% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 4513701 2.04% 92.88% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 2986759 1.35% 94.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 2449542 1.11% 95.34% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 10320106 4.66% 100.00% # Number of insts commited each cycle
611c611
< system.cpu.commit.committed_per_cycle::total 221328864 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 221327720 # Number of insts commited each cycle
657,661c657,661
< system.cpu.commit.bw_lim_events 10320398 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 561900676 # The number of ROB reads
< system.cpu.rob.rob_writes 705518580 # The number of ROB writes
< system.cpu.timesIdled 50864 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 318151 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 10320106 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 561900565 # The number of ROB reads
> system.cpu.rob.rob_writes 705520050 # The number of ROB writes
> system.cpu.timesIdled 50865 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 321187 # Total number of cycles that the CPU has spent unscheduled due to idling
664,674c664,674
< system.cpu.cpi 0.825427 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.825427 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.211495 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.211495 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 331331443 # number of integer regfile reads
< system.cpu.int_regfile_writes 136939322 # number of integer regfile writes
< system.cpu.fp_regfile_reads 187108010 # number of floating regfile reads
< system.cpu.fp_regfile_writes 132178699 # number of floating regfile writes
< system.cpu.cc_regfile_reads 1297132712 # number of cc regfile reads
< system.cpu.cc_regfile_writes 80241070 # number of cc regfile writes
< system.cpu.misc_regfile_reads 1183128145 # number of misc regfile reads
---
> system.cpu.cpi 0.825434 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.825434 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.211485 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.211485 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 331332035 # number of integer regfile reads
> system.cpu.int_regfile_writes 136939352 # number of integer regfile writes
> system.cpu.fp_regfile_reads 187107868 # number of floating regfile reads
> system.cpu.fp_regfile_writes 132178738 # number of floating regfile writes
> system.cpu.cc_regfile_reads 1297133606 # number of cc regfile reads
> system.cpu.cc_regfile_writes 80241640 # number of cc regfile writes
> system.cpu.misc_regfile_reads 1183127847 # number of misc regfile reads
677,678c677,678
< system.cpu.dcache.tags.tagsinuse 511.844014 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 163642665 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 511.843427 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 163642817 # Total number of references to valid blocks.
680,684c680,684
< system.cpu.dcache.tags.avg_refs 106.652275 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 82317000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.844014 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.avg_refs 106.652374 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 82681000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.843427 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy
691,698c691,698
< system.cpu.dcache.tags.tag_accesses 336636785 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 336636785 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 82609327 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 82609327 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 80941037 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 80941037 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 70495 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 70495 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 336637061 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 336637061 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 82609464 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 82609464 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 80941053 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 80941053 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 70494 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 70494 # number of SoftPFReq hits
703,710c703,710
< system.cpu.dcache.demand_hits::cpu.data 163550364 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 163550364 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 163620859 # number of overall hits
< system.cpu.dcache.overall_hits::total 163620859 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2796866 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2796866 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1111662 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1111662 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 163550517 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 163550517 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 163621011 # number of overall hits
> system.cpu.dcache.overall_hits::total 163621011 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2796868 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2796868 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1111646 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1111646 # number of WriteReq misses
715,722c715,722
< system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses
< system.cpu.dcache.overall_misses::total 3908546 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 22404027000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 22404027000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8967503998 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8967503998 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 3908514 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3908514 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3908532 # number of overall misses
> system.cpu.dcache.overall_misses::total 3908532 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 22403262000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 22403262000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8965991000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8965991000 # number of WriteReq miss cycles
725,730c725,730
< system.cpu.dcache.demand_miss_latency::cpu.data 31371530998 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31371530998 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31371530998 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31371530998 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 85406193 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 85406193 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 31369253000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31369253000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31369253000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31369253000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 85406332 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 85406332 # number of ReadReq accesses(hits+misses)
733,734c733,734
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 70513 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 70513 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 70512 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 70512 # number of SoftPFReq accesses(hits+misses)
739,742c739,742
< system.cpu.dcache.demand_accesses::cpu.data 167458892 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 167458892 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 167529405 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 167529405 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 167459031 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 167459031 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 167529543 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 167529543 # number of overall (read+write) accesses
753,758c753,758
< system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.404145 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.404145 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8066.754102 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 8066.754102 # average WriteReq miss latency
---
> system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.124897 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.124897 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8065.509164 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 8065.509164 # average WriteReq miss latency
761,764c761,764
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 8026.431178 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 8026.431178 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 8026.394214 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 8026.394214 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 8025.877098 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 8025.877098 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 8025.840136 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 8025.840136 # average overall miss latency
766c766
< system.cpu.dcache.blocked_cycles::no_targets 1059827 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 1060412 # number of cycles access was blocked
768c768
< system.cpu.dcache.blocked::no_targets 134751 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked
770c770
< system.cpu.dcache.avg_blocked_cycles::no_targets 7.865077 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 7.869477 # average number of cycles each access was blocked
775,778c775,778
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483173 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1483173 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891007 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 891007 # number of WriteReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483175 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1483175 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 890991 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 890991 # number of WriteReq MSHR hits
781,784c781,784
< system.cpu.dcache.demand_mshr_hits::cpu.data 2374180 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2374180 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2374180 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2374180 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 2374166 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2374166 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2374166 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2374166 # number of overall MSHR hits
795,798c795,798
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10622731000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10622731000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1827670779 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1827670779 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10623648000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10623648000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1826747781 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1826747781 # number of WriteReq MSHR miss cycles
801,804c801,804
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450401779 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12450401779 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451082779 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12451082779 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450395781 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12450395781 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451076781 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12451076781 # number of overall MSHR miss cycles
815,818c815,818
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.159399 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.159399 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8282.933897 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8282.933897 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.857432 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.857432 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8278.750905 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8278.750905 # average WriteReq mshr miss latency
821,824c821,824
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.457593 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.457593 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.843253 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.843253 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.453684 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.453684 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.839344 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.839344 # average overall mshr miss latency
826,834c826,834
< system.cpu.icache.tags.replacements 715634 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.830268 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 88370349 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 716146 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 123.397113 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 324802500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.830268 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999668 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 715635 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.829472 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 88370544 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 716147 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 123.397213 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 326419500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.829472 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy
842,867c842,867
< system.cpu.icache.tags.tag_accesses 178900425 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 178900425 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 88370349 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 88370349 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 88370349 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 88370349 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 88370349 # number of overall hits
< system.cpu.icache.overall_hits::total 88370349 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 721790 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 721790 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 721790 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 721790 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 721790 # number of overall misses
< system.cpu.icache.overall_misses::total 721790 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973224944 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 5973224944 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 5973224944 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 5973224944 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 5973224944 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 5973224944 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 89092139 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 89092139 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 89092139 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 89092139 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 89092139 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 89092139 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 178900820 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 178900820 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 88370544 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 88370544 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 88370544 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 88370544 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 88370544 # number of overall hits
> system.cpu.icache.overall_hits::total 88370544 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 721792 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 721792 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 721792 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 721792 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 721792 # number of overall misses
> system.cpu.icache.overall_misses::total 721792 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973239447 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 5973239447 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 5973239447 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 5973239447 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 5973239447 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 5973239447 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 89092336 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 89092336 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 89092336 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 89092336 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 89092336 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 89092336 # number of overall (read+write) accesses
874,880c874,880
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.571765 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 8275.571765 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 8275.571765 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 8275.571765 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 62134 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.568927 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8275.568927 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8275.568927 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8275.568927 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 62302 # number of cycles access was blocked
882c882
< system.cpu.icache.blocked::no_mshrs 2178 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 2158 # number of cycles access was blocked
884c884
< system.cpu.icache.avg_blocked_cycles::no_mshrs 28.528007 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.870250 # average number of cycles each access was blocked
888,905c888,905
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5643 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 5643 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 5643 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 5643 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 5643 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 5643 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716147 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 716147 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 716147 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 716147 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 716147 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 716147 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5549831453 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 5549831453 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5549831453 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 5549831453 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5549831453 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 5549831453 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5644 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 5644 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 5644 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 5644 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 5644 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 5644 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716148 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 716148 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 716148 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 716148 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 716148 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 716148 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5551358955 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 5551358955 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5551358955 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 5551358955 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5551358955 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 5551358955 # number of overall MSHR miss cycles
912,917c912,917
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7749.570204 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7749.570204 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7751.692325 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7751.692325 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency
919,921c919,921
< system.cpu.l2cache.prefetcher.num_hwpf_issued 404667 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 404963 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 238 # number of redundant prefetches already in prefetch queue
---
> system.cpu.l2cache.prefetcher.num_hwpf_issued 405270 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 405390 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 107 # number of redundant prefetches already in prefetch queue
924c924
< system.cpu.l2cache.prefetcher.pfSpanPage 28037 # number of prefetches not generated due to page crossing
---
> system.cpu.l2cache.prefetcher.pfSpanPage 28146 # number of prefetches not generated due to page crossing
926,929c926,929
< system.cpu.l2cache.tags.tagsinuse 5979.453401 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3840411 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 7285 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 527.166918 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 5987.985640 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3840429 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 7297 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 526.302453 # Average number of references to valid blocks.
931,940c931,940
< system.cpu.l2cache.tags.occ_blocks::writebacks 2575.206017 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.661219 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 617.502494 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 106.083671 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.157178 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163615 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.037689 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006475 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.364957 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 494 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2575.177185 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.633084 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 617.470420 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.704950 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.157176 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163613 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.037687 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007001 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.365478 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 506 # Occupied blocks per task id
945c945
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 112 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 124 # Occupied blocks per task id
948,949c948,949
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 772 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id
951c951
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030151 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030884 # Percentage of cache occupancy per task id
953,954c953,954
< system.cpu.l2cache.tags.tag_accesses 68225284 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 68225284 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 68225328 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 68225328 # Number of data accesses
959,970c959,970
< system.cpu.l2cache.ReadExReq_hits::cpu.data 219856 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 219856 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 712305 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 712305 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1312647 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1312647 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 712305 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2244808 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 712305 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2244808 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 219874 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 219874 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 712306 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 712306 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1312645 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1312645 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 712306 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1532519 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2244825 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 712306 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1532519 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2244825 # number of overall hits
973,974c973,974
< system.cpu.l2cache.ReadExReq_misses::cpu.data 797 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 797 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 779 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 779 # number of ReadExReq misses
977,978c977,978
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1057 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 1057 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1059 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 1059 # number of ReadSharedReq misses
980,981c980,981
< system.cpu.l2cache.demand_misses::cpu.data 1854 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 4790 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 1838 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 4774 # number of demand (read+write) misses
983,984c983,984
< system.cpu.l2cache.overall_misses::cpu.data 1854 # number of overall misses
< system.cpu.l2cache.overall_misses::total 4790 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.data 1838 # number of overall misses
> system.cpu.l2cache.overall_misses::total 4774 # number of overall misses
987,998c987,998
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57082000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 57082000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 199290000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 199290000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 76381000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 76381000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 199290000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 133463000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 332753000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 199290000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 133463000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 332753000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56035500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 56035500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 200811500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 200811500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 77311000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 77311000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 200811500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 133346500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 334158000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 200811500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 133346500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 334158000 # number of overall miss cycles
1005,1006c1005,1006
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715241 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 715241 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715242 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 715242 # number of ReadCleanReq accesses(hits+misses)
1009c1009
< system.cpu.l2cache.demand_accesses::cpu.inst 715241 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 715242 # number of demand (read+write) accesses
1011,1012c1011,1012
< system.cpu.l2cache.demand_accesses::total 2249598 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 715241 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 2249599 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 715242 # number of overall (read+write) accesses
1014c1014
< system.cpu.l2cache.overall_accesses::total 2249598 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 2249599 # number of overall (read+write) accesses
1017,1018c1017,1018
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003612 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.003612 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003530 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.003530 # miss rate for ReadExReq accesses
1021,1022c1021,1022
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000805 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000805 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000806 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000806 # miss rate for ReadSharedReq accesses
1024,1025c1024,1025
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.001208 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.002129 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.001198 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.002122 # miss rate for demand accesses
1027,1028c1027,1028
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.001208 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.002129 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.001198 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.002122 # miss rate for overall accesses
1031,1042c1031,1042
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71621.079046 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71621.079046 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67878.065395 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67878.065395 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72262.062441 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72262.062441 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67878.065395 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71986.515642 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69468.267223 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67878.065395 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71986.515642 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69468.267223 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71932.605905 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71932.605905 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68396.287466 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68396.287466 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73003.777148 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73003.777148 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68396.287466 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72549.782372 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69995.391705 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68396.287466 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72549.782372 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69995.391705 # average overall miss latency
1051,1052c1051,1052
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 57 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits
---
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 48 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 48 # number of ReadExReq MSHR hits
1058,1059c1058,1059
< system.cpu.l2cache.demand_mshr_hits::cpu.data 90 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
1061,1064c1061,1064
< system.cpu.l2cache.overall_mshr_hits::cpu.data 90 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 103 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30350 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 30350 # number of HardPFReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 94 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30427 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 30427 # number of HardPFReq MSHR misses
1067,1068c1067,1068
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 740 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 740 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 731 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 731 # number of ReadExReq MSHR misses
1071,1072c1071,1072
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1024 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1024 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1026 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1026 # number of ReadSharedReq MSHR misses
1074,1075c1074,1075
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1764 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 4687 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1757 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 4680 # number of demand (read+write) MSHR misses
1077,1081c1077,1081
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1764 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30350 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 35037 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 188993302 # number of HardPFReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1757 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30427 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 35107 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180653766 # number of HardPFReq MSHR miss cycles
1084,1096c1084,1096
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50613500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50613500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181139000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181139000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 68370000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 68370000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181139000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118983500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 300122500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181139000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118983500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 489115802 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49936000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49936000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182660500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182660500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69288000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69288000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182660500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119224000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 301884500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182660500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119224000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 482538266 # number of overall MSHR miss cycles
1101,1102c1101,1102
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003354 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003354 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003313 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003313 # mshr miss rate for ReadExReq accesses
1105,1106c1105,1106
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadSharedReq accesses
1108,1109c1108,1109
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.002083 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.002080 # mshr miss rate for demand accesses
1111c1111
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for overall accesses
1113,1115c1113,1115
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.015575 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6227.126919 # average HardPFReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.015606 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5937.284846 # average HardPFReq mshr miss latency
1118,1130c1118,1130
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820 # average overall mshr miss latency
1132c1132
< system.cpu.toL2Bus.trans_dist::ReadResp 2029851 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2029852 # Transaction distribution
1134,1135c1134,1135
< system.cpu.toL2Bus.trans_dist::CleanEvict 1033895 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 31761 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 1033896 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 31809 # Transaction distribution
1140c1140
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 716147 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 716148 # Transaction distribution
1142c1142
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122577 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122580 # Packet count per connected master and slave (bytes)
1144,1145c1144,1145
< system.cpu.toL2Bus.pkt_count::total 6500340 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775424 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 6500343 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775488 # Cumulative packet size per connected master and slave (bytes)
1147,1151c1147,1151
< system.cpu.toL2Bus.pkt_size::total 205819968 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 32667 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4531746 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.007009 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.083423 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size::total 205820032 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 32715 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4531796 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.007019 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.083485 # Request fanout histogram
1154,1155c1154,1155
< system.cpu.toL2Bus.snoop_fanout::1 4499985 99.30% 99.30% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 31761 0.70% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 4499987 99.30% 99.30% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 31809 0.70% 100.00% # Request fanout histogram
1159,1160c1159,1160
< system.cpu.toL2Bus.snoop_fanout::total 4531746 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3216331500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 4531796 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3216332500 # Layer occupancy (ticks)
1162c1162
< system.cpu.toL2Bus.respLayer0.occupancy 1074485469 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1074486969 # Layer occupancy (ticks)
1164c1164
< system.cpu.toL2Bus.respLayer1.occupancy 2301553965 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2301554963 # Layer occupancy (ticks)
1166c1166
< system.membus.trans_dist::ReadResp 6571 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 6592 # Transaction distribution
1169,1175c1169,1175
< system.membus.trans_dist::ReadExReq 740 # Transaction distribution
< system.membus.trans_dist::ReadExResp 740 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 6571 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14624 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 14624 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467904 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 467904 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 731 # Transaction distribution
> system.membus.trans_dist::ReadExResp 731 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14648 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 14648 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468672 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 468672 # Cumulative packet size per connected master and slave (bytes)
1177c1177
< system.membus.snoop_fanout::samples 7312 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 7324 # Request fanout histogram
1181c1181
< system.membus.snoop_fanout::0 7312 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 7324 100.00% 100.00% # Request fanout histogram
1186,1187c1186,1187
< system.membus.snoop_fanout::total 7312 # Request fanout histogram
< system.membus.reqLayer0.occupancy 9348857 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 7324 # Request fanout histogram
> system.membus.reqLayer0.occupancy 9437390 # Layer occupancy (ticks)
1189c1189
< system.membus.respLayer1.occupancy 38261400 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 38347412 # Layer occupancy (ticks)