3,5c3,5
< sim_seconds 0.112624 # Number of seconds simulated
< sim_ticks 112623767500 # Number of ticks simulated
< final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.112554 # Number of seconds simulated
> sim_ticks 112553814500 # Number of ticks simulated
> final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 123996 # Simulator instruction rate (inst/s)
< host_op_rate 148871 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 51146556 # Simulator tick rate (ticks/s)
< host_mem_usage 325020 # Number of bytes of host memory used
< host_seconds 2201.98 # Real time elapsed on the host
---
> host_inst_rate 125235 # Simulator instruction rate (inst/s)
> host_op_rate 150358 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 51625290 # Simulator tick rate (ticks/s)
> host_mem_usage 326264 # Number of bytes of host memory used
> host_seconds 2180.21 # Real time elapsed on the host
16,36c16,36
< system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory
< system.physmem.bytes_read::total 469120 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7330 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory
> system.physmem.bytes_read::total 468928 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 7327 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7327 # Number of read requests accepted
38c38
< system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue
40c40
< system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM
43c43
< system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 468928 # Total read bytes from the system interface side
51c51
< system.physmem.perBankRdBursts::3 519 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 520 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::7 257 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 255 # Per bank write bursts
57,58c57,58
< system.physmem.perBankRdBursts::9 291 # Per bank write bursts
< system.physmem.perBankRdBursts::10 316 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 290 # Per bank write bursts
> system.physmem.perBankRdBursts::10 315 # Per bank write bursts
82c82
< system.physmem.totGap 112623613500 # Total gap between requests
---
> system.physmem.totGap 112553656000 # Total gap between requests
89c89
< system.physmem.readPktSize::6 7330 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7327 # Read request sizes (log2)
97,109c97,109
< system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
193,210c193,210
< system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation
< system.physmem.totQLat 100359280 # Total ticks spent queuing
< system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation
> system.physmem.totQLat 96387273 # Total ticks spent queuing
> system.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 36635000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst
212c212
< system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst
221c221
< system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
223c223
< system.physmem.readRowHits 5950 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 5921 # Number of row buffer hits during reads
225c225
< system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads
227,230c227,230
< system.physmem.avgGap 15364749.45 # Average gap between requests
< system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ)
---
> system.physmem.avgGap 15361492.56 # Average gap between requests
> system.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ)
233,239c233,239
< system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.161673 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states
< system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states
---
> system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.186805 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states
> system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states
241c241
< system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states
243,245c243,245
< system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ)
247,253c247,253
< system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.228880 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states
< system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states
---
> system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.241613 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states
> system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states
255c255
< system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states
257,261c257,261
< system.cpu.branchPred.lookups 37762202 # Number of BP lookups
< system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits
---
> system.cpu.branchPred.lookups 37745757 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 17299874 # Number of BTB hits
263,265c263,265
< system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
384c384
< system.cpu.numCycles 225247536 # number of cpu cycles simulated
---
> system.cpu.numCycles 225107630 # number of cpu cycles simulated
387,399c387,399
< system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total)
401,404c401,404
< system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total)
408,436c408,436
< system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 108576617 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 113387886 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups
438,455c438,455
< system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 24831082 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle
457,463c457,463
< system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle
469c469
< system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle
471,501c471,501
< system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available
505,535c505,535
< system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued
538,550c538,550
< system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued
< system.cpu.iq.rate 1.537271 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 346404668 # Type of FU issued
> system.cpu.iq.rate 1.538840 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 251306416 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 126798006 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores
552,555c552,555
< system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed
558,559c558,559
< system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked
561,564c561,564
< system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ
566,577c566,577
< system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute
579,587c579,587
< system.cpu.iew.exec_nop 868 # number of nop insts executed
< system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed
< system.cpu.iew.exec_branches 31752029 # Number of branches executed
< system.cpu.iew.exec_stores 84582492 # Number of stores executed
< system.cpu.iew.exec_rate 1.519678 # Inst execution rate
< system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 153542130 # num instructions producing a value
< system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 867 # number of nop insts executed
> system.cpu.iew.exec_refs 175255989 # number of memory reference insts executed
> system.cpu.iew.exec_branches 31752931 # Number of branches executed
> system.cpu.iew.exec_stores 84589034 # Number of stores executed
> system.cpu.iew.exec_rate 1.521114 # Inst execution rate
> system.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 340687891 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 153731206 # num instructions producing a value
> system.cpu.iew.wb_consumers 266896125 # num instructions consuming a value
589,590c589,590
< system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.513444 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back
592c592
< system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit
594,597c594,597
< system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle
599,607c599,607
< system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle
611c611
< system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle
657c657
< system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached
659,662c659,662
< system.cpu.rob.rob_reads 561683936 # The number of ROB reads
< system.cpu.rob.rob_writes 705354391 # The number of ROB writes
< system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 561599370 # The number of ROB reads
> system.cpu.rob.rob_writes 705507733 # The number of ROB writes
> system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling
665,675c665,675
< system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 331186150 # number of integer regfile reads
< system.cpu.int_regfile_writes 136908474 # number of integer regfile writes
< system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads
< system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes
< system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads
< system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes
< system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads
---
> system.cpu.cpi 0.824458 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.212919 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 331300708 # number of integer regfile reads
> system.cpu.int_regfile_writes 136940215 # number of integer regfile writes
> system.cpu.fp_regfile_reads 187107289 # number of floating regfile reads
> system.cpu.fp_regfile_writes 132177847 # number of floating regfile writes
> system.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads
> system.cpu.cc_regfile_writes 80242169 # number of cc regfile writes
> system.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads
677,685c677,685
< system.cpu.dcache.tags.replacements 1533739 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.replacements 1533856 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy
687c687
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
689c689
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
692,701c692,701
< system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits
704,713c704,713
< system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits
< system.cpu.dcache.overall_hits::total 163782096 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits
> system.cpu.dcache.overall_hits::total 163667410 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses
716,731c716,731
< system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses
< system.cpu.dcache.overall_misses::total 3771380 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses
> system.cpu.dcache.overall_misses::total 3860348 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses)
734,737c734,737
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses)
740,749c740,749
< system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses
752,765c752,765
< system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency
767c767
< system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked
769c769
< system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked
771c771
< system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked
774,779c774,779
< system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks
< system.cpu.dcache.writebacks::total 966281 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks
> system.cpu.dcache.writebacks::total 966341 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits
782,789c782,789
< system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses
792,809c792,809
< system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses
812,825c812,825
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency
827,835c827,835
< system.cpu.icache.tags.replacements 715275 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 315060000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.840362 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999688 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999688 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 715719 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy
838,841c838,841
< system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 68 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id
843,883c843,883
< system.cpu.icache.tags.tag_accesses 178935006 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 178935006 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 88389408 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 88389408 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 88389408 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 88389408 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 88389408 # number of overall hits
< system.cpu.icache.overall_hits::total 88389408 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 720201 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 720201 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 720201 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 720201 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 720201 # number of overall misses
< system.cpu.icache.overall_misses::total 720201 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 5943843584 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 5943843584 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 5943843584 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 5943843584 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 5943843584 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 5943843584 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 89109609 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 89109609 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 89109609 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 89109609 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 89109609 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 89109609 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008082 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.008082 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.008082 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.008082 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.008082 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.008082 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8253.034339 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 8253.034339 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 8253.034339 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 8253.034339 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 51882 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 52 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 1935 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 178906226 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits
> system.cpu.icache.overall_hits::total 88373879 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses
> system.cpu.icache.overall_misses::total 721118 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked
885,886c885,886
< system.cpu.icache.avg_blocked_cycles::no_mshrs 26.812403 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 17.333333 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked
889,918c889,918
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4413 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 4413 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 4413 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 4413 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 4413 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 4413 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715788 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 715788 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 715788 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 715788 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 715788 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 715788 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4812391061 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 4812391061 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4812391061 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 4812391061 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4812391061 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 4812391061 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.008033 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.008033 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6723.207236 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6723.207236 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716232 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 716232 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 716232 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 716232 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 716232 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 716232 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5192936459 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 5192936459 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5192936459 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 5192936459 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5192936459 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 5192936459 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7250.355275 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7250.355275 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency
920,922c920,922
< system.cpu.l2cache.prefetcher.num_hwpf_issued 406270 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 406521 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 191 # number of redundant prefetches already in prefetch queue
---
> system.cpu.l2cache.prefetcher.num_hwpf_issued 404550 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 404804 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 188 # number of redundant prefetches already in prefetch queue
925c925
< system.cpu.l2cache.prefetcher.pfSpanPage 28111 # number of prefetches not generated due to page crossing
---
> system.cpu.l2cache.prefetcher.pfSpanPage 28140 # number of prefetches not generated due to page crossing
927,930c927,930
< system.cpu.l2cache.tags.tagsinuse 5993.755359 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2805980 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 7304 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 384.170318 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 5993.813794 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2806615 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 7301 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 384.415149 # Average number of references to valid blocks.
932,942c932,942
< system.cpu.l2cache.tags.occ_blocks::writebacks 2575.357550 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.182450 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 614.569855 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 123.645504 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.157187 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163585 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.037510 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007547 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.365830 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 515 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 6789 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2575.149913 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2681.614006 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 610.589138 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 126.460737 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.157175 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163673 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.037267 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007719 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.365833 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 517 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 6784 # Occupied blocks per task id
946,948c946,948
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 135 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
950,960c950,960
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5746 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031433 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414368 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 51674481 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 51674481 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 711950 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1312705 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2024655 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 966281 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 966281 # number of Writeback hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5743 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031555 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414062 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 51684538 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 51684538 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 712391 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1312672 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2025063 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits
963,973c963,973
< system.cpu.l2cache.ReadExReq_hits::cpu.data 219662 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 219662 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 711950 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1532367 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2244317 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 711950 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1532367 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2244317 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2934 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 1059 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 3993 # number of ReadReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 219831 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 219831 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 712391 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2244894 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 712391 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2244894 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2935 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 1053 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 3988 # number of ReadReq misses
976,1001c976,1001
< system.cpu.l2cache.ReadExReq_misses::cpu.data 825 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 825 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 2934 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1884 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 4818 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2934 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1884 # number of overall misses
< system.cpu.l2cache.overall_misses::total 4818 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 179619250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70145000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 249764250 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 50824468 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 50824468 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 179619250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 120969468 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 300588718 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 179619250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 120969468 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 300588718 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 714884 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1313764 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2028648 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 966281 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 966281 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 812 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 812 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 2935 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1865 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 4800 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2935 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1865 # number of overall misses
> system.cpu.l2cache.overall_misses::total 4800 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200800474 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76846248 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 277646722 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57691250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 57691250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 200800474 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 134537498 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 335337972 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 200800474 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 134537498 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 335337972 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 715326 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1313725 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2029051 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 966341 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 966341 # number of Writeback accesses(hits+misses)
1004,1014c1004,1014
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 220487 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 220487 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 714884 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1534251 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2249135 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 714884 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1534251 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2249135 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004104 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.001968 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 220643 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 220643 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 715326 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1534368 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2249694 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 715326 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2249694 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000802 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001965 # miss rate for ReadReq accesses
1017,1037c1017,1037
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003742 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.003742 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004104 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.001228 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.002142 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004104 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.001228 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.002142 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61219.921609 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66237.016053 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 62550.525920 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61605.415758 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61605.415758 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 62388.691988 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 62388.691988 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003680 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.003680 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004103 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.001215 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.002134 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004103 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.001215 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.002134 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68415.834412 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72978.393162 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69620.542126 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71048.337438 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71048.337438 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69862.077500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69862.077500 # average overall miss latency
1047,1050c1047,1050
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 98 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 98 # number of ReadExReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 47 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 47 # number of ReadExReq MSHR hits
1052,1053c1052,1053
< system.cpu.l2cache.demand_mshr_hits::cpu.data 131 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
1055,1061c1055,1061
< system.cpu.l2cache.overall_mshr_hits::cpu.data 131 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 142 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1026 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 3949 # number of ReadReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30530 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 30530 # number of HardPFReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 92 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2924 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1019 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30395 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 30395 # number of HardPFReq MSHR misses
1064,1091c1064,1091
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59960500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 213858750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 204942291 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41351500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41351500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 153898250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101312000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 765 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 765 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2924 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1784 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 4708 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2924 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1784 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30395 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 35103 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175338026 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 66096002 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241434028 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176500042 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49863251 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49863251 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175338026 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115959253 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 291297279 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175338026 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115959253 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 467797321 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000776 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001943 # mshr miss rate for ReadReq accesses
1096,1102c1096,1102
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses
1104,1120c1104,1120
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency
1122,1125c1122,1125
< system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution
1128,1139c1128,1139
< system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 33002 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 32706 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram
1144,1147c1144,1145
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram
1149,1152c1147,1150
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks)
1154c1152
< system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks)
1156c1154
< system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks)
1158,1159c1156,1157
< system.membus.trans_dist::ReadReq 6603 # Transaction distribution
< system.membus.trans_dist::ReadResp 6603 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 6562 # Transaction distribution
> system.membus.trans_dist::ReadResp 6562 # Transaction distribution
1162,1167c1160,1165
< system.membus.trans_dist::ReadExReq 727 # Transaction distribution
< system.membus.trans_dist::ReadExResp 727 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 765 # Transaction distribution
> system.membus.trans_dist::ReadExResp 765 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes)
1169c1167
< system.membus.snoop_fanout::samples 7331 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 7328 # Request fanout histogram
1173c1171
< system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram
1178,1179c1176,1177
< system.membus.snoop_fanout::total 7331 # Request fanout histogram
< system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 7328 # Request fanout histogram
> system.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks)
1181,1182c1179,1180
< system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.0 # Layer utilization (%)