3,5c3,5
< sim_seconds 0.058843 # Number of seconds simulated
< sim_ticks 58842982000 # Number of ticks simulated
< final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.112541 # Number of seconds simulated
> sim_ticks 112540655000 # Number of ticks simulated
> final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 157851 # Simulator instruction rate (inst/s)
< host_op_rate 189517 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34018873 # Simulator tick rate (ticks/s)
< host_mem_usage 327492 # Number of bytes of host memory used
< host_seconds 1729.72 # Real time elapsed on the host
< sim_insts 273036656 # Number of instructions simulated
< sim_ops 327810999 # Number of ops (including micro ops) simulated
---
> host_inst_rate 123771 # Simulator instruction rate (inst/s)
> host_op_rate 148600 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 51015836 # Simulator tick rate (ticks/s)
> host_mem_usage 322668 # Number of bytes of host memory used
> host_seconds 2205.99 # Real time elapsed on the host
> sim_insts 273037219 # Number of instructions simulated
> sim_ops 327811601 # Number of ops (including micro ops) simulated
16,32c16,36
< system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory
< system.physmem.bytes_read::total 461504 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7211 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory
> system.physmem.bytes_read::total 623680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 9745 # Number of read requests accepted
34c38
< system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue
36c40
< system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM
39c43
< system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side
43,59c47,63
< system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 592 # Per bank write bursts
< system.physmem.perBankRdBursts::1 792 # Per bank write bursts
< system.physmem.perBankRdBursts::2 603 # Per bank write bursts
< system.physmem.perBankRdBursts::3 519 # Per bank write bursts
< system.physmem.perBankRdBursts::4 437 # Per bank write bursts
< system.physmem.perBankRdBursts::5 342 # Per bank write bursts
< system.physmem.perBankRdBursts::6 159 # Per bank write bursts
< system.physmem.perBankRdBursts::7 228 # Per bank write bursts
< system.physmem.perBankRdBursts::8 208 # Per bank write bursts
< system.physmem.perBankRdBursts::9 292 # Per bank write bursts
< system.physmem.perBankRdBursts::10 317 # Per bank write bursts
< system.physmem.perBankRdBursts::11 409 # Per bank write bursts
< system.physmem.perBankRdBursts::12 526 # Per bank write bursts
< system.physmem.perBankRdBursts::13 671 # Per bank write bursts
< system.physmem.perBankRdBursts::14 612 # Per bank write bursts
< system.physmem.perBankRdBursts::15 504 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 803 # Per bank write bursts
> system.physmem.perBankRdBursts::1 999 # Per bank write bursts
> system.physmem.perBankRdBursts::2 769 # Per bank write bursts
> system.physmem.perBankRdBursts::3 645 # Per bank write bursts
> system.physmem.perBankRdBursts::4 618 # Per bank write bursts
> system.physmem.perBankRdBursts::5 484 # Per bank write bursts
> system.physmem.perBankRdBursts::6 251 # Per bank write bursts
> system.physmem.perBankRdBursts::7 363 # Per bank write bursts
> system.physmem.perBankRdBursts::8 300 # Per bank write bursts
> system.physmem.perBankRdBursts::9 432 # Per bank write bursts
> system.physmem.perBankRdBursts::10 486 # Per bank write bursts
> system.physmem.perBankRdBursts::11 534 # Per bank write bursts
> system.physmem.perBankRdBursts::12 696 # Per bank write bursts
> system.physmem.perBankRdBursts::13 850 # Per bank write bursts
> system.physmem.perBankRdBursts::14 782 # Per bank write bursts
> system.physmem.perBankRdBursts::15 733 # Per bank write bursts
78c82
< system.physmem.totGap 58842848000 # Total gap between requests
---
> system.physmem.totGap 112540488500 # Total gap between requests
85c89
< system.physmem.readPktSize::6 7211 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 9745 # Read request sizes (log2)
93,108c97,112
< system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see
189,206c193,210
< system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation
< system.physmem.totQLat 59614750 # Total ticks spent queuing
< system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation
> system.physmem.totQLat 248191131 # Total ticks spent queuing
> system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst
208,209c212,213
< system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s
211c215
< system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s
214,215c218,219
< system.physmem.busUtil 0.06 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 0.04 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
217c221
< system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
219c223
< system.physmem.readRowHits 5798 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 8500 # Number of row buffer hits during reads
221c225
< system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads
223,226c227,230
< system.physmem.avgGap 8160150.88 # Average gap between requests
< system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states
< system.physmem.memoryStateTime::REF 1964820000 # Time in different power states
---
> system.physmem.avgGap 11548536.53 # Average gap between requests
> system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states
> system.physmem.memoryStateTime::REF 3757780000 # Time in different power states
228c232
< system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states
230,243c234,255
< system.membus.throughput 7842974 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 4381 # Transaction distribution
< system.membus.trans_dist::ReadResp 4381 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 11 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 11 # Transaction distribution
< system.membus.trans_dist::ReadExReq 2830 # Transaction distribution
< system.membus.trans_dist::ReadExResp 2830 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 461504 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks)
---
> system.membus.trans_dist::ReadReq 9170 # Transaction distribution
> system.membus.trans_dist::ReadResp 9170 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
> system.membus.trans_dist::ReadExReq 575 # Transaction distribution
> system.membus.trans_dist::ReadExResp 575 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 9746 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 9746 # Request fanout histogram
> system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks)
245c257
< system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks)
248,252c260,264
< system.cpu.branchPred.lookups 36678579 # Number of BP lookups
< system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits
---
> system.cpu.branchPred.lookups 37763717 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits
254,256c266,268
< system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
342c354
< system.cpu.numCycles 117685965 # number of cpu cycles simulated
---
> system.cpu.numCycles 225081311 # number of cpu cycles simulated
345,358c357,370
< system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 3511516 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total)
360,368c372,375
< system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total)
371,418c378,426
< system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle
< system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle
420,428c428,436
< system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
431,432c439,440
< system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle
434,464c442,472
< system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available
468,498c476,506
< system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued
501,513c509,521
< system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued
< system.cpu.iq.rate 3.048316 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued
> system.cpu.iq.rate 1.538412 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores
515,518c523,526
< system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed
521,522c529,530
< system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked
524,540c532,548
< system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute
542,550c550,558
< system.cpu.iew.exec_nop 1106 # number of nop insts executed
< system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed
< system.cpu.iew.exec_branches 32405794 # Number of branches executed
< system.cpu.iew.exec_stores 88579829 # Number of stores executed
< system.cpu.iew.exec_rate 3.014336 # Inst execution rate
< system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 175212964 # num instructions producing a value
< system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 864 # number of nop insts executed
> system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed
> system.cpu.iew.exec_branches 31752179 # Number of branches executed
> system.cpu.iew.exec_stores 84582729 # Number of stores executed
> system.cpu.iew.exec_rate 1.520806 # Inst execution rate
> system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 153543382 # num instructions producing a value
> system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value
552,553c560,561
< system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back
555c563
< system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit
557,560c565,568
< system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle
562,570c570,578
< system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle
574,576c582,584
< system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 273037268 # Number of instructions committed
< system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 273037831 # Number of instructions committed
> system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed
578,579c586,587
< system.cpu.commit.refs 168107803 # Number of memory references committed
< system.cpu.commit.loads 85732225 # Number of loads committed
---
> system.cpu.commit.refs 168107892 # Number of memory references committed
> system.cpu.commit.loads 85732275 # Number of loads committed
581c589
< system.cpu.commit.branches 30563485 # Number of branches committed
---
> system.cpu.commit.branches 30563525 # Number of branches committed
583,584c591,592
< system.cpu.commit.int_insts 258331174 # Number of committed integer instructions.
< system.cpu.commit.function_calls 6225112 # Number of function calls committed.
---
> system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
> system.cpu.commit.function_calls 6225114 # Number of function calls committed.
586,587c594,595
< system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
615,616c623,624
< system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
619,620c627,628
< system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction
< system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction
> system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached
622,638c630,646
< system.cpu.rob.rob_reads 463276381 # The number of ROB reads
< system.cpu.rob.rob_writes 746948197 # The number of ROB writes
< system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.committedInsts 273036656 # Number of Instructions Simulated
< system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads
< system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 344698387 # number of integer regfile reads
< system.cpu.int_regfile_writes 141985623 # number of integer regfile writes
< system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads
< system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes
< system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads
< system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes
< system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads
---
> system.cpu.rob.rob_reads 561656707 # The number of ROB reads
> system.cpu.rob.rob_writes 705358338 # The number of ROB writes
> system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.committedInsts 273037219 # Number of Instructions Simulated
> system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 331187238 # number of integer regfile reads
> system.cpu.int_regfile_writes 136909181 # number of integer regfile writes
> system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads
> system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes
> system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads
> system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes
> system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads
640,721c648,743
< system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.cpu.icache.tags.replacements 13841 # number of replacements
< system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits
< system.cpu.icache.overall_hits::total 38751328 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses
< system.cpu.icache.overall_misses::total 17524 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 50213 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
> system.cpu.icache.tags.replacements 715368 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits
> system.cpu.icache.overall_hits::total 88391816 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses
> system.cpu.icache.overall_misses::total 719790 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked
724,753c746,775
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 1801 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 1801 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 1801 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 1801 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 1801 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15723 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 15723 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 15723 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 15723 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 15723 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350218008 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 350218008 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350218008 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 350218008 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350218008 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency
754a777,785
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
756,759c787,790
< system.cpu.l2cache.tags.tagsinuse 3837.051468 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 13121 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5294 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 2.478466 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 8320.579960 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2794148 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 9718 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 287.522947 # Average number of references to valid blocks.
761,781c792,820
< system.cpu.l2cache.tags.occ_blocks::writebacks 357.151307 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2707.112582 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 772.787579 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010899 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.082615 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.023584 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.117098 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5294 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3911 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.161560 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 178837 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 178837 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 12742 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 286 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 13028 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1022 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1022 # number of Writeback hits
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 2574.248018 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 441.129211 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 367.415546 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4937.787185 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2027473 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 966282 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 966282 # number of Writeback hits
784,855c823,898
< system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 12742 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 302 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 13044 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 12742 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 302 # number of overall hits
< system.cpu.l2cache.overall_hits::total 13044 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2967 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 1462 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 4429 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 2830 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 2830 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 2967 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 4292 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 7259 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2967 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses
< system.cpu.l2cache.overall_misses::total 7259 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207032250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 106837750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 313870000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 202417250 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 202417250 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 207032250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 309255000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 516287250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 207032250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 309255000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 516287250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 15709 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1748 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 17457 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1022 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1022 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 12 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 12 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2846 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2846 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 15709 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 4594 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 20303 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 15709 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 4594 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 20303 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.188873 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836384 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.253709 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916667 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916667 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994378 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.994378 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188873 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.934262 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.357533 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188873 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.934262 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.357533 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69778.311426 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73076.436389 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 70867.012870 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71525.530035 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71525.530035 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69778.311426 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72053.821062 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71123.742940 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69778.311426 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72053.821062 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71123.742940 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 219797 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 219797 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 714431 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1532839 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2247270 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 714431 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1532839 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2247270 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 546 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 730 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1276 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 689 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 689 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 546 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1419 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1965 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 546 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1419 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1965 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38998499 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50021748 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 89020247 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41954499 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 41954499 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 38998499 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 91976247 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 130974746 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 38998499 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 91976247 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 130974746 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 714977 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1313772 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2028749 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 966282 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 966282 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 220486 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 220486 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 714977 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1534258 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2249235 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 714977 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1534258 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2249235 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000764 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000556 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.000629 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003125 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.003125 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000764 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.000925 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.000874 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000764 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.000925 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.000874 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71425.822344 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68522.942466 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69765.083856 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60891.870827 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60891.870827 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66653.814758 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66653.814758 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 6173 # number of cycles access was blocked
857c900
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.l2cache.blocked::no_mshrs 209 # number of cycles access was blocked
859c902
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.535885 # average number of cycles each access was blocked
863,923c906,980
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 48 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2959 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1422 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2830 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 2830 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2959 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 4252 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 7211 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2959 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 4252 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 7211 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169394250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86707000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 256101250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 112009 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 112009 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 167488250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 167488250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169394250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254195250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 423589500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169394250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254195250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 423589500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813501 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250960 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916667 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916667 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994378 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994378 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.355169 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.355169 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57247.127408 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60975.386779 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58457.258617 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10182.636364 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10182.636364 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59183.127208 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59183.127208 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 114 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 114 # number of ReadExReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 157 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 157 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 225 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 478 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 687 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1165 # number of ReadReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 44298 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 44298 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 575 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 575 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 478 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1262 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1740 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 478 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1262 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 44298 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 46038 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32592250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42691498 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75283748 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 669707182 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34465750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34465750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32592250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77157248 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 109749498 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32592250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77157248 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 779456680 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000523 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
> system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency
925,950c982,1006
< system.cpu.dcache.tags.replacements 1384 # number of replacements
< system.cpu.dcache.tags.tagsinuse 3114.575432 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 161730326 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 4594 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 35204.685677 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3114.575432 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.760394 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.760394 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 3210 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82030417 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 87045 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 87045 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 11127 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 11127 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.replacements 1533746 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits
953,986c1009,1042
< system.cpu.dcache.demand_hits::cpu.data 161621188 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 161621188 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 161708233 # number of overall hits
< system.cpu.dcache.overall_hits::total 161708233 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 4059 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 4059 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 22243 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 22243 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 40 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 40 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses
< system.cpu.dcache.overall_misses::total 26342 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits
> system.cpu.dcache.overall_hits::total 163781573 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses
> system.cpu.dcache.overall_misses::total 3771680 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses)
989,1020c1045,1076
< system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked
1023,1074c1079,1130
< system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks
< system.cpu.dcache.writebacks::total 1022 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks
> system.cpu.dcache.writebacks::total 966282 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency