Cross Reference: /gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.068267 # Number of seconds simulated
4sim_ticks 68267465500 # Number of ticks simulated
5final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 160764 # Simulator instruction rate (inst/s)
8host_op_rate 205527 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 40194170 # Simulator tick rate (ticks/s)
10host_mem_usage 285344 # Number of bytes of host memory used
11host_seconds 1698.44 # Real time elapsed on the host

7host_inst_rate 47859 # Simulator instruction rate (inst/s)
8host_op_rate 61184 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 11965597 # Simulator tick rate (ticks/s)
10host_mem_usage 240720 # Number of bytes of host memory used
11host_seconds 5705.31 # Real time elapsed on the host

12sim_insts 273048375 # Number of instructions simulated
13sim_ops 349076099 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 273088 # Number of bytes read from this memory
16system.physmem.bytes_read::total 467008 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 4267 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 7297 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 2840592 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 4000266 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 6840857 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 2840592 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 2840592 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 2840592 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 4000266 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 6840857 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 7297 # Total number of read requests seen
31system.physmem.writeReqs 0 # Total number of write requests seen
32system.physmem.cpureqs 7297 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 467008 # Total number of bytes read from memory
34system.physmem.bytesWritten 0 # Total number of bytes written to memory
35system.physmem.bytesConsumedRd 467008 # bytesRead derated as per pkt->getSize()
36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 581 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::5 457 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 505 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 483 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 495 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 558 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 359 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis
55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

73system.physmem.totGap 68267282000 # Total gap between requests

73system.physmem.totGap 68267283000 # Total gap between requests

74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 7297 # Categorize read packet sizes
81system.physmem.readPktSize::7 0 # Categorize read packet sizes
82system.physmem.readPktSize::8 0 # Categorize read packet sizes
83system.physmem.writePktSize::0 0 # categorize write packet sizes
84system.physmem.writePktSize::1 0 # categorize write packet sizes
85system.physmem.writePktSize::2 0 # categorize write packet sizes
86system.physmem.writePktSize::3 0 # categorize write packet sizes
87system.physmem.writePktSize::4 0 # categorize write packet sizes
88system.physmem.writePktSize::5 0 # categorize write packet sizes
89system.physmem.writePktSize::6 0 # categorize write packet sizes
90system.physmem.writePktSize::7 0 # categorize write packet sizes
91system.physmem.writePktSize::8 0 # categorize write packet sizes
92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101system.physmem.rdQLenPdf::0 4347 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 2135 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 568 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 183 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167system.physmem.totQLat 36802775 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 167840775 # Sum of mem lat for all requests
169system.physmem.totBusLat 29188000 # Total cycles spent in databus access
170system.physmem.totBankLat 101850000 # Total cycles spent in bank access
171system.physmem.avgQLat 5043.55 # Average queueing delay per request
172system.physmem.avgBankLat 13957.79 # Average bank access latency per request
173system.physmem.avgBusLat 4000.00 # Average bus latency per request
174system.physmem.avgMemAccLat 23001.34 # Average memory access latency
175system.physmem.avgRdBW 6.84 # Average achieved read bandwidth in MB/s
176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177system.physmem.avgConsumedRdBW 6.84 # Average consumed read bandwidth in MB/s
178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 0.04 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.00 # Average read queue length over time
182system.physmem.avgWrQLen 0.00 # Average write queue length over time
183system.physmem.readRowHits 6392 # Number of row buffer hits during reads
184system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads
186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

187system.physmem.avgGap 9355527.20 # Average gap between requests

187system.physmem.avgGap 9355527.34 # Average gap between requests

188system.cpu.dtb.inst_hits 0 # ITB inst hits
189system.cpu.dtb.inst_misses 0 # ITB inst misses
190system.cpu.dtb.read_hits 0 # DTB read hits
191system.cpu.dtb.read_misses 0 # DTB read misses
192system.cpu.dtb.write_hits 0 # DTB write hits
193system.cpu.dtb.write_misses 0 # DTB write misses
194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
196system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
197system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
198system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
199system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
200system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
201system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
202system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
203system.cpu.dtb.read_accesses 0 # DTB read accesses
204system.cpu.dtb.write_accesses 0 # DTB write accesses
205system.cpu.dtb.inst_accesses 0 # ITB inst accesses
206system.cpu.dtb.hits 0 # DTB hits
207system.cpu.dtb.misses 0 # DTB misses
208system.cpu.dtb.accesses 0 # DTB accesses
209system.cpu.itb.inst_hits 0 # ITB inst hits
210system.cpu.itb.inst_misses 0 # ITB inst misses
211system.cpu.itb.read_hits 0 # DTB read hits
212system.cpu.itb.read_misses 0 # DTB read misses
213system.cpu.itb.write_hits 0 # DTB write hits
214system.cpu.itb.write_misses 0 # DTB write misses
215system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
216system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
217system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
218system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
219system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
220system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
221system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
222system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
224system.cpu.itb.read_accesses 0 # DTB read accesses
225system.cpu.itb.write_accesses 0 # DTB write accesses
226system.cpu.itb.inst_accesses 0 # ITB inst accesses
227system.cpu.itb.hits 0 # DTB hits
228system.cpu.itb.misses 0 # DTB misses
229system.cpu.itb.accesses 0 # DTB accesses
230system.cpu.workload.num_syscalls 191 # Number of system calls
231system.cpu.numCycles 136534932 # number of cpu cycles simulated
232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
234system.cpu.BPredUnit.lookups 41739250 # Number of BP lookups
235system.cpu.BPredUnit.condPredicted 21065104 # Number of conditional branches predicted
236system.cpu.BPredUnit.condIncorrect 1640413 # Number of conditional branches incorrect
237system.cpu.BPredUnit.BTBLookups 26027262 # Number of BTB lookups
238system.cpu.BPredUnit.BTBHits 16735646 # Number of BTB hits
239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
240system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target.
241system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions.

242system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss

242system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss

243system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed
244system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered
245system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken
246system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked
247system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing

248system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked
249system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

248system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked
249system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

250system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps
251system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR

252system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched
253system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed
254system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total)

252system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched
253system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed
254system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total)

255system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total)
256system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total)
257system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

258system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total)

258system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total)

259system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total)
260system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total)
261system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::4 4881557 3.58% 65.63% # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::5 4156543 3.05% 68.67% # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.rateDist::6 3204825 2.35% 71.03% # Number of instructions fetched each cycle (Total)
265system.cpu.fetch.rateDist::7 4146681 3.04% 74.07% # Number of instructions fetched each cycle (Total)
266system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Number of instructions fetched each cycle (Total)
267system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
268system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
269system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

270system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total)

270system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total)

271system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle
272system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle
273system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle

274system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked

274system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked

275system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running
276system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking
277system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing
278system.cpu.decode.BranchResolved 7269016 # Number of times decode resolved a branch
279system.cpu.decode.BranchMispred 69099 # Number of times decode detected a branch misprediction
280system.cpu.decode.DecodedInsts 401164000 # Number of instructions handled by decode
281system.cpu.decode.SquashedInsts 213330 # Number of squashed instructions handled by decode
282system.cpu.rename.SquashCycles 5039795 # Number of cycles rename is squashing
283system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle
284system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking
285system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst

286system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running

286system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running

287system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking

288system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename

288system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename

289system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full
290system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full
291system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full
292system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers

293system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed
294system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made
295system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups

293system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed
294system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made
295system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups

296system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups
297system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed

298system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing

298system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing

299system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed
300system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed
301system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer
302system.cpu.memDep0.insertedLoads 103432229 # Number of loads inserted to the mem dependence unit.
303system.cpu.memDep0.insertedStores 91356063 # Number of stores inserted to the mem dependence unit.
304system.cpu.memDep0.conflictingLoads 4280154 # Number of conflicting loads.
305system.cpu.memDep0.conflictingStores 5359345 # Number of conflicting stores.
306system.cpu.iq.iqInstsAdded 383896453 # Number of instructions added to the IQ (excludes non-spec)
307system.cpu.iq.iqNonSpecInstsAdded 25411 # Number of non-speculative instructions added to the IQ
308system.cpu.iq.iqInstsIssued 373948163 # Number of instructions issued
309system.cpu.iq.iqSquashedInstsIssued 1224653 # Number of squashed instructions issued
310system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling
311system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph
312system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed

313system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle

313system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle

314system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle
316system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

317system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle

317system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle

318system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle
319system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::4 23977307 17.59% 78.82% # Number of insts issued each cycle
322system.cpu.iq.issued_per_cycle::5 15767707 11.57% 90.39% # Number of insts issued each cycle
323system.cpu.iq.issued_per_cycle::6 8831817 6.48% 96.87% # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::7 3361471 2.47% 99.33% # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Number of insts issued each cycle
326system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

329system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle

329system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle

330system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
331system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available
332system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available
333system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
334system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
335system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
336system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
337system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
338system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
339system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
340system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
341system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
342system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
343system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
344system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
345system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
346system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
347system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
348system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
349system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
350system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
351system.cpu.iq.fu_full::SimdFloatAdd 46185 0.26% 0.34% # attempts to use FU when none available
352system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
353system.cpu.iq.fu_full::SimdFloatCmp 7671 0.04% 0.38% # attempts to use FU when none available
354system.cpu.iq.fu_full::SimdFloatCvt 470 0.00% 0.38% # attempts to use FU when none available
355system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available
356system.cpu.iq.fu_full::SimdFloatMisc 190051 1.07% 1.45% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdFloatMult 6041 0.03% 1.48% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdFloatMultAcc 241741 1.36% 2.84% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
360system.cpu.iq.fu_full::MemRead 9330966 52.43% 55.27% # attempts to use FU when none available
361system.cpu.iq.fu_full::MemWrite 7960919 44.73% 100.00% # attempts to use FU when none available
362system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
363system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
364system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
365system.cpu.iq.FU_type_0::IntAlu 126153074 33.74% 33.74% # Type of FU issued
366system.cpu.iq.FU_type_0::IntMult 2174128 0.58% 34.32% # Type of FU issued
367system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued
368system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued
369system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued
370system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued
371system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued
372system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued
373system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued
374system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued
375system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued
376system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued
377system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued
378system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued
379system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdFloatAdd 6786226 1.81% 36.13% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.13% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdFloatCmp 8470375 2.27% 38.40% # Type of FU issued
388system.cpu.iq.FU_type_0::SimdFloatCvt 3426412 0.92% 39.31% # Type of FU issued
389system.cpu.iq.FU_type_0::SimdFloatDiv 1600673 0.43% 39.74% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdFloatMisc 20911148 5.59% 45.33% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdFloatMult 7171927 1.92% 47.25% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134560 1.91% 49.16% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.21% # Type of FU issued
394system.cpu.iq.FU_type_0::MemRead 101505429 27.14% 76.35% # Type of FU issued
395system.cpu.iq.FU_type_0::MemWrite 88438925 23.65% 100.00% # Type of FU issued
396system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
397system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
398system.cpu.iq.FU_type_0::total 373948163 # Type of FU issued
399system.cpu.iq.rate 2.738846 # Inst issue rate
400system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested
401system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst)

402system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads

402system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads

403system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes
404system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses
405system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads
406system.cpu.iq.fp_inst_queue_writes 130436942 # Number of floating instruction queue writes
407system.cpu.iq.fp_inst_queue_wakeup_accesses 118161488 # Number of floating instruction queue wakeup accesses
408system.cpu.iq.int_alu_accesses 262975786 # Number of integer alu accesses
409system.cpu.iq.fp_alu_accesses 128770067 # Number of floating point alu accesses
410system.cpu.iew.lsq.thread0.forwLoads 11107823 # Number of loads that had data forwarded from stores
411system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
412system.cpu.iew.lsq.thread0.squashedLoads 8781151 # Number of loads squashed
413system.cpu.iew.lsq.thread0.ignoredResponses 113920 # Number of memory responses ignored because the instruction is squashed
414system.cpu.iew.lsq.thread0.memOrderViolation 14326 # Number of memory ordering violations
415system.cpu.iew.lsq.thread0.squashedStores 8978150 # Number of stores squashed
416system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
417system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
418system.cpu.iew.lsq.thread0.rescheduledLoads 176383 # Number of loads that were rescheduled
419system.cpu.iew.lsq.thread0.cacheBlocked 1158 # Number of times an access to memory failed due to the cache being blocked
420system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
421system.cpu.iew.iewSquashCycles 5039795 # Number of cycles IEW is squashing
422system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking
423system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking
424system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ

425system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch

425system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch

426system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions
427system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions
428system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions
429system.cpu.iew.iewIQFullEvents 345 # Number of times the IQ has become full, causing a stall
430system.cpu.iew.iewLSQFullEvents 384 # Number of times the LSQ has become full, causing a stall
431system.cpu.iew.memOrderViolationEvents 14326 # Number of memory order violations
432system.cpu.iew.predictedTakenIncorrect 1283309 # Number of branches that were predicted taken incorrectly
433system.cpu.iew.predictedNotTakenIncorrect 356464 # Number of branches that were predicted not taken incorrectly
434system.cpu.iew.branchMispredicts 1639773 # Number of branch mispredicts detected at execute
435system.cpu.iew.iewExecutedInsts 370071311 # Number of executed instructions
436system.cpu.iew.iewExecLoadInsts 100289689 # Number of load instructions executed
437system.cpu.iew.iewExecSquashedInsts 3876852 # Number of squashed instructions skipped in execute
438system.cpu.iew.exec_swp 0 # number of swp insts executed
439system.cpu.iew.exec_nop 1594 # number of nop insts executed
440system.cpu.iew.exec_refs 187642898 # number of memory reference insts executed
441system.cpu.iew.exec_branches 38279004 # Number of branches executed
442system.cpu.iew.exec_stores 87353209 # Number of stores executed
443system.cpu.iew.exec_rate 2.710451 # Inst execution rate
444system.cpu.iew.wb_sent 368702519 # cumulative count of insts sent to commit
445system.cpu.iew.wb_count 368038571 # cumulative count of insts written-back
446system.cpu.iew.wb_producers 182991065 # num instructions producing a value
447system.cpu.iew.wb_consumers 363891400 # num instructions consuming a value
448system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
449system.cpu.iew.wb_rate 2.695563 # insts written-back per cycle
450system.cpu.iew.wb_fanout 0.502873 # average fanout of values written-back
451system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
452system.cpu.commit.commitSquashedInsts 34846819 # The number of squashed insts skipped by commit
453system.cpu.commit.commitNonSpecStalls 24450 # The number of times commit has been forced to stall to communicate backwards
454system.cpu.commit.branchMispredicts 1571698 # The number of times a branch was mispredicted
455system.cpu.commit.committed_per_cycle::samples 131284486 # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::mean 2.658933 # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::stdev 2.660928 # Number of insts commited each cycle
458system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
459system.cpu.commit.committed_per_cycle::0 34526115 26.30% 26.30% # Number of insts commited each cycle
460system.cpu.commit.committed_per_cycle::1 28464962 21.68% 47.98% # Number of insts commited each cycle
461system.cpu.commit.committed_per_cycle::2 13313072 10.14% 58.12% # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::3 11375196 8.66% 66.79% # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::4 13798040 10.51% 77.30% # Number of insts commited each cycle
464system.cpu.commit.committed_per_cycle::5 7398451 5.64% 82.93% # Number of insts commited each cycle
465system.cpu.commit.committed_per_cycle::6 3831320 2.92% 85.85% # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::7 3930958 2.99% 88.84% # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::8 14646372 11.16% 100.00% # Number of insts commited each cycle
468system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
471system.cpu.commit.committed_per_cycle::total 131284486 # Number of insts commited each cycle
472system.cpu.commit.committedInsts 273048987 # Number of instructions committed
473system.cpu.commit.committedOps 349076711 # Number of ops (including micro ops) committed
474system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
475system.cpu.commit.refs 177028991 # Number of memory references committed
476system.cpu.commit.loads 94651078 # Number of loads committed
477system.cpu.commit.membars 11033 # Number of memory barriers committed
478system.cpu.commit.branches 36549040 # Number of branches committed
479system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
480system.cpu.commit.int_insts 279593931 # Number of committed integer instructions.
481system.cpu.commit.function_calls 6225112 # Number of function calls committed.
482system.cpu.commit.bw_lim_events 14646372 # number cycles where commit BW limit reached
483system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
484system.cpu.rob.rob_reads 500559121 # The number of ROB reads
485system.cpu.rob.rob_writes 772890927 # The number of ROB writes
486system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself

487system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling

487system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling

488system.cpu.committedInsts 273048375 # Number of Instructions Simulated
489system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated
490system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated
491system.cpu.cpi 0.500039 # CPI: Cycles Per Instruction
492system.cpu.cpi_total 0.500039 # CPI: Total CPI of All Threads
493system.cpu.ipc 1.999843 # IPC: Instructions Per Cycle
494system.cpu.ipc_total 1.999843 # IPC: Total IPC of All Threads
495system.cpu.int_regfile_reads 1769305779 # number of integer regfile reads
496system.cpu.int_regfile_writes 232713829 # number of integer regfile writes
497system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads
498system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes
499system.cpu.misc_regfile_reads 567370356 # number of misc regfile reads
500system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes
501system.cpu.icache.replacements 13908 # number of replacements
502system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use
503system.cpu.icache.total_refs 37470862 # Total number of references to valid blocks.
504system.cpu.icache.sampled_refs 15795 # Sample count of references to valid blocks.
505system.cpu.icache.avg_refs 2372.324280 # Average number of references to valid blocks.
506system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
507system.cpu.icache.occ_blocks::cpu.inst 1849.811927 # Average occupied blocks per requestor
508system.cpu.icache.occ_percent::cpu.inst 0.903228 # Average percentage of cache occupancy
509system.cpu.icache.occ_percent::total 0.903228 # Average percentage of cache occupancy
510system.cpu.icache.ReadReq_hits::cpu.inst 37470862 # number of ReadReq hits
511system.cpu.icache.ReadReq_hits::total 37470862 # number of ReadReq hits
512system.cpu.icache.demand_hits::cpu.inst 37470862 # number of demand (read+write) hits
513system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits
514system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits
515system.cpu.icache.overall_hits::total 37470862 # number of overall hits

516system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses
517system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses
518system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses
519system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses
520system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses
521system.cpu.icache.overall_misses::total 17049 # number of overall misses
522system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles
523system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles
524system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles
525system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles
526system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles
527system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles
528system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses)
529system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses)
530system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses
531system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses
532system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses
533system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses

516system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses
517system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses
518system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses
519system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses
520system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses
521system.cpu.icache.overall_misses::total 17050 # number of overall misses
522system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles
523system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles
524system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles
525system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles
526system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles
527system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles
528system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses)
529system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses)
530system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses
531system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses
532system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses
533system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses

534system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses
535system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses
536system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses
537system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses
538system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses
539system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses

540system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency
541system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency
542system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
543system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency
544system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
545system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency

540system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency
541system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency
542system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
543system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency
544system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
545system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency

546system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked
547system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
548system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
549system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
550system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 # average number of cycles each access was blocked
551system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
552system.cpu.icache.fast_writes 0 # number of fast writes performed
553system.cpu.icache.cache_copies 0 # number of cache copies performed

554system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits
555system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits
556system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits
557system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits
558system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits
559system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits

554system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits
555system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits
556system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits
557system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits
558system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits
559system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits

560system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses
561system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses
562system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses
563system.cpu.icache.demand_mshr_misses::total 15795 # number of demand (read+write) MSHR misses
564system.cpu.icache.overall_mshr_misses::cpu.inst 15795 # number of overall MSHR misses
565system.cpu.icache.overall_mshr_misses::total 15795 # number of overall MSHR misses
566system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291702997 # number of ReadReq MSHR miss cycles
567system.cpu.icache.ReadReq_mshr_miss_latency::total 291702997 # number of ReadReq MSHR miss cycles
568system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291702997 # number of demand (read+write) MSHR miss cycles
569system.cpu.icache.demand_mshr_miss_latency::total 291702997 # number of demand (read+write) MSHR miss cycles
570system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291702997 # number of overall MSHR miss cycles
571system.cpu.icache.overall_mshr_miss_latency::total 291702997 # number of overall MSHR miss cycles
572system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses
573system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses
574system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses
575system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses
576system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses
577system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses
578system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18468.059323 # average ReadReq mshr miss latency
579system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18468.059323 # average ReadReq mshr miss latency
580system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
581system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
582system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
583system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
584system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

585system.cpu.dcache.replacements 1414 # number of replacements
586system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
587system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
588system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
589system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
590system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
591system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
592system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
593system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
594system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
595system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
596system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
597system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
598system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
599system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
600system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
601system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
602system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
603system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
604system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
605system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
606system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
607system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
608system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
609system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
610system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
611system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
612system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
613system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
614system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
615system.cpu.dcache.overall_misses::total 25149 # number of overall misses
616system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
617system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
618system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
619system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
620system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
621system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
622system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
623system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
624system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
625system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
626system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
627system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
628system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
629system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
630system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
631system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
632system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
633system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
634system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
635system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
636system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
637system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
638system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
639system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
640system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
641system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
642system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
643system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
644system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
645system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
646system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
647system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
648system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
649system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
650system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
651system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
652system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
653system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
654system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
655system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
656system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
657system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
658system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
659system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
660system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
661system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
662system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
663system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
664system.cpu.dcache.fast_writes 0 # number of fast writes performed
665system.cpu.dcache.cache_copies 0 # number of cache copies performed
666system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
667system.cpu.dcache.writebacks::total 1040 # number of writebacks
668system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
669system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
670system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
671system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
672system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
673system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
674system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
675system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
676system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
677system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
678system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
679system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
680system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
681system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
682system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
683system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
684system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
685system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
686system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
687system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
688system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
689system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
690system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
691system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
692system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
693system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
694system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
695system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
696system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
697system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
698system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
699system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
700system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
701system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
702system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
704system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
706system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
707system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
708system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
709system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
710system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

711system.cpu.l2cache.replacements 0 # number of replacements

585system.cpu.l2cache.replacements 0 # number of replacements

712system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use

586system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use

713system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks.
714system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks.
715system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks.
716system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
717system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor

587system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks.
588system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks.
589system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks.
590system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
591system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor

718system.cpu.l2cache.occ_blocks::cpu.inst 2774.541574 # Average occupied blocks per requestor

592system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor

719system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor
720system.cpu.l2cache.occ_percent::writebacks 0.011220 # Average percentage of cache occupancy
721system.cpu.l2cache.occ_percent::cpu.inst 0.084672 # Average percentage of cache occupancy
722system.cpu.l2cache.occ_percent::cpu.data 0.024945 # Average percentage of cache occupancy
723system.cpu.l2cache.occ_percent::total 0.120837 # Average percentage of cache occupancy
724system.cpu.l2cache.ReadReq_hits::cpu.inst 12753 # number of ReadReq hits
725system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits
726system.cpu.l2cache.ReadReq_hits::total 13052 # number of ReadReq hits
727system.cpu.l2cache.Writeback_hits::writebacks 1040 # number of Writeback hits
728system.cpu.l2cache.Writeback_hits::total 1040 # number of Writeback hits
729system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits
730system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits
731system.cpu.l2cache.demand_hits::cpu.inst 12753 # number of demand (read+write) hits
732system.cpu.l2cache.demand_hits::cpu.data 317 # number of demand (read+write) hits
733system.cpu.l2cache.demand_hits::total 13070 # number of demand (read+write) hits
734system.cpu.l2cache.overall_hits::cpu.inst 12753 # number of overall hits
735system.cpu.l2cache.overall_hits::cpu.data 317 # number of overall hits
736system.cpu.l2cache.overall_hits::total 13070 # number of overall hits
737system.cpu.l2cache.ReadReq_misses::cpu.inst 3042 # number of ReadReq misses
738system.cpu.l2cache.ReadReq_misses::cpu.data 1512 # number of ReadReq misses
739system.cpu.l2cache.ReadReq_misses::total 4554 # number of ReadReq misses
740system.cpu.l2cache.ReadExReq_misses::cpu.data 2795 # number of ReadExReq misses
741system.cpu.l2cache.ReadExReq_misses::total 2795 # number of ReadExReq misses
742system.cpu.l2cache.demand_misses::cpu.inst 3042 # number of demand (read+write) misses
743system.cpu.l2cache.demand_misses::cpu.data 4307 # number of demand (read+write) misses
744system.cpu.l2cache.demand_misses::total 7349 # number of demand (read+write) misses
745system.cpu.l2cache.overall_misses::cpu.inst 3042 # number of overall misses
746system.cpu.l2cache.overall_misses::cpu.data 4307 # number of overall misses
747system.cpu.l2cache.overall_misses::total 7349 # number of overall misses
748system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 148332000 # number of ReadReq miss cycles

593system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor
594system.cpu.l2cache.occ_percent::writebacks 0.011220 # Average percentage of cache occupancy
595system.cpu.l2cache.occ_percent::cpu.inst 0.084672 # Average percentage of cache occupancy
596system.cpu.l2cache.occ_percent::cpu.data 0.024945 # Average percentage of cache occupancy
597system.cpu.l2cache.occ_percent::total 0.120837 # Average percentage of cache occupancy
598system.cpu.l2cache.ReadReq_hits::cpu.inst 12753 # number of ReadReq hits
599system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits
600system.cpu.l2cache.ReadReq_hits::total 13052 # number of ReadReq hits
601system.cpu.l2cache.Writeback_hits::writebacks 1040 # number of Writeback hits
602system.cpu.l2cache.Writeback_hits::total 1040 # number of Writeback hits
603system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits
604system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits
605system.cpu.l2cache.demand_hits::cpu.inst 12753 # number of demand (read+write) hits
606system.cpu.l2cache.demand_hits::cpu.data 317 # number of demand (read+write) hits
607system.cpu.l2cache.demand_hits::total 13070 # number of demand (read+write) hits
608system.cpu.l2cache.overall_hits::cpu.inst 12753 # number of overall hits
609system.cpu.l2cache.overall_hits::cpu.data 317 # number of overall hits
610system.cpu.l2cache.overall_hits::total 13070 # number of overall hits
611system.cpu.l2cache.ReadReq_misses::cpu.inst 3042 # number of ReadReq misses
612system.cpu.l2cache.ReadReq_misses::cpu.data 1512 # number of ReadReq misses
613system.cpu.l2cache.ReadReq_misses::total 4554 # number of ReadReq misses
614system.cpu.l2cache.ReadExReq_misses::cpu.data 2795 # number of ReadExReq misses
615system.cpu.l2cache.ReadExReq_misses::total 2795 # number of ReadExReq misses
616system.cpu.l2cache.demand_misses::cpu.inst 3042 # number of demand (read+write) misses
617system.cpu.l2cache.demand_misses::cpu.data 4307 # number of demand (read+write) misses
618system.cpu.l2cache.demand_misses::total 7349 # number of demand (read+write) misses
619system.cpu.l2cache.overall_misses::cpu.inst 3042 # number of overall misses
620system.cpu.l2cache.overall_misses::cpu.data 4307 # number of overall misses
621system.cpu.l2cache.overall_misses::total 7349 # number of overall misses
622system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 148332000 # number of ReadReq miss cycles

749system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74801500 # number of ReadReq miss cycles
750system.cpu.l2cache.ReadReq_miss_latency::total 223133500 # number of ReadReq miss cycles

623system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74802000 # number of ReadReq miss cycles
624system.cpu.l2cache.ReadReq_miss_latency::total 223134000 # number of ReadReq miss cycles

751system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128955500 # number of ReadExReq miss cycles
752system.cpu.l2cache.ReadExReq_miss_latency::total 128955500 # number of ReadExReq miss cycles
753system.cpu.l2cache.demand_miss_latency::cpu.inst 148332000 # number of demand (read+write) miss cycles

625system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128955500 # number of ReadExReq miss cycles
626system.cpu.l2cache.ReadExReq_miss_latency::total 128955500 # number of ReadExReq miss cycles
627system.cpu.l2cache.demand_miss_latency::cpu.inst 148332000 # number of demand (read+write) miss cycles

754system.cpu.l2cache.demand_miss_latency::cpu.data 203757000 # number of demand (read+write) miss cycles
755system.cpu.l2cache.demand_miss_latency::total 352089000 # number of demand (read+write) miss cycles

628system.cpu.l2cache.demand_miss_latency::cpu.data 203757500 # number of demand (read+write) miss cycles
629system.cpu.l2cache.demand_miss_latency::total 352089500 # number of demand (read+write) miss cycles

756system.cpu.l2cache.overall_miss_latency::cpu.inst 148332000 # number of overall miss cycles

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631system.cpu.l2cache.overall_miss_latency::cpu.data 203757500 # number of overall miss cycles
632system.cpu.l2cache.overall_miss_latency::total 352089500 # number of overall miss cycles

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760system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses)
761system.cpu.l2cache.ReadReq_accesses::total 17606 # number of ReadReq accesses(hits+misses)
762system.cpu.l2cache.Writeback_accesses::writebacks 1040 # number of Writeback accesses(hits+misses)
763system.cpu.l2cache.Writeback_accesses::total 1040 # number of Writeback accesses(hits+misses)
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765system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses)
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771system.cpu.l2cache.overall_accesses::total 20419 # number of overall (read+write) accesses
772system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192593 # miss rate for ReadReq accesses
773system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834898 # miss rate for ReadReq accesses
774system.cpu.l2cache.ReadReq_miss_rate::total 0.258662 # miss rate for ReadReq accesses
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776system.cpu.l2cache.ReadExReq_miss_rate::total 0.993601 # miss rate for ReadExReq accesses
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778system.cpu.l2cache.demand_miss_rate::cpu.data 0.931445 # miss rate for demand accesses
779system.cpu.l2cache.demand_miss_rate::total 0.359910 # miss rate for demand accesses
780system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192593 # miss rate for overall accesses
781system.cpu.l2cache.overall_miss_rate::cpu.data 0.931445 # miss rate for overall accesses
782system.cpu.l2cache.overall_miss_rate::total 0.359910 # miss rate for overall accesses
783system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223 # average ReadReq miss latency

633system.cpu.l2cache.ReadReq_accesses::cpu.inst 15795 # number of ReadReq accesses(hits+misses)
634system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses)
635system.cpu.l2cache.ReadReq_accesses::total 17606 # number of ReadReq accesses(hits+misses)
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637system.cpu.l2cache.Writeback_accesses::total 1040 # number of Writeback accesses(hits+misses)
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639system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses)
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643system.cpu.l2cache.overall_accesses::cpu.inst 15795 # number of overall (read+write) accesses
644system.cpu.l2cache.overall_accesses::cpu.data 4624 # number of overall (read+write) accesses
645system.cpu.l2cache.overall_accesses::total 20419 # number of overall (read+write) accesses
646system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192593 # miss rate for ReadReq accesses
647system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834898 # miss rate for ReadReq accesses
648system.cpu.l2cache.ReadReq_miss_rate::total 0.258662 # miss rate for ReadReq accesses
649system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993601 # miss rate for ReadExReq accesses
650system.cpu.l2cache.ReadExReq_miss_rate::total 0.993601 # miss rate for ReadExReq accesses
651system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192593 # miss rate for demand accesses
652system.cpu.l2cache.demand_miss_rate::cpu.data 0.931445 # miss rate for demand accesses
653system.cpu.l2cache.demand_miss_rate::total 0.359910 # miss rate for demand accesses
654system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192593 # miss rate for overall accesses
655system.cpu.l2cache.overall_miss_rate::cpu.data 0.931445 # miss rate for overall accesses
656system.cpu.l2cache.overall_miss_rate::total 0.359910 # miss rate for overall accesses
657system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223 # average ReadReq miss latency

784system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534 # average ReadReq miss latency
785system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160 # average ReadReq miss latency

658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222 # average ReadReq miss latency
659system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954 # average ReadReq miss latency

786system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866 # average ReadExReq miss latency
787system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866 # average ReadExReq miss latency
788system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency

660system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866 # average ReadExReq miss latency
661system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866 # average ReadExReq miss latency
662system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency

789system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
790system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644 # average overall miss latency

663system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
664system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681 # average overall miss latency

791system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency

665system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency

792system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
793system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644 # average overall miss latency

666system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
667system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681 # average overall miss latency

794system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
795system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
796system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
797system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
798system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
799system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
800system.cpu.l2cache.fast_writes 0 # number of fast writes performed
801system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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803system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
804system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
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806system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits
807system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
808system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
809system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
810system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits
811system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3030 # number of ReadReq MSHR misses
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815system.cpu.l2cache.ReadExReq_mshr_misses::total 2795 # number of ReadExReq MSHR misses
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818system.cpu.l2cache.demand_mshr_misses::total 7297 # number of demand (read+write) MSHR misses
819system.cpu.l2cache.overall_mshr_misses::cpu.inst 3030 # number of overall MSHR misses
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821system.cpu.l2cache.overall_mshr_misses::total 7297 # number of overall MSHR misses
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823system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54676221 # number of ReadReq MSHR miss cycles
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826system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94308882 # number of ReadExReq MSHR miss cycles
827system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109506099 # number of demand (read+write) MSHR miss cycles
828system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148985103 # number of demand (read+write) MSHR miss cycles
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830system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109506099 # number of overall MSHR miss cycles
831system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148985103 # number of overall MSHR miss cycles
832system.cpu.l2cache.overall_mshr_miss_latency::total 258491202 # number of overall MSHR miss cycles
833system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for ReadReq accesses
834system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812811 # mshr miss rate for ReadReq accesses
835system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255708 # mshr miss rate for ReadReq accesses
836system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993601 # mshr miss rate for ReadExReq accesses
837system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993601 # mshr miss rate for ReadExReq accesses
838system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for demand accesses
839system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for demand accesses
840system.cpu.l2cache.demand_mshr_miss_rate::total 0.357363 # mshr miss rate for demand accesses
841system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for overall accesses
842system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for overall accesses
843system.cpu.l2cache.overall_mshr_miss_rate::total 0.357363 # mshr miss rate for overall accesses
844system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36140.626733 # average ReadReq mshr miss latency
845system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37144.171875 # average ReadReq mshr miss latency
846system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36468.751666 # average ReadReq mshr miss latency
847system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33741.997138 # average ReadExReq mshr miss latency
848system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33741.997138 # average ReadExReq mshr miss latency
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850system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
851system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
852system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733 # average overall mshr miss latency
853system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
854system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
855system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

668system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
669system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
670system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
671system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
672system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
673system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
674system.cpu.l2cache.fast_writes 0 # number of fast writes performed
675system.cpu.l2cache.cache_copies 0 # number of cache copies performed
676system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
677system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
678system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
679system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
680system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits
681system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
682system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
683system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
684system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits
685system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3030 # number of ReadReq MSHR misses
686system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1472 # number of ReadReq MSHR misses
687system.cpu.l2cache.ReadReq_mshr_misses::total 4502 # number of ReadReq MSHR misses
688system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2795 # number of ReadExReq MSHR misses
689system.cpu.l2cache.ReadExReq_mshr_misses::total 2795 # number of ReadExReq MSHR misses
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692system.cpu.l2cache.demand_mshr_misses::total 7297 # number of demand (read+write) MSHR misses
693system.cpu.l2cache.overall_mshr_misses::cpu.inst 3030 # number of overall MSHR misses
694system.cpu.l2cache.overall_mshr_misses::cpu.data 4267 # number of overall MSHR misses
695system.cpu.l2cache.overall_mshr_misses::total 7297 # number of overall MSHR misses
696system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109506099 # number of ReadReq MSHR miss cycles
697system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54676221 # number of ReadReq MSHR miss cycles
698system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164182320 # number of ReadReq MSHR miss cycles
699system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94308882 # number of ReadExReq MSHR miss cycles
700system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94308882 # number of ReadExReq MSHR miss cycles
701system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109506099 # number of demand (read+write) MSHR miss cycles
702system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148985103 # number of demand (read+write) MSHR miss cycles
703system.cpu.l2cache.demand_mshr_miss_latency::total 258491202 # number of demand (read+write) MSHR miss cycles
704system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109506099 # number of overall MSHR miss cycles
705system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148985103 # number of overall MSHR miss cycles
706system.cpu.l2cache.overall_mshr_miss_latency::total 258491202 # number of overall MSHR miss cycles
707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for ReadReq accesses
708system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812811 # mshr miss rate for ReadReq accesses
709system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255708 # mshr miss rate for ReadReq accesses
710system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993601 # mshr miss rate for ReadExReq accesses
711system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993601 # mshr miss rate for ReadExReq accesses
712system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for demand accesses
713system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for demand accesses
714system.cpu.l2cache.demand_mshr_miss_rate::total 0.357363 # mshr miss rate for demand accesses
715system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for overall accesses
716system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for overall accesses
717system.cpu.l2cache.overall_mshr_miss_rate::total 0.357363 # mshr miss rate for overall accesses
718system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36140.626733 # average ReadReq mshr miss latency
719system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37144.171875 # average ReadReq mshr miss latency
720system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36468.751666 # average ReadReq mshr miss latency
721system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33741.997138 # average ReadExReq mshr miss latency
722system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33741.997138 # average ReadExReq mshr miss latency
723system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36140.626733 # average overall mshr miss latency
724system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
725system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733 # average overall mshr miss latency
727system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
728system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
729system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

730system.cpu.dcache.replacements 1414 # number of replacements
731system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use
732system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
733system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
734system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
735system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
736system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor
737system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
738system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
739system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
740system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
741system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
742system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
743system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
744system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
745system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
746system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
747system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
748system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
749system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
750system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
751system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
752system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
753system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
754system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
755system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
756system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
757system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
758system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
759system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
760system.cpu.dcache.overall_misses::total 25149 # number of overall misses
761system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles
762system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles
763system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
764system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
765system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
766system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
767system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles
768system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles
769system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles
770system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles
771system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
772system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
773system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
774system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
775system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
776system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
777system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
778system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
779system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
780system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
781system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
782system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
783system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
784system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
785system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
786system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
787system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
788system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
789system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
790system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
791system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
792system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
793system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency
794system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency
795system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
796system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
797system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
798system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
799system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
800system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency
801system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
802system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency
803system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
804system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
805system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
806system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
807system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
808system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
809system.cpu.dcache.fast_writes 0 # number of fast writes performed
810system.cpu.dcache.cache_copies 0 # number of cache copies performed
811system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
812system.cpu.dcache.writebacks::total 1040 # number of writebacks
813system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
814system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
815system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
816system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
817system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
818system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
819system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
820system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
821system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
822system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
823system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
824system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
825system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
826system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
827system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
828system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
829system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
830system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
831system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles
832system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles
833system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
834system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
835system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles
836system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles
837system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles
838system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles
839system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
840system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
841system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
842system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
843system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
844system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
845system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
846system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
847system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency
848system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency
849system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
850system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
851system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
852system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
853system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
854system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
855system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate