1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.071775 # Number of seconds simulated
4sim_ticks 71774859500 # Number of ticks simulated
5final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 69606 # Simulator instruction rate (inst/s)
8host_op_rate 88987 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 18296996 # Simulator tick rate (ticks/s)
10host_mem_usage 240272 # Number of bytes of host memory used
11host_seconds 3922.77 # Real time elapsed on the host
12sim_insts 273048474 # Number of instructions simulated
13sim_ops 349076199 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 472896 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 7389 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.inst_hits 0 # ITB inst hits
24system.cpu.dtb.inst_misses 0 # ITB inst misses
25system.cpu.dtb.read_hits 0 # DTB read hits
26system.cpu.dtb.read_misses 0 # DTB read misses
27system.cpu.dtb.write_hits 0 # DTB write hits
28system.cpu.dtb.write_misses 0 # DTB write misses
29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 332 unchanged lines hidden (view full) ---
363system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles
364system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses
367system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses
368system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses
369system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses
370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses
372system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses
373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency
374system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
382system.cpu.icache.fast_writes 0 # number of fast writes performed
383system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
395system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses
396system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles
397system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles
402system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses
403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses
404system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses
405system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency
406system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
407system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
408system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu.dcache.replacements 1427 # number of replacements
410system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use
411system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks.
412system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks.
413system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks.
414system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
455system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses)
456system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses)
457system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses)
458system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses
459system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses
460system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses
461system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses
462system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses
463system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses
464system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses
465system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses
466system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses
467system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency
468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency
469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency
470system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
473system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked
478system.cpu.dcache.fast_writes 0 # number of fast writes performed
479system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
501system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles
502system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles
503system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles
504system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles
508system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
509system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
510system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
511system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency
513system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency
514system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
515system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
516system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
517system.cpu.l2cache.replacements 69 # number of replacements
518system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use
519system.cpu.l2cache.total_refs 13357 # Total number of references to valid blocks.
520system.cpu.l2cache.sampled_refs 5499 # Sample count of references to valid blocks.
521system.cpu.l2cache.avg_refs 2.428987 # Average number of references to valid blocks.
522system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
523system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor
--- 52 unchanged lines hidden (view full) ---
576system.cpu.l2cache.demand_accesses::cpu.inst 16092 # number of demand (read+write) accesses
577system.cpu.l2cache.demand_accesses::cpu.data 4641 # number of demand (read+write) accesses
578system.cpu.l2cache.demand_accesses::total 20733 # number of demand (read+write) accesses
579system.cpu.l2cache.overall_accesses::cpu.inst 16092 # number of overall (read+write) accesses
580system.cpu.l2cache.overall_accesses::cpu.data 4641 # number of overall (read+write) accesses
581system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses
582system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses
583system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses
584system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
585system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses
586system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses
587system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses
588system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses
589system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses
590system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency
591system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency
592system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency
593system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
594system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
595system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
596system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
597system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
598system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
599system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
600system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
601system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
602system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
603system.cpu.l2cache.fast_writes 0 # number of fast writes performed
604system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 29 unchanged lines hidden (view full) ---
634system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles
635system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles
636system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles
637system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles
638system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles
639system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles
640system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses
641system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses
642system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
643system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses
644system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses
645system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses
646system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses
647system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses
648system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency
649system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency
650system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
651system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency
652system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
653system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
655system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
656system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
657
658---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.071775 # Number of seconds simulated
4sim_ticks 71774859500 # Number of ticks simulated
5final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 69606 # Simulator instruction rate (inst/s)
8host_op_rate 88987 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 18296996 # Simulator tick rate (ticks/s)
10host_mem_usage 240272 # Number of bytes of host memory used
11host_seconds 3922.77 # Real time elapsed on the host
12sim_insts 273048474 # Number of instructions simulated
13sim_ops 349076199 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 472896 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 7389 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.inst_hits 0 # ITB inst hits
24system.cpu.dtb.inst_misses 0 # ITB inst misses
25system.cpu.dtb.read_hits 0 # DTB read hits
26system.cpu.dtb.read_misses 0 # DTB read misses
27system.cpu.dtb.write_hits 0 # DTB write hits
28system.cpu.dtb.write_misses 0 # DTB write misses
29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 332 unchanged lines hidden (view full) ---
363system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles
364system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses
367system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses
368system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses
369system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses
370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses
372system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses
373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency
374system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
382system.cpu.icache.fast_writes 0 # number of fast writes performed
383system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
395system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses
396system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles
397system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles
402system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses
403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses
404system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses
405system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency
406system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
407system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
408system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu.dcache.replacements 1427 # number of replacements
410system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use
411system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks.
412system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks.
413system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks.
414system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
455system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses)
456system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses)
457system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses)
458system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses
459system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses
460system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses
461system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses
462system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses
463system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses
464system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses
465system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses
466system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses
467system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency
468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency
469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency
470system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
473system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked
478system.cpu.dcache.fast_writes 0 # number of fast writes performed
479system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
501system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles
502system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles
503system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles
504system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles
508system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
509system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
510system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
511system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency
513system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency
514system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
515system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
516system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
517system.cpu.l2cache.replacements 69 # number of replacements
518system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use
519system.cpu.l2cache.total_refs 13357 # Total number of references to valid blocks.
520system.cpu.l2cache.sampled_refs 5499 # Sample count of references to valid blocks.
521system.cpu.l2cache.avg_refs 2.428987 # Average number of references to valid blocks.
522system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
523system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor
--- 52 unchanged lines hidden (view full) ---
576system.cpu.l2cache.demand_accesses::cpu.inst 16092 # number of demand (read+write) accesses
577system.cpu.l2cache.demand_accesses::cpu.data 4641 # number of demand (read+write) accesses
578system.cpu.l2cache.demand_accesses::total 20733 # number of demand (read+write) accesses
579system.cpu.l2cache.overall_accesses::cpu.inst 16092 # number of overall (read+write) accesses
580system.cpu.l2cache.overall_accesses::cpu.data 4641 # number of overall (read+write) accesses
581system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses
582system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses
583system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses
584system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
585system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses
586system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses
587system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses
588system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses
589system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses
590system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency
591system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency
592system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency
593system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
594system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
595system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
596system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
597system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
598system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
599system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
600system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
601system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
602system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
603system.cpu.l2cache.fast_writes 0 # number of fast writes performed
604system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 29 unchanged lines hidden (view full) ---
634system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles
635system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles
636system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles
637system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles
638system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles
639system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles
640system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses
641system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses
642system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
643system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses
644system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses
645system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses
646system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses
647system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses
648system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency
649system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency
650system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
651system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency
652system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
653system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
655system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
656system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
657
658---------- End Simulation Statistics ----------