1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.104493 # Number of seconds simulated
4sim_ticks 104492506500 # Number of ticks simulated
5final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 158423 # Simulator instruction rate (inst/s)
8host_op_rate 202536 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 60628822 # Simulator tick rate (ticks/s)
10host_mem_usage 231676 # Number of bytes of host memory used
11host_seconds 1723.48 # Real time elapsed on the host
12sim_insts 273038258 # Number of instructions simulated
13sim_ops 349066034 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 464000 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 7250 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 4440510 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1842352 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 4440510 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.inst_hits 0 # ITB inst hits
24system.cpu.dtb.inst_misses 0 # ITB inst misses
25system.cpu.dtb.read_hits 0 # DTB read hits
26system.cpu.dtb.read_misses 0 # DTB read misses
27system.cpu.dtb.write_hits 0 # DTB write hits
28system.cpu.dtb.write_misses 0 # DTB write misses
29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 27 unchanged lines hidden (view full) ---

58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.itb.read_accesses 0 # DTB read accesses
60system.cpu.itb.write_accesses 0 # DTB write accesses
61system.cpu.itb.inst_accesses 0 # ITB inst accesses
62system.cpu.itb.hits 0 # DTB hits
63system.cpu.itb.misses 0 # DTB misses
64system.cpu.itb.accesses 0 # DTB accesses
65system.cpu.workload.num_syscalls 191 # Number of system calls
66system.cpu.numCycles 208985014 # number of cpu cycles simulated
67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69system.cpu.BPredUnit.lookups 38314474 # Number of BP lookups
70system.cpu.BPredUnit.condPredicted 21092938 # Number of conditional branches predicted
71system.cpu.BPredUnit.condIncorrect 3256966 # Number of conditional branches incorrect
72system.cpu.BPredUnit.BTBLookups 27298627 # Number of BTB lookups
73system.cpu.BPredUnit.BTBHits 21213565 # Number of BTB hits
74system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
75system.cpu.BPredUnit.usedRAS 7683795 # Number of times the RAS was used to get a target.
76system.cpu.BPredUnit.RASInCorrect 61136 # Number of incorrect RAS predictions.
77system.cpu.fetch.icacheStallCycles 43642080 # Number of cycles fetch is stalled on an Icache miss
78system.cpu.fetch.Insts 338343690 # Number of instructions fetch has processed
79system.cpu.fetch.Branches 38314474 # Number of branches that fetch encountered
80system.cpu.fetch.predictedBranches 28897360 # Number of branches that fetch has predicted taken
81system.cpu.fetch.Cycles 78995706 # Number of cycles fetch has run and was not squashing or blocked
82system.cpu.fetch.SquashCycles 10989579 # Number of cycles fetch has spent squashing
83system.cpu.fetch.BlockedCycles 78549841 # Number of cycles fetch has spent blocked
84system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
85system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
86system.cpu.fetch.CacheLines 41237520 # Number of cache lines fetched
87system.cpu.fetch.IcacheSquashes 904571 # Number of outstanding Icache misses that were squashed
88system.cpu.fetch.rateDist::samples 208872334 # Number of instructions fetched each cycle (Total)
89system.cpu.fetch.rateDist::mean 2.119807 # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::stdev 3.192773 # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::0 130527843 62.49% 62.49% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::1 9429667 4.51% 67.01% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::2 6020154 2.88% 69.89% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::3 6750748 3.23% 73.12% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::4 5430125 2.60% 75.72% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::5 4858478 2.33% 78.05% # Number of instructions fetched each cycle (Total)
98system.cpu.fetch.rateDist::6 3783272 1.81% 79.86% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::7 4242115 2.03% 81.89% # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::8 37829932 18.11% 100.00% # Number of instructions fetched each cycle (Total)
101system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
103system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
104system.cpu.fetch.rateDist::total 208872334 # Number of instructions fetched each cycle (Total)
105system.cpu.fetch.branchRate 0.183336 # Number of branch fetches per cycle
106system.cpu.fetch.rate 1.618985 # Number of inst fetches per cycle
107system.cpu.decode.IdleCycles 51215510 # Number of cycles decode is idle
108system.cpu.decode.BlockedCycles 73658589 # Number of cycles decode is blocked
109system.cpu.decode.RunCycles 72565491 # Number of cycles decode is running
110system.cpu.decode.UnblockCycles 3819053 # Number of cycles decode is unblocking
111system.cpu.decode.SquashCycles 7613691 # Number of cycles decode is squashing
112system.cpu.decode.BranchResolved 7463255 # Number of times decode resolved a branch
113system.cpu.decode.BranchMispred 71181 # Number of times decode detected a branch misprediction
114system.cpu.decode.DecodedInsts 431647720 # Number of instructions handled by decode
115system.cpu.decode.SquashedInsts 198442 # Number of squashed instructions handled by decode
116system.cpu.rename.SquashCycles 7613691 # Number of cycles rename is squashing
117system.cpu.rename.IdleCycles 58863443 # Number of cycles rename is idle
118system.cpu.rename.BlockCycles 1188654 # Number of cycles rename is blocking
119system.cpu.rename.serializeStallCycles 57607169 # count of cycles rename stalled for serializing inst
120system.cpu.rename.RunCycles 68932187 # Number of cycles rename is running
121system.cpu.rename.UnblockCycles 14667190 # Number of cycles rename is unblocking
122system.cpu.rename.RenamedInsts 416637973 # Number of instructions processed by rename
123system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
124system.cpu.rename.LSQFullEvents 8032684 # Number of times rename has blocked due to LSQ full
125system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
126system.cpu.rename.RenamedOperands 455385433 # Number of destination operands rename has renamed
127system.cpu.rename.RenameLookups 2446563589 # Number of register rename lookups that rename has made
128system.cpu.rename.int_rename_lookups 1351891912 # Number of integer rename lookups
129system.cpu.rename.fp_rename_lookups 1094671677 # Number of floating rename lookups
130system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
131system.cpu.rename.UndoneMaps 70816834 # Number of HB maps that are undone due to squashing
132system.cpu.rename.serializingInsts 3986585 # count of serializing insts renamed
133system.cpu.rename.tempSerializingInsts 4043449 # count of temporary serializing insts renamed
134system.cpu.rename.skidInsts 48232782 # count of insts added to the skid buffer
135system.cpu.memDep0.insertedLoads 108804127 # Number of loads inserted to the mem dependence unit.
136system.cpu.memDep0.insertedStores 93109820 # Number of stores inserted to the mem dependence unit.
137system.cpu.memDep0.conflictingLoads 3374999 # Number of conflicting loads.
138system.cpu.memDep0.conflictingStores 2307513 # Number of conflicting stores.
139system.cpu.iq.iqInstsAdded 394258042 # Number of instructions added to the IQ (excludes non-spec)
140system.cpu.iq.iqNonSpecInstsAdded 3864226 # Number of non-speculative instructions added to the IQ
141system.cpu.iq.iqInstsIssued 379117437 # Number of instructions issued
142system.cpu.iq.iqSquashedInstsIssued 1806866 # Number of squashed instructions issued
143system.cpu.iq.iqSquashedInstsExamined 46393196 # Number of squashed instructions iterated over during squash; mainly for profiling
144system.cpu.iq.iqSquashedOperandsExamined 143558304 # Number of squashed operands that are examined and possibly removed from graph
145system.cpu.iq.iqSquashedNonSpecRemoved 308585 # Number of squashed non-spec instructions that were removed
146system.cpu.iq.issued_per_cycle::samples 208872334 # Number of insts issued each cycle
147system.cpu.iq.issued_per_cycle::mean 1.815068 # Number of insts issued each cycle
148system.cpu.iq.issued_per_cycle::stdev 1.996247 # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::0 82047947 39.28% 39.28% # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::1 34785806 16.65% 55.94% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::2 24508634 11.73% 67.67% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::3 18508923 8.86% 76.53% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::4 21724585 10.40% 86.93% # Number of insts issued each cycle
155system.cpu.iq.issued_per_cycle::5 15318663 7.33% 94.27% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::6 8418302 4.03% 98.30% # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::7 2689665 1.29% 99.58% # Number of insts issued each cycle
158system.cpu.iq.issued_per_cycle::8 869809 0.42% 100.00% # Number of insts issued each cycle
159system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
160system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
161system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
162system.cpu.iq.issued_per_cycle::total 208872334 # Number of insts issued each cycle
163system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
164system.cpu.iq.fu_full::IntAlu 2261 0.01% 0.01% # attempts to use FU when none available
165system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
166system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
167system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
168system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
169system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
170system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
171system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
172system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
173system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
174system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdFloatAdd 10246 0.06% 0.10% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatCmp 2469 0.01% 0.12% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
189system.cpu.iq.fu_full::SimdFloatMisc 64552 0.37% 0.49% # attempts to use FU when none available
190system.cpu.iq.fu_full::SimdFloatMult 790 0.00% 0.49% # attempts to use FU when none available
191system.cpu.iq.fu_full::SimdFloatMultAcc 177361 1.02% 1.52% # attempts to use FU when none available
192system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
193system.cpu.iq.fu_full::MemRead 9662090 55.64% 57.16% # attempts to use FU when none available
194system.cpu.iq.fu_full::MemWrite 7440153 42.84% 100.00% # attempts to use FU when none available
195system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
196system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
197system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
198system.cpu.iq.FU_type_0::IntAlu 129612173 34.19% 34.19% # Type of FU issued
199system.cpu.iq.FU_type_0::IntMult 2147283 0.57% 34.75% # Type of FU issued
200system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
201system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
202system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
203system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued
204system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued
205system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued
206system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued
207system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
208system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdCmp 15 0.00% 34.75% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdFloatAdd 6745842 1.78% 36.53% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatCmp 8678031 2.29% 38.82% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatCvt 3497767 0.92% 39.75% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatDiv 1584514 0.42% 40.16% # Type of FU issued
223system.cpu.iq.FU_type_0::SimdFloatMisc 21146877 5.58% 45.74% # Type of FU issued
224system.cpu.iq.FU_type_0::SimdFloatMult 7187357 1.90% 47.64% # Type of FU issued
225system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146686 1.89% 49.52% # Type of FU issued
226system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
227system.cpu.iq.FU_type_0::MemRead 103748568 27.37% 76.93% # Type of FU issued
228system.cpu.iq.FU_type_0::MemWrite 87447038 23.07% 100.00% # Type of FU issued
229system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
230system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
231system.cpu.iq.FU_type_0::total 379117437 # Type of FU issued
232system.cpu.iq.rate 1.814089 # Inst issue rate
233system.cpu.iq.fu_busy_cnt 17365346 # FU busy when requested
234system.cpu.iq.fu_busy_rate 0.045805 # FU busy rate (busy events/executed inst)
235system.cpu.iq.int_inst_queue_reads 735356252 # Number of integer instruction queue reads
236system.cpu.iq.int_inst_queue_writes 310675933 # Number of integer instruction queue writes
237system.cpu.iq.int_inst_queue_wakeup_accesses 251537712 # Number of integer instruction queue wakeup accesses
238system.cpu.iq.fp_inst_queue_reads 250923168 # Number of floating instruction queue reads
239system.cpu.iq.fp_inst_queue_writes 133847541 # Number of floating instruction queue writes
240system.cpu.iq.fp_inst_queue_wakeup_accesses 118277096 # Number of floating instruction queue wakeup accesses
241system.cpu.iq.int_alu_accesses 267613476 # Number of integer alu accesses
242system.cpu.iq.fp_alu_accesses 128869307 # Number of floating point alu accesses
243system.cpu.iew.lsq.thread0.forwLoads 7295740 # Number of loads that had data forwarded from stores
244system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
245system.cpu.iew.lsq.thread0.squashedLoads 14155127 # Number of loads squashed
246system.cpu.iew.lsq.thread0.ignoredResponses 112471 # Number of memory responses ignored because the instruction is squashed
247system.cpu.iew.lsq.thread0.memOrderViolation 8340 # Number of memory ordering violations
248system.cpu.iew.lsq.thread0.squashedStores 10733989 # Number of stores squashed
249system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
250system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
251system.cpu.iew.lsq.thread0.rescheduledLoads 274 # Number of loads that were rescheduled
252system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
253system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
254system.cpu.iew.iewSquashCycles 7613691 # Number of cycles IEW is squashing
255system.cpu.iew.iewBlockCycles 19337 # Number of cycles IEW is blocking
256system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
257system.cpu.iew.iewDispatchedInsts 398169516 # Number of instructions dispatched to IQ
258system.cpu.iew.iewDispSquashedInsts 2638152 # Number of squashed instructions skipped by dispatch
259system.cpu.iew.iewDispLoadInsts 108804127 # Number of dispatched load instructions
260system.cpu.iew.iewDispStoreInsts 93109820 # Number of dispatched store instructions
261system.cpu.iew.iewDispNonSpecInsts 3853005 # Number of dispatched non-speculative instructions
262system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
263system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
264system.cpu.iew.memOrderViolationEvents 8340 # Number of memory order violations
265system.cpu.iew.predictedTakenIncorrect 3192687 # Number of branches that were predicted taken incorrectly
266system.cpu.iew.predictedNotTakenIncorrect 308539 # Number of branches that were predicted not taken incorrectly
267system.cpu.iew.branchMispredicts 3501226 # Number of branch mispredicts detected at execute
268system.cpu.iew.iewExecutedInsts 373035381 # Number of executed instructions
269system.cpu.iew.iewExecLoadInsts 102118243 # Number of load instructions executed
270system.cpu.iew.iewExecSquashedInsts 6082056 # Number of squashed instructions skipped in execute
271system.cpu.iew.exec_swp 0 # number of swp insts executed
272system.cpu.iew.exec_nop 47248 # number of nop insts executed
273system.cpu.iew.exec_refs 188073317 # number of memory reference insts executed
274system.cpu.iew.exec_branches 32214551 # Number of branches executed
275system.cpu.iew.exec_stores 85955074 # Number of stores executed
276system.cpu.iew.exec_rate 1.784986 # Inst execution rate
277system.cpu.iew.wb_sent 370819014 # cumulative count of insts sent to commit
278system.cpu.iew.wb_count 369814808 # cumulative count of insts written-back
279system.cpu.iew.wb_producers 175635069 # num instructions producing a value
280system.cpu.iew.wb_consumers 345639533 # num instructions consuming a value
281system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
282system.cpu.iew.wb_rate 1.769576 # insts written-back per cycle
283system.cpu.iew.wb_fanout 0.508145 # average fanout of values written-back
284system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
285system.cpu.commit.commitCommittedInsts 273038870 # The number of committed instructions
286system.cpu.commit.commitCommittedOps 349066646 # The number of committed instructions
287system.cpu.commit.commitSquashedInsts 49103053 # The number of squashed insts skipped by commit
288system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
289system.cpu.commit.branchMispredicts 3227876 # The number of times a branch was mispredicted
290system.cpu.commit.committed_per_cycle::samples 201258644 # Number of insts commited each cycle
291system.cpu.commit.committed_per_cycle::mean 1.734418 # Number of insts commited each cycle
292system.cpu.commit.committed_per_cycle::stdev 2.321139 # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::0 89876372 44.66% 44.66% # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::1 39560210 19.66% 64.31% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::2 17969648 8.93% 73.24% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::3 13168483 6.54% 79.79% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::4 14551255 7.23% 87.02% # Number of insts commited each cycle
299system.cpu.commit.committed_per_cycle::5 7589820 3.77% 90.79% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::6 3505620 1.74% 92.53% # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::7 3424037 1.70% 94.23% # Number of insts commited each cycle
302system.cpu.commit.committed_per_cycle::8 11613199 5.77% 100.00% # Number of insts commited each cycle
303system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
304system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
305system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
306system.cpu.commit.committed_per_cycle::total 201258644 # Number of insts commited each cycle
307system.cpu.commit.committedInsts 273038870 # Number of instructions committed
308system.cpu.commit.committedOps 349066646 # Number of ops (including micro ops) committed
309system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
310system.cpu.commit.refs 177024831 # Number of memory references committed
311system.cpu.commit.loads 94649000 # Number of loads committed
312system.cpu.commit.membars 11033 # Number of memory barriers committed
313system.cpu.commit.branches 30521879 # Number of branches committed
314system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
315system.cpu.commit.int_insts 279585929 # Number of committed integer instructions.
316system.cpu.commit.function_calls 6225114 # Number of function calls committed.
317system.cpu.commit.bw_lim_events 11613199 # number cycles where commit BW limit reached
318system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
319system.cpu.rob.rob_reads 587812621 # The number of ROB reads
320system.cpu.rob.rob_writes 803956224 # The number of ROB writes
321system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself
322system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling
323system.cpu.committedInsts 273038258 # Number of Instructions Simulated
324system.cpu.committedOps 349066034 # Number of Ops (including micro ops) Simulated
325system.cpu.committedInsts_total 273038258 # Number of Instructions Simulated
326system.cpu.cpi 0.765406 # CPI: Cycles Per Instruction
327system.cpu.cpi_total 0.765406 # CPI: Total CPI of All Threads
328system.cpu.ipc 1.306497 # IPC: Instructions Per Cycle
329system.cpu.ipc_total 1.306497 # IPC: Total IPC of All Threads
330system.cpu.int_regfile_reads 1781918480 # number of integer regfile reads
331system.cpu.int_regfile_writes 235832393 # number of integer regfile writes
332system.cpu.fp_regfile_reads 188783884 # number of floating regfile reads
333system.cpu.fp_regfile_writes 133870920 # number of floating regfile writes
334system.cpu.misc_regfile_reads 1003409978 # number of misc regfile reads
335system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes
336system.cpu.icache.replacements 14108 # number of replacements
337system.cpu.icache.tagsinuse 1842.733120 # Cycle average of tags in use
338system.cpu.icache.total_refs 41220872 # Total number of references to valid blocks.
339system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks.
340system.cpu.icache.avg_refs 2578.238179 # Average number of references to valid blocks.
341system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
342system.cpu.icache.occ_blocks::cpu.inst 1842.733120 # Average occupied blocks per requestor
343system.cpu.icache.occ_percent::cpu.inst 0.899772 # Average percentage of cache occupancy
344system.cpu.icache.occ_percent::total 0.899772 # Average percentage of cache occupancy
345system.cpu.icache.ReadReq_hits::cpu.inst 41220872 # number of ReadReq hits
346system.cpu.icache.ReadReq_hits::total 41220872 # number of ReadReq hits
347system.cpu.icache.demand_hits::cpu.inst 41220872 # number of demand (read+write) hits
348system.cpu.icache.demand_hits::total 41220872 # number of demand (read+write) hits
349system.cpu.icache.overall_hits::cpu.inst 41220872 # number of overall hits
350system.cpu.icache.overall_hits::total 41220872 # number of overall hits
351system.cpu.icache.ReadReq_misses::cpu.inst 16648 # number of ReadReq misses
352system.cpu.icache.ReadReq_misses::total 16648 # number of ReadReq misses
353system.cpu.icache.demand_misses::cpu.inst 16648 # number of demand (read+write) misses
354system.cpu.icache.demand_misses::total 16648 # number of demand (read+write) misses
355system.cpu.icache.overall_misses::cpu.inst 16648 # number of overall misses
356system.cpu.icache.overall_misses::total 16648 # number of overall misses
357system.cpu.icache.ReadReq_miss_latency::cpu.inst 201025000 # number of ReadReq miss cycles
358system.cpu.icache.ReadReq_miss_latency::total 201025000 # number of ReadReq miss cycles
359system.cpu.icache.demand_miss_latency::cpu.inst 201025000 # number of demand (read+write) miss cycles
360system.cpu.icache.demand_miss_latency::total 201025000 # number of demand (read+write) miss cycles
361system.cpu.icache.overall_miss_latency::cpu.inst 201025000 # number of overall miss cycles
362system.cpu.icache.overall_miss_latency::total 201025000 # number of overall miss cycles
363system.cpu.icache.ReadReq_accesses::cpu.inst 41237520 # number of ReadReq accesses(hits+misses)
364system.cpu.icache.ReadReq_accesses::total 41237520 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.demand_accesses::cpu.inst 41237520 # number of demand (read+write) accesses
366system.cpu.icache.demand_accesses::total 41237520 # number of demand (read+write) accesses
367system.cpu.icache.overall_accesses::cpu.inst 41237520 # number of overall (read+write) accesses
368system.cpu.icache.overall_accesses::total 41237520 # number of overall (read+write) accesses
369system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000404 # miss rate for ReadReq accesses
370system.cpu.icache.demand_miss_rate::cpu.inst 0.000404 # miss rate for demand accesses
371system.cpu.icache.overall_miss_rate::cpu.inst 0.000404 # miss rate for overall accesses
372system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12075.024027 # average ReadReq miss latency
373system.cpu.icache.demand_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency
374system.cpu.icache.overall_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency
375system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
376system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
377system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
380system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
381system.cpu.icache.fast_writes 0 # number of fast writes performed
382system.cpu.icache.cache_copies 0 # number of cache copies performed
383system.cpu.icache.ReadReq_mshr_hits::cpu.inst 637 # number of ReadReq MSHR hits
384system.cpu.icache.ReadReq_mshr_hits::total 637 # number of ReadReq MSHR hits
385system.cpu.icache.demand_mshr_hits::cpu.inst 637 # number of demand (read+write) MSHR hits
386system.cpu.icache.demand_mshr_hits::total 637 # number of demand (read+write) MSHR hits
387system.cpu.icache.overall_mshr_hits::cpu.inst 637 # number of overall MSHR hits
388system.cpu.icache.overall_mshr_hits::total 637 # number of overall MSHR hits
389system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16011 # number of ReadReq MSHR misses
390system.cpu.icache.ReadReq_mshr_misses::total 16011 # number of ReadReq MSHR misses
391system.cpu.icache.demand_mshr_misses::cpu.inst 16011 # number of demand (read+write) MSHR misses
392system.cpu.icache.demand_mshr_misses::total 16011 # number of demand (read+write) MSHR misses
393system.cpu.icache.overall_mshr_misses::cpu.inst 16011 # number of overall MSHR misses
394system.cpu.icache.overall_mshr_misses::total 16011 # number of overall MSHR misses
395system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 135953500 # number of ReadReq MSHR miss cycles
396system.cpu.icache.ReadReq_mshr_miss_latency::total 135953500 # number of ReadReq MSHR miss cycles
397system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135953500 # number of demand (read+write) MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::total 135953500 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135953500 # number of overall MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::total 135953500 # number of overall MSHR miss cycles
401system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for ReadReq accesses
402system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for demand accesses
403system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for overall accesses
404system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8491.256011 # average ReadReq mshr miss latency
405system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8491.256011 # average overall mshr miss latency
406system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8491.256011 # average overall mshr miss latency
407system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
408system.cpu.dcache.replacements 1410 # number of replacements
409system.cpu.dcache.tagsinuse 3098.497902 # Cycle average of tags in use
410system.cpu.dcache.total_refs 176602100 # Total number of references to valid blocks.
411system.cpu.dcache.sampled_refs 4594 # Sample count of references to valid blocks.
412system.cpu.dcache.avg_refs 38441.902481 # Average number of references to valid blocks.
413system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
414system.cpu.dcache.occ_blocks::cpu.data 3098.497902 # Average occupied blocks per requestor
415system.cpu.dcache.occ_percent::cpu.data 0.756469 # Average percentage of cache occupancy
416system.cpu.dcache.occ_percent::total 0.756469 # Average percentage of cache occupancy
417system.cpu.dcache.ReadReq_hits::cpu.data 94546395 # number of ReadReq hits
418system.cpu.dcache.ReadReq_hits::total 94546395 # number of ReadReq hits
419system.cpu.dcache.WriteReq_hits::cpu.data 82033205 # number of WriteReq hits
420system.cpu.dcache.WriteReq_hits::total 82033205 # number of WriteReq hits
421system.cpu.dcache.LoadLockedReq_hits::cpu.data 11358 # number of LoadLockedReq hits
422system.cpu.dcache.LoadLockedReq_hits::total 11358 # number of LoadLockedReq hits
423system.cpu.dcache.StoreCondReq_hits::cpu.data 11114 # number of StoreCondReq hits
424system.cpu.dcache.StoreCondReq_hits::total 11114 # number of StoreCondReq hits
425system.cpu.dcache.demand_hits::cpu.data 176579600 # number of demand (read+write) hits
426system.cpu.dcache.demand_hits::total 176579600 # number of demand (read+write) hits
427system.cpu.dcache.overall_hits::cpu.data 176579600 # number of overall hits
428system.cpu.dcache.overall_hits::total 176579600 # number of overall hits
429system.cpu.dcache.ReadReq_misses::cpu.data 3383 # number of ReadReq misses
430system.cpu.dcache.ReadReq_misses::total 3383 # number of ReadReq misses
431system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses
432system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses
433system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
434system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
435system.cpu.dcache.demand_misses::cpu.data 22872 # number of demand (read+write) misses
436system.cpu.dcache.demand_misses::total 22872 # number of demand (read+write) misses
437system.cpu.dcache.overall_misses::cpu.data 22872 # number of overall misses
438system.cpu.dcache.overall_misses::total 22872 # number of overall misses
439system.cpu.dcache.ReadReq_miss_latency::cpu.data 111712500 # number of ReadReq miss cycles
440system.cpu.dcache.ReadReq_miss_latency::total 111712500 # number of ReadReq miss cycles
441system.cpu.dcache.WriteReq_miss_latency::cpu.data 649715000 # number of WriteReq miss cycles
442system.cpu.dcache.WriteReq_miss_latency::total 649715000 # number of WriteReq miss cycles
443system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles
444system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles
445system.cpu.dcache.demand_miss_latency::cpu.data 761427500 # number of demand (read+write) miss cycles
446system.cpu.dcache.demand_miss_latency::total 761427500 # number of demand (read+write) miss cycles
447system.cpu.dcache.overall_miss_latency::cpu.data 761427500 # number of overall miss cycles
448system.cpu.dcache.overall_miss_latency::total 761427500 # number of overall miss cycles
449system.cpu.dcache.ReadReq_accesses::cpu.data 94549778 # number of ReadReq accesses(hits+misses)
450system.cpu.dcache.ReadReq_accesses::total 94549778 # number of ReadReq accesses(hits+misses)
451system.cpu.dcache.WriteReq_accesses::cpu.data 82052694 # number of WriteReq accesses(hits+misses)
452system.cpu.dcache.WriteReq_accesses::total 82052694 # number of WriteReq accesses(hits+misses)
453system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11360 # number of LoadLockedReq accesses(hits+misses)
454system.cpu.dcache.LoadLockedReq_accesses::total 11360 # number of LoadLockedReq accesses(hits+misses)
455system.cpu.dcache.StoreCondReq_accesses::cpu.data 11114 # number of StoreCondReq accesses(hits+misses)
456system.cpu.dcache.StoreCondReq_accesses::total 11114 # number of StoreCondReq accesses(hits+misses)
457system.cpu.dcache.demand_accesses::cpu.data 176602472 # number of demand (read+write) accesses
458system.cpu.dcache.demand_accesses::total 176602472 # number of demand (read+write) accesses
459system.cpu.dcache.overall_accesses::cpu.data 176602472 # number of overall (read+write) accesses
460system.cpu.dcache.overall_accesses::total 176602472 # number of overall (read+write) accesses
461system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000036 # miss rate for ReadReq accesses
462system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses
463system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000176 # miss rate for LoadLockedReq accesses
464system.cpu.dcache.demand_miss_rate::cpu.data 0.000130 # miss rate for demand accesses
465system.cpu.dcache.overall_miss_rate::cpu.data 0.000130 # miss rate for overall accesses
466system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33021.726278 # average ReadReq miss latency
467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33337.523731 # average WriteReq miss latency
468system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency
469system.cpu.dcache.demand_avg_miss_latency::cpu.data 33290.814096 # average overall miss latency
470system.cpu.dcache.overall_avg_miss_latency::cpu.data 33290.814096 # average overall miss latency
471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
472system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked
473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
475system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
476system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked
477system.cpu.dcache.fast_writes 0 # number of fast writes performed
478system.cpu.dcache.cache_copies 0 # number of cache copies performed
479system.cpu.dcache.writebacks::writebacks 1034 # number of writebacks
480system.cpu.dcache.writebacks::total 1034 # number of writebacks
481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1633 # number of ReadReq MSHR hits
482system.cpu.dcache.ReadReq_mshr_hits::total 1633 # number of ReadReq MSHR hits
483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16622 # number of WriteReq MSHR hits
484system.cpu.dcache.WriteReq_mshr_hits::total 16622 # number of WriteReq MSHR hits
485system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
486system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
487system.cpu.dcache.demand_mshr_hits::cpu.data 18255 # number of demand (read+write) MSHR hits
488system.cpu.dcache.demand_mshr_hits::total 18255 # number of demand (read+write) MSHR hits
489system.cpu.dcache.overall_mshr_hits::cpu.data 18255 # number of overall MSHR hits
490system.cpu.dcache.overall_mshr_hits::total 18255 # number of overall MSHR hits
491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1750 # number of ReadReq MSHR misses
492system.cpu.dcache.ReadReq_mshr_misses::total 1750 # number of ReadReq MSHR misses
493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2867 # number of WriteReq MSHR misses
494system.cpu.dcache.WriteReq_mshr_misses::total 2867 # number of WriteReq MSHR misses
495system.cpu.dcache.demand_mshr_misses::cpu.data 4617 # number of demand (read+write) MSHR misses
496system.cpu.dcache.demand_mshr_misses::total 4617 # number of demand (read+write) MSHR misses
497system.cpu.dcache.overall_mshr_misses::cpu.data 4617 # number of overall MSHR misses
498system.cpu.dcache.overall_mshr_misses::total 4617 # number of overall MSHR misses
499system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53344000 # number of ReadReq MSHR miss cycles
500system.cpu.dcache.ReadReq_mshr_miss_latency::total 53344000 # number of ReadReq MSHR miss cycles
501system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101787500 # number of WriteReq MSHR miss cycles
502system.cpu.dcache.WriteReq_mshr_miss_latency::total 101787500 # number of WriteReq MSHR miss cycles
503system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155131500 # number of demand (read+write) MSHR miss cycles
504system.cpu.dcache.demand_mshr_miss_latency::total 155131500 # number of demand (read+write) MSHR miss cycles
505system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155131500 # number of overall MSHR miss cycles
506system.cpu.dcache.overall_mshr_miss_latency::total 155131500 # number of overall MSHR miss cycles
507system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
508system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
509system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses
510system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
511system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30482.285714 # average ReadReq mshr miss latency
512system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35503.139170 # average WriteReq mshr miss latency
513system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33600.064977 # average overall mshr miss latency
514system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33600.064977 # average overall mshr miss latency
515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
516system.cpu.l2cache.replacements 57 # number of replacements
517system.cpu.l2cache.tagsinuse 3892.486015 # Cycle average of tags in use
518system.cpu.l2cache.total_refs 13341 # Total number of references to valid blocks.
519system.cpu.l2cache.sampled_refs 5352 # Sample count of references to valid blocks.
520system.cpu.l2cache.avg_refs 2.492713 # Average number of references to valid blocks.
521system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
522system.cpu.l2cache.occ_blocks::writebacks 378.577721 # Average occupied blocks per requestor
523system.cpu.l2cache.occ_blocks::cpu.inst 2756.979421 # Average occupied blocks per requestor
524system.cpu.l2cache.occ_blocks::cpu.data 756.928873 # Average occupied blocks per requestor
525system.cpu.l2cache.occ_percent::writebacks 0.011553 # Average percentage of cache occupancy
526system.cpu.l2cache.occ_percent::cpu.inst 0.084136 # Average percentage of cache occupancy
527system.cpu.l2cache.occ_percent::cpu.data 0.023100 # Average percentage of cache occupancy
528system.cpu.l2cache.occ_percent::total 0.118789 # Average percentage of cache occupancy
529system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits
530system.cpu.l2cache.ReadReq_hits::cpu.data 288 # number of ReadReq hits
531system.cpu.l2cache.ReadReq_hits::total 13258 # number of ReadReq hits
532system.cpu.l2cache.Writeback_hits::writebacks 1034 # number of Writeback hits
533system.cpu.l2cache.Writeback_hits::total 1034 # number of Writeback hits
534system.cpu.l2cache.ReadExReq_hits::cpu.data 19 # number of ReadExReq hits
535system.cpu.l2cache.ReadExReq_hits::total 19 # number of ReadExReq hits
536system.cpu.l2cache.demand_hits::cpu.inst 12970 # number of demand (read+write) hits
537system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits
538system.cpu.l2cache.demand_hits::total 13277 # number of demand (read+write) hits
539system.cpu.l2cache.overall_hits::cpu.inst 12970 # number of overall hits
540system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits
541system.cpu.l2cache.overall_hits::total 13277 # number of overall hits
542system.cpu.l2cache.ReadReq_misses::cpu.inst 3018 # number of ReadReq misses
543system.cpu.l2cache.ReadReq_misses::cpu.data 1461 # number of ReadReq misses
544system.cpu.l2cache.ReadReq_misses::total 4479 # number of ReadReq misses
545system.cpu.l2cache.UpgradeReq_misses::cpu.data 23 # number of UpgradeReq misses
546system.cpu.l2cache.UpgradeReq_misses::total 23 # number of UpgradeReq misses
547system.cpu.l2cache.ReadExReq_misses::cpu.data 2826 # number of ReadExReq misses
548system.cpu.l2cache.ReadExReq_misses::total 2826 # number of ReadExReq misses
549system.cpu.l2cache.demand_misses::cpu.inst 3018 # number of demand (read+write) misses
550system.cpu.l2cache.demand_misses::cpu.data 4287 # number of demand (read+write) misses
551system.cpu.l2cache.demand_misses::total 7305 # number of demand (read+write) misses
552system.cpu.l2cache.overall_misses::cpu.inst 3018 # number of overall misses
553system.cpu.l2cache.overall_misses::cpu.data 4287 # number of overall misses
554system.cpu.l2cache.overall_misses::total 7305 # number of overall misses
555system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 103392000 # number of ReadReq miss cycles
556system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50287500 # number of ReadReq miss cycles
557system.cpu.l2cache.ReadReq_miss_latency::total 153679500 # number of ReadReq miss cycles
558system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97429500 # number of ReadExReq miss cycles
559system.cpu.l2cache.ReadExReq_miss_latency::total 97429500 # number of ReadExReq miss cycles
560system.cpu.l2cache.demand_miss_latency::cpu.inst 103392000 # number of demand (read+write) miss cycles
561system.cpu.l2cache.demand_miss_latency::cpu.data 147717000 # number of demand (read+write) miss cycles
562system.cpu.l2cache.demand_miss_latency::total 251109000 # number of demand (read+write) miss cycles
563system.cpu.l2cache.overall_miss_latency::cpu.inst 103392000 # number of overall miss cycles
564system.cpu.l2cache.overall_miss_latency::cpu.data 147717000 # number of overall miss cycles
565system.cpu.l2cache.overall_miss_latency::total 251109000 # number of overall miss cycles
566system.cpu.l2cache.ReadReq_accesses::cpu.inst 15988 # number of ReadReq accesses(hits+misses)
567system.cpu.l2cache.ReadReq_accesses::cpu.data 1749 # number of ReadReq accesses(hits+misses)
568system.cpu.l2cache.ReadReq_accesses::total 17737 # number of ReadReq accesses(hits+misses)
569system.cpu.l2cache.Writeback_accesses::writebacks 1034 # number of Writeback accesses(hits+misses)
570system.cpu.l2cache.Writeback_accesses::total 1034 # number of Writeback accesses(hits+misses)
571system.cpu.l2cache.UpgradeReq_accesses::cpu.data 23 # number of UpgradeReq accesses(hits+misses)
572system.cpu.l2cache.UpgradeReq_accesses::total 23 # number of UpgradeReq accesses(hits+misses)
573system.cpu.l2cache.ReadExReq_accesses::cpu.data 2845 # number of ReadExReq accesses(hits+misses)
574system.cpu.l2cache.ReadExReq_accesses::total 2845 # number of ReadExReq accesses(hits+misses)
575system.cpu.l2cache.demand_accesses::cpu.inst 15988 # number of demand (read+write) accesses
576system.cpu.l2cache.demand_accesses::cpu.data 4594 # number of demand (read+write) accesses
577system.cpu.l2cache.demand_accesses::total 20582 # number of demand (read+write) accesses
578system.cpu.l2cache.overall_accesses::cpu.inst 15988 # number of overall (read+write) accesses
579system.cpu.l2cache.overall_accesses::cpu.data 4594 # number of overall (read+write) accesses
580system.cpu.l2cache.overall_accesses::total 20582 # number of overall (read+write) accesses
581system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.188767 # miss rate for ReadReq accesses
582system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835334 # miss rate for ReadReq accesses
583system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
584system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993322 # miss rate for ReadExReq accesses
585system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188767 # miss rate for demand accesses
586system.cpu.l2cache.demand_miss_rate::cpu.data 0.933174 # miss rate for demand accesses
587system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188767 # miss rate for overall accesses
588system.cpu.l2cache.overall_miss_rate::cpu.data 0.933174 # miss rate for overall accesses
589system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34258.449304 # average ReadReq miss latency
590system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34419.917864 # average ReadReq miss latency
591system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.114650 # average ReadExReq miss latency
592system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency
593system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency
594system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency
595system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency
596system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
597system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
598system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
599system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
600system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
601system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
602system.cpu.l2cache.fast_writes 0 # number of fast writes performed
603system.cpu.l2cache.cache_copies 0 # number of cache copies performed
604system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
605system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits
606system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
607system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
608system.cpu.l2cache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits
609system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
610system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
611system.cpu.l2cache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits
612system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits
613system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3008 # number of ReadReq MSHR misses
614system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1416 # number of ReadReq MSHR misses
615system.cpu.l2cache.ReadReq_mshr_misses::total 4424 # number of ReadReq MSHR misses
616system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 23 # number of UpgradeReq MSHR misses
617system.cpu.l2cache.UpgradeReq_mshr_misses::total 23 # number of UpgradeReq MSHR misses
618system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2826 # number of ReadExReq MSHR misses
619system.cpu.l2cache.ReadExReq_mshr_misses::total 2826 # number of ReadExReq MSHR misses
620system.cpu.l2cache.demand_mshr_misses::cpu.inst 3008 # number of demand (read+write) MSHR misses
621system.cpu.l2cache.demand_mshr_misses::cpu.data 4242 # number of demand (read+write) MSHR misses
622system.cpu.l2cache.demand_mshr_misses::total 7250 # number of demand (read+write) MSHR misses
623system.cpu.l2cache.overall_mshr_misses::cpu.inst 3008 # number of overall MSHR misses
624system.cpu.l2cache.overall_mshr_misses::cpu.data 4242 # number of overall MSHR misses
625system.cpu.l2cache.overall_mshr_misses::total 7250 # number of overall MSHR misses
626system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 93473500 # number of ReadReq MSHR miss cycles
627system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44349000 # number of ReadReq MSHR miss cycles
628system.cpu.l2cache.ReadReq_mshr_miss_latency::total 137822500 # number of ReadReq MSHR miss cycles
629system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 713000 # number of UpgradeReq MSHR miss cycles
630system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 713000 # number of UpgradeReq MSHR miss cycles
631system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88418000 # number of ReadExReq MSHR miss cycles
632system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88418000 # number of ReadExReq MSHR miss cycles
633system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93473500 # number of demand (read+write) MSHR miss cycles
634system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132767000 # number of demand (read+write) MSHR miss cycles
635system.cpu.l2cache.demand_mshr_miss_latency::total 226240500 # number of demand (read+write) MSHR miss cycles
636system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93473500 # number of overall MSHR miss cycles
637system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132767000 # number of overall MSHR miss cycles
638system.cpu.l2cache.overall_mshr_miss_latency::total 226240500 # number of overall MSHR miss cycles
639system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for ReadReq accesses
640system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses
641system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
642system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993322 # mshr miss rate for ReadExReq accesses
643system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for demand accesses
644system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for demand accesses
645system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for overall accesses
646system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for overall accesses
647system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.966755 # average ReadReq mshr miss latency
648system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31319.915254 # average ReadReq mshr miss latency
649system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
650system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31287.331918 # average ReadExReq mshr miss latency
651system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency
652system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency
653system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency
654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency
655system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
656
657---------- End Simulation Statistics ----------