1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.111754 # Number of seconds simulated
4sim_ticks 111753553500 # Number of ticks simulated
5final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 210028 # Simulator instruction rate (inst/s)
8host_op_rate 252162 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 85964130 # Simulator tick rate (ticks/s)
10host_mem_usage 334160 # Number of bytes of host memory used
11host_seconds 1300.00 # Real time elapsed on the host
12sim_insts 273037220 # Number of instructions simulated
13sim_ops 327811602 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory
19system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory
--- 225 unchanged lines hidden (view full) ---
249system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ)
250system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ)
251system.physmem_1.averagePower 678.173227 # Core power per rank (mW)
252system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states
253system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states
254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
255system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states
256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
257system.cpu.branchPred.lookups 35971731 # Number of BP lookups
258system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted
259system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect
260system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups
261system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits
262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
263system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage
264system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target.
265system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions.
266system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups.
267system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits.
268system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses.
269system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches.
270system.cpu_clk_domain.clock 500 # Clock period in ticks
271system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
292system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
293system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
294system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
295system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
296system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
297system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
298system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
299system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
300system.cpu.dtb.walker.walks 0 # Table walker walks requested
301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
323system.cpu.dtb.read_accesses 0 # DTB read accesses
324system.cpu.dtb.write_accesses 0 # DTB write accesses
325system.cpu.dtb.inst_accesses 0 # ITB inst accesses
326system.cpu.dtb.hits 0 # DTB hits
327system.cpu.dtb.misses 0 # DTB misses
328system.cpu.dtb.accesses 0 # DTB accesses
329system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
350system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
351system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
352system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
353system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
354system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
355system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
356system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
357system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
358system.cpu.itb.walker.walks 0 # Table walker walks requested
359system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
363system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
364system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
365system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
381system.cpu.itb.read_accesses 0 # DTB read accesses
382system.cpu.itb.write_accesses 0 # DTB write accesses
383system.cpu.itb.inst_accesses 0 # ITB inst accesses
384system.cpu.itb.hits 0 # DTB hits
385system.cpu.itb.misses 0 # DTB misses
386system.cpu.itb.accesses 0 # DTB accesses
387system.cpu.workload.num_syscalls 191 # Number of system calls
388system.cpu.numCycles 223507108 # number of cpu cycles simulated
389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
391system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss
392system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed
393system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered
394system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken
395system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked
--- 275 unchanged lines hidden (view full) ---
671system.cpu.int_regfile_reads 325161919 # number of integer regfile reads
672system.cpu.int_regfile_writes 134094717 # number of integer regfile writes
673system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads
674system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes
675system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads
676system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes
677system.cpu.misc_regfile_reads 1056766060 # number of misc regfile reads
678system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
679system.cpu.dcache.tags.replacements 1542955 # number of replacements
680system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use
681system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks.
682system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks.
683system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks.
684system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit.
685system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor
686system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy
687system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy
688system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
689system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
690system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
691system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
692system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
693system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
694system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses
695system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses
696system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits
697system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits
698system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits
699system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits
700system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits
701system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits
702system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits
703system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits
--- 114 unchanged lines hidden (view full) ---
818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency
819system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency
820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency
821system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency
822system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency
823system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency
824system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency
825system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency
826system.cpu.icache.tags.replacements 726201 # number of replacements
827system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use
828system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks.
829system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks.
830system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks.
831system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit.
832system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor
833system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy
834system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy
835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
836system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
837system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
838system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id
839system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
840system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id
841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
842system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses
843system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses
844system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits
845system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits
846system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits
847system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits
848system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits
849system.cpu.icache.overall_hits::total 81470529 # number of overall hits
850system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses
851system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses
911system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses
912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency
913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency
914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
915system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
917system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
918system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued
919system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified
920system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue
921system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
922system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
923system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing
924system.cpu.l2cache.tags.replacements 0 # number of replacements
925system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use
926system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks.
927system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks.
928system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks.
929system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
930system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor
931system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor
--- 11 unchanged lines hidden (view full) ---
943system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
944system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id
945system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id
946system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # Occupied blocks per task id
947system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id
948system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id
949system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses
950system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses
951system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits
952system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits
953system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits
954system.cpu.l2cache.WritebackClean_hits::total 1046226 # number of WritebackClean hits
955system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
956system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
957system.cpu.l2cache.ReadExReq_hits::cpu.data 219964 # number of ReadExReq hits
958system.cpu.l2cache.ReadExReq_hits::total 219964 # number of ReadExReq hits
--- 168 unchanged lines hidden (view full) ---
1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency
1128system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency
1129system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter.
1130system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1131system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1132system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter.
1133system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1134system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1135system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution
1136system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution
1137system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution
1138system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution
1139system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution
1140system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution
1141system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
1142system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1162system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1163system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram
1164system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks)
1165system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%)
1166system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks)
1167system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
1168system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks)
1169system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
1170system.membus.trans_dist::ReadResp 83887 # Transaction distribution
1171system.membus.trans_dist::UpgradeReq 13 # Transaction distribution
1172system.membus.trans_dist::ReadExReq 730 # Transaction distribution
1173system.membus.trans_dist::ReadExResp 730 # Transaction distribution
1174system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution
1175system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes)
1176system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes)
1177system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes)
--- 18 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.111754 # Number of seconds simulated
4sim_ticks 111753553500 # Number of ticks simulated
5final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 210028 # Simulator instruction rate (inst/s)
8host_op_rate 252162 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 85964130 # Simulator tick rate (ticks/s)
10host_mem_usage 334160 # Number of bytes of host memory used
11host_seconds 1300.00 # Real time elapsed on the host
12sim_insts 273037220 # Number of instructions simulated
13sim_ops 327811602 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory
19system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory
--- 225 unchanged lines hidden (view full) ---
249system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ)
250system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ)
251system.physmem_1.averagePower 678.173227 # Core power per rank (mW)
252system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states
253system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states
254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
255system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states
256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
257system.cpu.branchPred.lookups 35971731 # Number of BP lookups
258system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted
259system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect
260system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups
261system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits
262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
263system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage
264system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target.
265system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions.
266system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups.
267system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits.
268system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses.
269system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches.
270system.cpu_clk_domain.clock 500 # Clock period in ticks
271system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
292system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
293system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
294system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
295system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
296system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
297system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
298system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
299system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
300system.cpu.dtb.walker.walks 0 # Table walker walks requested
301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
323system.cpu.dtb.read_accesses 0 # DTB read accesses
324system.cpu.dtb.write_accesses 0 # DTB write accesses
325system.cpu.dtb.inst_accesses 0 # ITB inst accesses
326system.cpu.dtb.hits 0 # DTB hits
327system.cpu.dtb.misses 0 # DTB misses
328system.cpu.dtb.accesses 0 # DTB accesses
329system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
350system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
351system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
352system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
353system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
354system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
355system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
356system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
357system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
358system.cpu.itb.walker.walks 0 # Table walker walks requested
359system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
363system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
364system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
365system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 14 unchanged lines hidden (view full) ---
380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
381system.cpu.itb.read_accesses 0 # DTB read accesses
382system.cpu.itb.write_accesses 0 # DTB write accesses
383system.cpu.itb.inst_accesses 0 # ITB inst accesses
384system.cpu.itb.hits 0 # DTB hits
385system.cpu.itb.misses 0 # DTB misses
386system.cpu.itb.accesses 0 # DTB accesses
387system.cpu.workload.num_syscalls 191 # Number of system calls
388system.cpu.numCycles 223507108 # number of cpu cycles simulated
389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
391system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss
392system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed
393system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered
394system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken
395system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked
--- 275 unchanged lines hidden (view full) ---
671system.cpu.int_regfile_reads 325161919 # number of integer regfile reads
672system.cpu.int_regfile_writes 134094717 # number of integer regfile writes
673system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads
674system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes
675system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads
676system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes
677system.cpu.misc_regfile_reads 1056766060 # number of misc regfile reads
678system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
679system.cpu.dcache.tags.replacements 1542955 # number of replacements
680system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use
681system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks.
682system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks.
683system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks.
684system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit.
685system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor
686system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy
687system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy
688system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
689system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
690system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
691system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
692system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
693system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
694system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses
695system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses
696system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits
697system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits
698system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits
699system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits
700system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits
701system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits
702system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits
703system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits
--- 114 unchanged lines hidden (view full) ---
818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency
819system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency
820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency
821system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency
822system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency
823system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency
824system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency
825system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency
826system.cpu.icache.tags.replacements 726201 # number of replacements
827system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use
828system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks.
829system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks.
830system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks.
831system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit.
832system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor
833system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy
834system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy
835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
836system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
837system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
838system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id
839system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
840system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id
841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
842system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses
843system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses
844system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits
845system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits
846system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits
847system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits
848system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits
849system.cpu.icache.overall_hits::total 81470529 # number of overall hits
850system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses
851system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses
--- 58 unchanged lines hidden (view full) ---
910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses
911system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses
912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency
913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency
914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
915system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
917system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
918system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued
919system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified
920system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue
921system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
922system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
923system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing
924system.cpu.l2cache.tags.replacements 0 # number of replacements
925system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use
926system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks.
927system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks.
928system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks.
929system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
930system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor
931system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor
--- 11 unchanged lines hidden (view full) ---
943system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
944system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id
945system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id
946system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # Occupied blocks per task id
947system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id
948system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id
949system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses
950system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses
951system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits
952system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits
953system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits
954system.cpu.l2cache.WritebackClean_hits::total 1046226 # number of WritebackClean hits
955system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
956system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
957system.cpu.l2cache.ReadExReq_hits::cpu.data 219964 # number of ReadExReq hits
958system.cpu.l2cache.ReadExReq_hits::total 219964 # number of ReadExReq hits
--- 168 unchanged lines hidden (view full) ---
1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency
1128system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency
1129system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter.
1130system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1131system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1132system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter.
1133system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1134system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1135system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution
1136system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution
1137system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution
1138system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution
1139system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution
1140system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution
1141system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
1142system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1162system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1163system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram
1164system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks)
1165system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%)
1166system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks)
1167system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
1168system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks)
1169system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
1170system.membus.trans_dist::ReadResp 83887 # Transaction distribution
1171system.membus.trans_dist::UpgradeReq 13 # Transaction distribution
1172system.membus.trans_dist::ReadExReq 730 # Transaction distribution
1173system.membus.trans_dist::ReadExResp 730 # Transaction distribution
1174system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution
1175system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes)
1176system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes)
1177system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes)
--- 18 unchanged lines hidden ---