1[root] 2type=Root 3children=system |
4eventq_index=0 |
5full_system=false |
6sim_quantum=0 |
7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
17eventq_index=0 |
18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= --- 5 unchanged lines hidden (view full) --- 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 |
39eventq_index=0 |
40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb |
71eventq_index=0 72fetchBufferSize=64 |
73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 129 130[system.cpu.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 |
137eventq_index=0 |
138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=2 152clk_domain=system.cpu_clk_domain |
153eventq_index=0 |
154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 --- 6 unchanged lines hidden (view full) --- 168cpu_side=system.cpu.dcache_port 169mem_side=system.cpu.toL2Bus.slave[1] 170 171[system.cpu.dcache.tags] 172type=LRU 173assoc=2 174block_size=64 175clk_domain=system.cpu_clk_domain |
176eventq_index=0 |
177hit_latency=2 178size=262144 179 180[system.cpu.dtb] 181type=ArmTLB 182children=walker |
183eventq_index=0 |
184size=64 185walker=system.cpu.dtb.walker 186 187[system.cpu.dtb.walker] 188type=ArmTableWalker 189clk_domain=system.cpu_clk_domain |
190eventq_index=0 |
191num_squash_per_cycle=2 192sys=system 193port=system.cpu.toL2Bus.slave[3] 194 195[system.cpu.fuPool] 196type=FUPool 197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 198FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 |
199eventq_index=0 |
200 201[system.cpu.fuPool.FUList0] 202type=FUDesc 203children=opList 204count=6 |
205eventq_index=0 |
206opList=system.cpu.fuPool.FUList0.opList 207 208[system.cpu.fuPool.FUList0.opList] 209type=OpDesc |
210eventq_index=0 |
211issueLat=1 212opClass=IntAlu 213opLat=1 214 215[system.cpu.fuPool.FUList1] 216type=FUDesc 217children=opList0 opList1 218count=2 |
219eventq_index=0 |
220opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 221 222[system.cpu.fuPool.FUList1.opList0] 223type=OpDesc |
224eventq_index=0 |
225issueLat=1 226opClass=IntMult 227opLat=3 228 229[system.cpu.fuPool.FUList1.opList1] 230type=OpDesc |
231eventq_index=0 |
232issueLat=19 233opClass=IntDiv 234opLat=20 235 236[system.cpu.fuPool.FUList2] 237type=FUDesc 238children=opList0 opList1 opList2 239count=4 |
240eventq_index=0 |
241opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 242 243[system.cpu.fuPool.FUList2.opList0] 244type=OpDesc |
245eventq_index=0 |
246issueLat=1 247opClass=FloatAdd 248opLat=2 249 250[system.cpu.fuPool.FUList2.opList1] 251type=OpDesc |
252eventq_index=0 |
253issueLat=1 254opClass=FloatCmp 255opLat=2 256 257[system.cpu.fuPool.FUList2.opList2] 258type=OpDesc |
259eventq_index=0 |
260issueLat=1 261opClass=FloatCvt 262opLat=2 263 264[system.cpu.fuPool.FUList3] 265type=FUDesc 266children=opList0 opList1 opList2 267count=2 |
268eventq_index=0 |
269opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 270 271[system.cpu.fuPool.FUList3.opList0] 272type=OpDesc |
273eventq_index=0 |
274issueLat=1 275opClass=FloatMult 276opLat=4 277 278[system.cpu.fuPool.FUList3.opList1] 279type=OpDesc |
280eventq_index=0 |
281issueLat=12 282opClass=FloatDiv 283opLat=12 284 285[system.cpu.fuPool.FUList3.opList2] 286type=OpDesc |
287eventq_index=0 |
288issueLat=24 289opClass=FloatSqrt 290opLat=24 291 292[system.cpu.fuPool.FUList4] 293type=FUDesc 294children=opList 295count=0 |
296eventq_index=0 |
297opList=system.cpu.fuPool.FUList4.opList 298 299[system.cpu.fuPool.FUList4.opList] 300type=OpDesc |
301eventq_index=0 |
302issueLat=1 303opClass=MemRead 304opLat=1 305 306[system.cpu.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 |
310eventq_index=0 |
311opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 312 313[system.cpu.fuPool.FUList5.opList00] 314type=OpDesc |
315eventq_index=0 |
316issueLat=1 317opClass=SimdAdd 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList01] 321type=OpDesc |
322eventq_index=0 |
323issueLat=1 324opClass=SimdAddAcc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList02] 328type=OpDesc |
329eventq_index=0 |
330issueLat=1 331opClass=SimdAlu 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList03] 335type=OpDesc |
336eventq_index=0 |
337issueLat=1 338opClass=SimdCmp 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList04] 342type=OpDesc |
343eventq_index=0 |
344issueLat=1 345opClass=SimdCvt 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList05] 349type=OpDesc |
350eventq_index=0 |
351issueLat=1 352opClass=SimdMisc 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList06] 356type=OpDesc |
357eventq_index=0 |
358issueLat=1 359opClass=SimdMult 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList07] 363type=OpDesc |
364eventq_index=0 |
365issueLat=1 366opClass=SimdMultAcc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList08] 370type=OpDesc |
371eventq_index=0 |
372issueLat=1 373opClass=SimdShift 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList09] 377type=OpDesc |
378eventq_index=0 |
379issueLat=1 380opClass=SimdShiftAcc 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList10] 384type=OpDesc |
385eventq_index=0 |
386issueLat=1 387opClass=SimdSqrt 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList11] 391type=OpDesc |
392eventq_index=0 |
393issueLat=1 394opClass=SimdFloatAdd 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc |
399eventq_index=0 |
400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc |
406eventq_index=0 |
407issueLat=1 408opClass=SimdFloatCmp 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList14] 412type=OpDesc |
413eventq_index=0 |
414issueLat=1 415opClass=SimdFloatCvt 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList15] 419type=OpDesc |
420eventq_index=0 |
421issueLat=1 422opClass=SimdFloatDiv 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList16] 426type=OpDesc |
427eventq_index=0 |
428issueLat=1 429opClass=SimdFloatMisc 430opLat=1 431 432[system.cpu.fuPool.FUList5.opList17] 433type=OpDesc |
434eventq_index=0 |
435issueLat=1 436opClass=SimdFloatMult 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList18] 440type=OpDesc |
441eventq_index=0 |
442issueLat=1 443opClass=SimdFloatMultAcc 444opLat=1 445 446[system.cpu.fuPool.FUList5.opList19] 447type=OpDesc |
448eventq_index=0 |
449issueLat=1 450opClass=SimdFloatSqrt 451opLat=1 452 453[system.cpu.fuPool.FUList6] 454type=FUDesc 455children=opList 456count=0 |
457eventq_index=0 |
458opList=system.cpu.fuPool.FUList6.opList 459 460[system.cpu.fuPool.FUList6.opList] 461type=OpDesc |
462eventq_index=0 |
463issueLat=1 464opClass=MemWrite 465opLat=1 466 467[system.cpu.fuPool.FUList7] 468type=FUDesc 469children=opList0 opList1 470count=4 |
471eventq_index=0 |
472opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 473 474[system.cpu.fuPool.FUList7.opList0] 475type=OpDesc |
476eventq_index=0 |
477issueLat=1 478opClass=MemRead 479opLat=1 480 481[system.cpu.fuPool.FUList7.opList1] 482type=OpDesc |
483eventq_index=0 |
484issueLat=1 485opClass=MemWrite 486opLat=1 487 488[system.cpu.fuPool.FUList8] 489type=FUDesc 490children=opList 491count=1 |
492eventq_index=0 |
493opList=system.cpu.fuPool.FUList8.opList 494 495[system.cpu.fuPool.FUList8.opList] 496type=OpDesc |
497eventq_index=0 |
498issueLat=3 499opClass=IprAccess 500opLat=3 501 502[system.cpu.icache] 503type=BaseCache 504children=tags 505addr_ranges=0:18446744073709551615 506assoc=2 507clk_domain=system.cpu_clk_domain |
508eventq_index=0 |
509forward_snoops=true 510hit_latency=2 511is_top_level=true 512max_miss_count=0 513mshrs=4 514prefetch_on_access=false 515prefetcher=Null 516response_latency=2 --- 6 unchanged lines hidden (view full) --- 523cpu_side=system.cpu.icache_port 524mem_side=system.cpu.toL2Bus.slave[0] 525 526[system.cpu.icache.tags] 527type=LRU 528assoc=2 529block_size=64 530clk_domain=system.cpu_clk_domain |
531eventq_index=0 |
532hit_latency=2 533size=131072 534 535[system.cpu.interrupts] 536type=ArmInterrupts |
537eventq_index=0 |
538 539[system.cpu.isa] 540type=ArmISA |
541eventq_index=0 |
542fpsid=1090793632 543id_isar0=34607377 544id_isar1=34677009 545id_isar2=555950401 546id_isar3=17899825 547id_isar4=268501314 548id_isar5=0 549id_mmfr0=3 550id_mmfr1=0 551id_mmfr2=19070976 552id_mmfr3=4027589137 553id_pfr0=49 554id_pfr1=1 555midr=890224640 556 557[system.cpu.itb] 558type=ArmTLB 559children=walker |
560eventq_index=0 |
561size=64 562walker=system.cpu.itb.walker 563 564[system.cpu.itb.walker] 565type=ArmTableWalker 566clk_domain=system.cpu_clk_domain |
567eventq_index=0 |
568num_squash_per_cycle=2 569sys=system 570port=system.cpu.toL2Bus.slave[2] 571 572[system.cpu.l2cache] 573type=BaseCache 574children=tags 575addr_ranges=0:18446744073709551615 576assoc=8 577clk_domain=system.cpu_clk_domain |
578eventq_index=0 |
579forward_snoops=true 580hit_latency=20 581is_top_level=false 582max_miss_count=0 583mshrs=20 584prefetch_on_access=false 585prefetcher=Null 586response_latency=20 --- 6 unchanged lines hidden (view full) --- 593cpu_side=system.cpu.toL2Bus.master[0] 594mem_side=system.membus.slave[1] 595 596[system.cpu.l2cache.tags] 597type=LRU 598assoc=8 599block_size=64 600clk_domain=system.cpu_clk_domain |
601eventq_index=0 |
602hit_latency=20 603size=2097152 604 605[system.cpu.toL2Bus] 606type=CoherentBus 607clk_domain=system.cpu_clk_domain |
608eventq_index=0 |
609header_cycles=1 610system=system 611use_default_range=false 612width=32 613master=system.cpu.l2cache.cpu_side 614slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 615 616[system.cpu.tracer] 617type=ExeTracer |
618eventq_index=0 |
619 620[system.cpu.workload] 621type=LiveProcess 622cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook 623cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing 624egid=100 625env= 626errout=cerr 627euid=100 |
628eventq_index=0 629executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon |
630gid=100 631input=cin 632max_stack_size=67108864 633output=cout 634pid=100 635ppid=99 636simpoint=0 637system=system 638uid=100 639 640[system.cpu_clk_domain] 641type=SrcClockDomain 642clock=500 |
643eventq_index=0 |
644voltage_domain=system.voltage_domain 645 646[system.membus] 647type=CoherentBus 648clk_domain=system.clk_domain |
649eventq_index=0 |
650header_cycles=1 651system=system 652use_default_range=false 653width=8 654master=system.physmem.port 655slave=system.system_port system.cpu.l2cache.mem_side 656 657[system.physmem] 658type=SimpleDRAM 659activation_limit=4 660addr_mapping=RaBaChCo 661banks_per_rank=8 662burst_length=8 663channels=1 664clk_domain=system.clk_domain 665conf_table_reported=true 666device_bus_width=8 667device_rowbuffer_size=1024 668devices_per_rank=8 |
669eventq_index=0 |
670in_addr_map=true 671mem_sched_policy=frfcfs 672null=false 673page_policy=open 674range=0:134217727 675ranks_per_channel=2 676read_buffer_size=32 677static_backend_latency=10000 678static_frontend_latency=10000 679tBURST=5000 680tCL=13750 |
681tRAS=35000 |
682tRCD=13750 683tREFI=7800000 684tRFC=300000 685tRP=13750 |
686tRRD=6250 |
687tWTR=7500 688tXAW=40000 689write_buffer_size=32 |
690write_high_thresh_perc=70 691write_low_thresh_perc=0 |
692port=system.membus.master[0] 693 694[system.voltage_domain] 695type=VoltageDomain |
696eventq_index=0 |
697voltage=1.000000 698 |