| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.225030 # Number of seconds simulated 4sim_ticks 225030243000 # Number of ticks simulated 5final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.225041 # Number of seconds simulated 4sim_ticks 225040911000 # Number of ticks simulated 5final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 131394 # Simulator instruction rate (inst/s) 8host_op_rate 157754 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 108291606 # Simulator tick rate (ticks/s) 10host_mem_usage 275248 # Number of bytes of host memory used 11host_seconds 2078.00 # Real time elapsed on the host | 7host_inst_rate 161529 # Simulator instruction rate (inst/s) 8host_op_rate 193933 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 133133968 # Simulator tick rate (ticks/s) 10host_mem_usage 280148 # Number of bytes of host memory used 11host_seconds 1690.33 # Real time elapsed on the host |
| 12sim_insts 273037855 # Number of instructions simulated 13sim_ops 327812212 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 273037855 # Number of instructions simulated 13sim_ops 327812212 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory 19system.physmem.bytes_read::total 485568 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory 19system.physmem.bytes_read::total 485568 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 7587 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 7587 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 225029996000 # Total gap between requests | 79system.physmem.totGap 225040663000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 7587 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 7587 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation 204system.physmem.totQLat 51456750 # Total ticks spent queuing 205system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM | 190system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation 204system.physmem.totQLat 55497500 # Total ticks spent queuing 205system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst | 209system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst |
| 210system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.02 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 210system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.02 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 6068 # Number of row buffer hits during reads | 220system.physmem.readRowHits 6044 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 29659944.11 # Average gap between requests 225system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 29661350.07 # Average gap between requests 225system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 230system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ) 234system.physmem_0.averagePower 668.664832 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states 236system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states | 230system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ) 234system.physmem_0.averagePower 668.691134 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states 236system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states |
| 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states |
| 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 240system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ) | 240system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ) |
| 242system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 242system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 244system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ) 248system.physmem_1.averagePower 668.764823 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states 250system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states | 244system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ) 248system.physmem_1.averagePower 668.800930 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states 250system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states |
| 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states |
| 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 32430290 # Number of BP lookups | 254system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 32430292 # Number of BP lookups |
| 256system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect | 256system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect |
| 258system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits | 258system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits |
| 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 261system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage | 261system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage |
| 262system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks | 262system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses | 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses |
| 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 191 # Number of system calls | 360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 191 # Number of system calls |
| 390system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states 391system.cpu.numCycles 450060486 # number of cpu cycles simulated | 390system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states 391system.cpu.numCycles 450081822 # number of cpu cycles simulated |
| 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 273037855 # Number of instructions committed 395system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed | 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 273037855 # Number of instructions committed 395system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed |
| 396system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit | 396system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit |
| 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 398system.cpu.cpi 1.648345 # CPI: cycles per instruction 399system.cpu.ipc 0.606669 # IPC: instructions per cycle | 398system.cpu.cpi 1.648423 # CPI: cycles per instruction 399system.cpu.ipc 0.606640 # IPC: instructions per cycle |
| 400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 401system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction 402system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction 403system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 404system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 405system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 406system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 407system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 427system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 428system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 429system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 430system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 327812212 # Class of committed instruction | 400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 401system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction 402system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction 403system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 404system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 405system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 406system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 407system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 427system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 428system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 429system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 430system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 327812212 # Class of committed instruction |
| 435system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 435system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 438system.cpu.dcache.tags.replacements 1355 # number of replacements | 438system.cpu.dcache.tags.replacements 1355 # number of replacements |
| 439system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks. | 439system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks. |
| 441system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. | 441system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. |
| 442system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks. | 442system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks. |
| 443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 444system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy | 444system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy |
| 447system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 451system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 452system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id 453system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id | 447system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 451system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 452system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id 453system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id |
| 454system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses 455system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses 456system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states 457system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits 458system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits 459system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits 460system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits | 454system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses 455system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses 456system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states 457system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits 458system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits 459system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits 460system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits |
| 461system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits 462system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits 463system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 464system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 465system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 466system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits | 461system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits 462system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits 463system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 464system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 465system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 466system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| 467system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits 468system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits 469system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits 470system.cpu.dcache.overall_hits::total 168632427 # number of overall hits | 467system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits 468system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits 469system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits 470system.cpu.dcache.overall_hits::total 168632429 # number of overall hits |
| 471system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses 472system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses | 471system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses 472system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses |
| 473system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses 474system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses | 473system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses 474system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses |
| 475system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses 476system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses | 475system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses 476system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses |
| 477system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses 478system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses 479system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses 480system.cpu.dcache.overall_misses::total 6936 # number of overall misses 481system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles 482system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles 483system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles 484system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles 485system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles 486system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles 487system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles 488system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles 489system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses) 490system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses) | 477system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses 478system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses 479system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses 480system.cpu.dcache.overall_misses::total 6935 # number of overall misses 481system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles 482system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles 483system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles 484system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles 485system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles 486system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles 487system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles 488system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles 489system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses) 490system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses) |
| 491system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 492system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 493system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) 494system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses) 495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 496system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 497system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 498system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) | 491system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 492system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 493system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) 494system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses) 495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 496system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 497system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 498system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| 499system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses 500system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses 501system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses 502system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses | 499system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses 500system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses 501system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses 502system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses |
| 503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 504system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses 506system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 507system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses 508system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses 509system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses 510system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses 511system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses 512system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses | 503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 504system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses 506system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 507system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses 508system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses 509system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses 510system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses 511system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses 512system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses |
| 513system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency 514system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency 515system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency 516system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency 517system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency 518system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency 519system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency 520system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency | 513system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency 514system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency 515system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency 516system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency 517system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency 518system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency 519system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency 520system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency |
| 521system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 524system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 525system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 526system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 527system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks 528system.cpu.dcache.writebacks::total 1010 # number of writebacks 529system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits 530system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits | 521system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 524system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 525system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 526system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 527system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks 528system.cpu.dcache.writebacks::total 1010 # number of writebacks 529system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits 530system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits |
| 531system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits 532system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits 533system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits 534system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits 535system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits 536system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits | 531system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits 532system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits 533system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits 534system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits 535system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits 536system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits |
| 537system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses 538system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses 539system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses 540system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses 541system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 542system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 543system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses 544system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses 545system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses 546system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses | 537system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses 538system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses 539system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses 540system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses 541system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 542system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 543system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses 544system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses 545system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses 546system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses |
| 547system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles 548system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles 549system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles 550system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles 551system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles 552system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles 553system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles 554system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles 555system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles 556system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles | 547system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles 548system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles 549system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles 550system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles 551system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles 552system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles 553system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles 554system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles 555system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles 556system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles |
| 557system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 558system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 559system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 560system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 561system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses 562system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses 563system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 564system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 565system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 566system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 557system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 558system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 559system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 560system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 561system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses 562system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses 563system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 564system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 565system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 566system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 567system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency 568system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency 569system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency 570system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency 571system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency 572system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency 573system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency 574system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency 575system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency 576system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency 577system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 567system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency 568system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency 569system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency 570system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency 571system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency 572system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency 573system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency 574system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency 575system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency 576system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency 577system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 578system.cpu.icache.tags.replacements 38188 # number of replacements | 578system.cpu.icache.tags.replacements 38188 # number of replacements |
| 579system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use 580system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks. | 579system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use 580system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks. |
| 581system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. | 581system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. |
| 582system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks. | 582system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks. |
| 583system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 583system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 584system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor 585system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy 586system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy | 584system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor 585system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy 586system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy |
| 587system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id | 587system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id |
| 588system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id | 588system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id |
| 590system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id 593system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id | 590system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id 593system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id |
| 594system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses 595system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses 596system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states 597system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits 598system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits 599system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits 602system.cpu.icache.overall_hits::total 69819783 # number of overall hits | 594system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses 595system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses 596system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states 597system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits 598system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits 599system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits 602system.cpu.icache.overall_hits::total 69819782 # number of overall hits |
| 603system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses 604system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses 605system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses 606system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses 607system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses 608system.cpu.icache.overall_misses::total 40126 # number of overall misses | 603system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses 604system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses 605system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses 606system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses 607system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses 608system.cpu.icache.overall_misses::total 40126 # number of overall misses |
| 609system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles 610system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles 611system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles 612system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles 613system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles 614system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles 615system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses 618system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses 619system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses 620system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses | 609system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles 610system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles 611system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles 612system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles 613system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles 614system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles 615system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses 618system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses 619system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses 620system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses |
| 621system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses 623system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses 624system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses 625system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses 626system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses | 621system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses 623system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses 624system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses 625system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses 626system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses |
| 627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency 628system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency 629system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency 630system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency 632system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency | 627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency 628system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency 629system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency 630system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency 631system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency 632system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency |
| 633system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 635system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 637system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 638system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu.icache.writebacks::writebacks 38188 # number of writebacks 640system.cpu.icache.writebacks::total 38188 # number of writebacks 641system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses 642system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses 643system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses 644system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses 645system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses 646system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses | 633system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 635system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 637system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 638system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu.icache.writebacks::writebacks 38188 # number of writebacks 640system.cpu.icache.writebacks::total 38188 # number of writebacks 641system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses 642system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses 643system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses 644system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses 645system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses 646system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses |
| 647system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles 648system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles 652system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles | 647system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles 648system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles 652system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles |
| 653system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses 654system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses 655system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses 656system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses 657system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses 658system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses | 653system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses 654system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses 655system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses 656system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses 657system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses 658system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses |
| 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency 660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency 662system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency 664system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency 665system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency 660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency 662system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency 664system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency 665system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 666system.cpu.l2cache.tags.replacements 0 # number of replacements | 666system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 667system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use 668system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks. 669system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks. 670system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks. | 667system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use 668system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. 669system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. 670system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. |
| 671system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 671system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 672system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor 673system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor 674system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor 675system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy 676system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy 677system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy 678system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy 679system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id 680system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 681system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id | 672system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor 673system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor 674system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy 675system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy 676system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy 677system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id 678system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 679system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id |
| 682system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id | 680system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id |
| 683system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id 684system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id 685system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id 686system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses 687system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses 688system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 681system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id 682system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id 683system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id 684system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses 685system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses 686system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 689system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits 690system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits 691system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits 692system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits 693system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 694system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 695system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36700 # number of ReadCleanReq hits 696system.cpu.l2cache.ReadCleanReq_hits::total 36700 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 709system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses 710system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses 711system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses 712system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses 713system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses 714system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses 715system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses 716system.cpu.l2cache.overall_misses::total 7630 # number of overall misses | 687system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits 688system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits 689system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits 690system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits 691system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 692system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 693system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36700 # number of ReadCleanReq hits 694system.cpu.l2cache.ReadCleanReq_hits::total 36700 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 707system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses 708system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses 709system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses 710system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses 711system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses 712system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses 713system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses 714system.cpu.l2cache.overall_misses::total 7630 # number of overall misses |
| 717system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles 718system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles 719system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles 720system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles 721system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles 722system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles 723system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles 724system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles 725system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles 726system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles 727system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles 728system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles | 715system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles 716system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles 717system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles 718system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles 719system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles 720system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles 721system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles 722system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles 723system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles 724system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles 725system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles 726system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles |
| 729system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) 730system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) 731system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) 732system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses) 733system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) 734system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) 735system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40126 # number of ReadCleanReq accesses(hits+misses) 736system.cpu.l2cache.ReadCleanReq_accesses::total 40126 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 749system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses 750system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses 751system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses 752system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses 753system.cpu.l2cache.demand_miss_rate::total 0.170931 # miss rate for demand accesses 754system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses 755system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses 756system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses | 727system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) 728system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) 729system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) 730system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) 733system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40126 # number of ReadCleanReq accesses(hits+misses) 734system.cpu.l2cache.ReadCleanReq_accesses::total 40126 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 747system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses 748system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses 749system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses 750system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses 751system.cpu.l2cache.demand_miss_rate::total 0.170931 # miss rate for demand accesses 752system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses 753system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses 754system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses |
| 757system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency 758system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency 759system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency 760system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency 761system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency 762system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency 763system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency 766system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency | 755system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency 756system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency 757system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency 758system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency 759system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency 760system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency 761system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency 762system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency 763system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency 765system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency 766system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency |
| 769system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 776system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits --- 12 unchanged lines hidden (view full) --- 789system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses 790system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses 791system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses 792system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses 793system.cpu.l2cache.demand_mshr_misses::total 7587 # number of demand (read+write) MSHR misses 794system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses 795system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses 796system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses | 767system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 768system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 769system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 770system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 771system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 772system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 773system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 774system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits --- 12 unchanged lines hidden (view full) --- 787system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses 788system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses 789system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses 790system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses 791system.cpu.l2cache.demand_mshr_misses::total 7587 # number of demand (read+write) MSHR misses 792system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses 793system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses 794system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses |
| 797system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles 798system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles 799system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles 800system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles 801system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles 802system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles 803system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles 804system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles 805system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles 806system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles 807system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles 808system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles | 795system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles 796system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles 797system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles 798system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles 799system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles 800system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles 801system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles 802system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles 803system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles 804system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles 805system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles 806system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles |
| 809system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses 810system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses 811system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses 812system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses 813system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses 814system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses 815system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses 816system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses 817system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses 818system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses 819system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses 820system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses | 807system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses 808system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses 809system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses 810system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses 811system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses 812system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses 813system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses 814system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses 815system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses 816system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses 817system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses 818system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses |
| 821system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency 822system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency 823system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency 824system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency 825system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency 826system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency 827system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency 828system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency 829system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency 830system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency 831system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency 832system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency | 819system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency 820system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency 821system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency 822system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency 823system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency 824system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency 827system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency 830system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency |
| 833system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. 834system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. 835system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 836system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 837system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 838system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 831system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. 832system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. 833system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 834system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 835system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 836system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 839system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 837system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 840system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution 845system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution 846system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution 847system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 865system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 866system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram 867system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks) 868system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 869system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks) 870system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 871system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) 872system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 838system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution 845system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 863system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 864system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram 865system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks) 866system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 867system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks) 868system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 869system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) 870system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 873system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states | 871system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter. 872system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 873system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 874system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 875system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 876system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 877system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states |
| 874system.membus.trans_dist::ReadResp 4733 # Transaction distribution 875system.membus.trans_dist::ReadExReq 2854 # Transaction distribution 876system.membus.trans_dist::ReadExResp 2854 # Transaction distribution 877system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution 878system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes) 879system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes) 880system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes) 881system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 886system.membus.snoop_fanout::stdev 0 # Request fanout histogram 887system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 888system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram 889system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 890system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 891system.membus.snoop_fanout::min_value 0 # Request fanout histogram 892system.membus.snoop_fanout::max_value 0 # Request fanout histogram 893system.membus.snoop_fanout::total 7587 # Request fanout histogram | 878system.membus.trans_dist::ReadResp 4733 # Transaction distribution 879system.membus.trans_dist::ReadExReq 2854 # Transaction distribution 880system.membus.trans_dist::ReadExResp 2854 # Transaction distribution 881system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution 882system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes) 883system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes) 884system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes) 885system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 890system.membus.snoop_fanout::stdev 0 # Request fanout histogram 891system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 892system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram 893system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 894system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 895system.membus.snoop_fanout::min_value 0 # Request fanout histogram 896system.membus.snoop_fanout::max_value 0 # Request fanout histogram 897system.membus.snoop_fanout::total 7587 # Request fanout histogram |
| 894system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks) | 898system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks) |
| 895system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 899system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 896system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks) | 900system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks) |
| 897system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 898 899---------- End Simulation Statistics ---------- | 901system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 902 903---------- End Simulation Statistics ---------- |