| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.215506 # Number of seconds simulated 4sim_ticks 215505832500 # Number of ticks simulated 5final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.215510 # Number of seconds simulated 4sim_ticks 215510486500 # Number of ticks simulated 5final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 114925 # Simulator instruction rate (inst/s) 8host_op_rate 137980 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 90709005 # Simulator tick rate (ticks/s) 10host_mem_usage 317788 # Number of bytes of host memory used 11host_seconds 2375.79 # Real time elapsed on the host | 7host_inst_rate 166248 # Simulator instruction rate (inst/s) 8host_op_rate 199599 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 131220473 # Simulator tick rate (ticks/s) 10host_mem_usage 326292 # Number of bytes of host memory used 11host_seconds 1642.35 # Real time elapsed on the host |
| 12sim_insts 273037857 # Number of instructions simulated 13sim_ops 327812214 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory 18system.physmem.bytes_read::total 485248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory | 12sim_insts 273037857 # Number of instructions simulated 13sim_ops 327812214 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory 18system.physmem.bytes_read::total 485248 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 7582 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 485248 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 485248 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 7582 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 485248 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 485248 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 215505593500 # Total gap between requests | 78system.physmem.totGap 215510247500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 7582 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 7582 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation 203system.physmem.totQLat 52046750 # Total ticks spent queuing 204system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation 203system.physmem.totQLat 52026250 # Total ticks spent queuing 204system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 209system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 6056 # Number of row buffer hits during reads | 219system.physmem.readRowHits 6062 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 28423317.53 # Average gap between requests 224system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 28423931.35 # Average gap between requests 224system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.699601 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states | 229system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.715971 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states 235system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states |
| 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) | 239system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ) |
| 241system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 241system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.806188 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states | 243system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.792285 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 32816945 # Number of BP lookups 254system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted | 253system.cpu.branchPred.lookups 32816918 # Number of BP lookups 254system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted |
| 255system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect | 255system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect |
| 256system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits | 256system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage | 259system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage |
| 260system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst --- 104 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 191 # Number of system calls | 260system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst --- 104 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 191 # Number of system calls |
| 380system.cpu.numCycles 431011665 # number of cpu cycles simulated | 380system.cpu.numCycles 431020973 # number of cpu cycles simulated |
| 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 273037857 # Number of instructions committed 384system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 273037857 # Number of instructions committed 384system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed |
| 385system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit | 385system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit |
| 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 387system.cpu.cpi 1.578578 # CPI: cycles per instruction 388system.cpu.ipc 0.633481 # IPC: instructions per cycle 389system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped | 387system.cpu.cpi 1.578612 # CPI: cycles per instruction 388system.cpu.ipc 0.633468 # IPC: instructions per cycle 389system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped |
| 391system.cpu.dcache.tags.replacements 1354 # number of replacements | 391system.cpu.dcache.tags.replacements 1354 # number of replacements |
| 392system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks. | 392system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks. |
| 394system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. | 394system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. |
| 395system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks. | 395system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks. |
| 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 397system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor | 397system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor |
| 398system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id 406system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id | 398system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id 406system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id |
| 407system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses 408system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses 409system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits 410system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits 411system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits 412system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits | 407system.cpu.dcache.tags.tag_accesses 337448859 # Number of tag accesses 408system.cpu.dcache.tags.data_accesses 337448859 # Number of data accesses 409system.cpu.dcache.ReadReq_hits::cpu.data 86582109 # number of ReadReq hits 410system.cpu.dcache.ReadReq_hits::total 86582109 # number of ReadReq hits 411system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits 412system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits |
| 413system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits 414system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits 415system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 416system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 417system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 418system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits | 413system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits 414system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits 415system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 416system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 417system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 418system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| 419system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits 422system.cpu.dcache.overall_hits::total 168693090 # number of overall hits | 419system.cpu.dcache.demand_hits::cpu.data 168629560 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 168629560 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 168693094 # number of overall hits 422system.cpu.dcache.overall_hits::total 168693094 # number of overall hits |
| 423system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses | 423system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses |
| 425system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses | 425system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses |
| 427system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses 428system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses | 427system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses 428system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses |
| 429system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses 430system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses 431system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses 432system.cpu.dcache.overall_misses::total 7292 # number of overall misses 433system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles 434system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles 437system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles 438system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles 439system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles 440system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles 441system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses) | 429system.cpu.dcache.demand_misses::cpu.data 7285 # number of demand (read+write) misses 430system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses 431system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses 432system.cpu.dcache.overall_misses::total 7290 # number of overall misses 433system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles 434system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles 437system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles 438system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles 439system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles 440system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles 441system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses) |
| 443system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::total 63539 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 449system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 450system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) | 443system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::total 63539 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 449system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 450system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| 451system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses 452system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses 453system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses 454system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses | 451system.cpu.dcache.demand_accesses::cpu.data 168636845 # number of demand (read+write) accesses 452system.cpu.dcache.demand_accesses::total 168636845 # number of demand (read+write) accesses 453system.cpu.dcache.overall_accesses::cpu.data 168700384 # number of overall (read+write) accesses 454system.cpu.dcache.overall_accesses::total 168700384 # number of overall (read+write) accesses |
| 455system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses 456system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 459system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses 460system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses 461system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses 462system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses 464system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses | 455system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses 456system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 459system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses 460system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses 461system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses 462system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses 464system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses |
| 465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency 466system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency 470system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency | 465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency 466system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency 470system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency |
| 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks 482system.cpu.dcache.writebacks::total 1010 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits | 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks 482system.cpu.dcache.writebacks::total 1010 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits |
| 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits 487system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits 488system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits 489system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits 490system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits | 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits 487system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits 488system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits 489system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits 490system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits |
| 491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses 492system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses 495system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 496system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 4508 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses | 491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses 492system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses 495system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 496system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 4508 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses |
| 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles | 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles |
| 505system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles 506system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles | 505system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles 506system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles |
| 507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles 510system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles | 507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles 510system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles |
| 511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 518system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 519system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 520system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 518system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 519system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 520system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency | 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency |
| 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency | 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency |
| 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency | 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency |
| 531system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu.icache.tags.replacements 36873 # number of replacements | 531system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu.icache.tags.replacements 36873 # number of replacements |
| 533system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use 534system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks. | 533system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use 534system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks. |
| 535system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. | 535system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. |
| 536system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks. | 536system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks. |
| 537system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 537system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 538system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor 539system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy 540system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy | 538system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor 539system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy 540system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy |
| 541system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id 544system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id 545system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id 546system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id 547system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id | 541system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id 544system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id 545system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id 546system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id 547system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id |
| 548system.cpu.icache.tags.tag_accesses 145214241 # Number of tag accesses 549system.cpu.icache.tags.data_accesses 145214241 # Number of data accesses 550system.cpu.icache.ReadReq_hits::cpu.inst 72548906 # number of ReadReq hits 551system.cpu.icache.ReadReq_hits::total 72548906 # number of ReadReq hits 552system.cpu.icache.demand_hits::cpu.inst 72548906 # number of demand (read+write) hits 553system.cpu.icache.demand_hits::total 72548906 # number of demand (read+write) hits 554system.cpu.icache.overall_hits::cpu.inst 72548906 # number of overall hits 555system.cpu.icache.overall_hits::total 72548906 # number of overall hits | 548system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses 549system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses 550system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits 551system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits 552system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits 553system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits 554system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits 555system.cpu.icache.overall_hits::total 72548791 # number of overall hits |
| 556system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses 561system.cpu.icache.overall_misses::total 38810 # number of overall misses | 556system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses 561system.cpu.icache.overall_misses::total 38810 # number of overall misses |
| 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 726866500 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 726866500 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 726866500 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 726866500 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 726866500 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 726866500 # number of overall miss cycles 568system.cpu.icache.ReadReq_accesses::cpu.inst 72587716 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 72587716 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 72587716 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 72587716 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 72587716 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 72587716 # number of overall (read+write) accesses | 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles 568system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses |
| 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses | 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses |
| 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18728.845658 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 18728.845658 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 18728.845658 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 18728.845658 # average overall miss latency | 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 19088.843082 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency |
| 586system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38810 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 38810 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 38810 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses | 586system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38810 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 38810 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 38810 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses |
| 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 688057500 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 688057500 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 688057500 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 688057500 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 688057500 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 688057500 # number of overall MSHR miss cycles | 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702029000 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 702029000 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702029000 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 702029000 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702029000 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 702029000 # number of overall MSHR miss cycles |
| 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses | 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses |
| 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17728.871425 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17728.871425 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency | 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency |
| 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.tags.replacements 0 # number of replacements | 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 620system.cpu.l2cache.tags.tagsinuse 4197.344986 # Cycle average of tags in use | 620system.cpu.l2cache.tags.tagsinuse 4197.348676 # Cycle average of tags in use |
| 621system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks. 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 621system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks. 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 625system.cpu.l2cache.tags.occ_blocks::writebacks 353.814355 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200376 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 678.330255 # Average occupied blocks per requestor | 625system.cpu.l2cache.tags.occ_blocks::writebacks 353.816119 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor |
| 628system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy 629system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::total 0.128093 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id 635system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id --- 23 unchanged lines hidden (view full) --- 659system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses 660system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses 661system.cpu.l2cache.demand_misses::cpu.inst 3422 # number of demand (read+write) misses 662system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses 663system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses 664system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses 665system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses 666system.cpu.l2cache.overall_misses::total 7626 # number of overall misses | 628system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy 629system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::total 0.128093 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id 635system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id --- 23 unchanged lines hidden (view full) --- 659system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses 660system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses 661system.cpu.l2cache.demand_misses::cpu.inst 3422 # number of demand (read+write) misses 662system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses 663system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses 664system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses 665system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses 666system.cpu.l2cache.overall_misses::total 7626 # number of overall misses |
| 667system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214130000 # number of ReadExReq miss cycles 668system.cpu.l2cache.ReadExReq_miss_latency::total 214130000 # number of ReadExReq miss cycles 669system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 258275500 # number of ReadCleanReq miss cycles 670system.cpu.l2cache.ReadCleanReq_miss_latency::total 258275500 # number of ReadCleanReq miss cycles 671system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104189000 # number of ReadSharedReq miss cycles 672system.cpu.l2cache.ReadSharedReq_miss_latency::total 104189000 # number of ReadSharedReq miss cycles 673system.cpu.l2cache.demand_miss_latency::cpu.inst 258275500 # number of demand (read+write) miss cycles 674system.cpu.l2cache.demand_miss_latency::cpu.data 318319000 # number of demand (read+write) miss cycles 675system.cpu.l2cache.demand_miss_latency::total 576594500 # number of demand (read+write) miss cycles 676system.cpu.l2cache.overall_miss_latency::cpu.inst 258275500 # number of overall miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.data 318319000 # number of overall miss cycles 678system.cpu.l2cache.overall_miss_latency::total 576594500 # number of overall miss cycles | 667system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214741500 # number of ReadExReq miss cycles 668system.cpu.l2cache.ReadExReq_miss_latency::total 214741500 # number of ReadExReq miss cycles 669system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257334000 # number of ReadCleanReq miss cycles 670system.cpu.l2cache.ReadCleanReq_miss_latency::total 257334000 # number of ReadCleanReq miss cycles 671system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104502500 # number of ReadSharedReq miss cycles 672system.cpu.l2cache.ReadSharedReq_miss_latency::total 104502500 # number of ReadSharedReq miss cycles 673system.cpu.l2cache.demand_miss_latency::cpu.inst 257334000 # number of demand (read+write) miss cycles 674system.cpu.l2cache.demand_miss_latency::cpu.data 319244000 # number of demand (read+write) miss cycles 675system.cpu.l2cache.demand_miss_latency::total 576578000 # number of demand (read+write) miss cycles 676system.cpu.l2cache.overall_miss_latency::cpu.inst 257334000 # number of overall miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.data 319244000 # number of overall miss cycles 678system.cpu.l2cache.overall_miss_latency::total 576578000 # number of overall miss cycles |
| 679system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) 680system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) 681system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) 683system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 38810 # number of ReadCleanReq accesses(hits+misses) 684system.cpu.l2cache.ReadCleanReq_accesses::total 38810 # number of ReadCleanReq accesses(hits+misses) 685system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1641 # number of ReadSharedReq accesses(hits+misses) 686system.cpu.l2cache.ReadSharedReq_accesses::total 1641 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822669 # miss rate for ReadSharedReq accesses 698system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822669 # miss rate for ReadSharedReq accesses 699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088173 # miss rate for demand accesses 700system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses 701system.cpu.l2cache.demand_miss_rate::total 0.176035 # miss rate for demand accesses 702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses 703system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses 704system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses | 679system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) 680system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) 681system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) 683system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 38810 # number of ReadCleanReq accesses(hits+misses) 684system.cpu.l2cache.ReadCleanReq_accesses::total 38810 # number of ReadCleanReq accesses(hits+misses) 685system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1641 # number of ReadSharedReq accesses(hits+misses) 686system.cpu.l2cache.ReadSharedReq_accesses::total 1641 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822669 # miss rate for ReadSharedReq accesses 698system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822669 # miss rate for ReadSharedReq accesses 699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088173 # miss rate for demand accesses 700system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses 701system.cpu.l2cache.demand_miss_rate::total 0.176035 # miss rate for demand accesses 702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses 703system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses 704system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses |
| 705system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency 706system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency 707system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency 708system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency 709system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency 710system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency 711system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency 712system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency 713system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency 714system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency | 705system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency 706system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency 707system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # average ReadCleanReq miss latency 708system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109 # average ReadCleanReq miss latency 709system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259 # average ReadSharedReq miss latency 710system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259 # average ReadSharedReq miss latency 711system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency 712system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency 713system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230 # average overall miss latency 714system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230 # average overall miss latency |
| 717system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.l2cache.fast_writes 0 # number of fast writes performed 724system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 739system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1308 # number of ReadSharedReq MSHR misses 740system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1308 # number of ReadSharedReq MSHR misses 741system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses 743system.cpu.l2cache.demand_mshr_misses::total 7582 # number of demand (read+write) MSHR misses 744system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses 745system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses 746system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses | 717system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.l2cache.fast_writes 0 # number of fast writes performed 724system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 739system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1308 # number of ReadSharedReq MSHR misses 740system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1308 # number of ReadSharedReq MSHR misses 741system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses 743system.cpu.l2cache.demand_mshr_misses::total 7582 # number of demand (read+write) MSHR misses 744system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses 745system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses 746system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses |
| 747system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles 748system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles 749system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles 750system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles 751system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles 752system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles | 747system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles 748system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles 749system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles 750system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles 751system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles 752system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles |
| 759system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses 760system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses 761system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses 762system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088122 # mshr miss rate for ReadCleanReq accesses 763system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses 764system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 # mshr miss rate for demand accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses | 759system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses 760system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses 761system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses 762system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088122 # mshr miss rate for ReadCleanReq accesses 763system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses 764system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 # mshr miss rate for demand accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses |
| 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency 773system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency 774system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency 775system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency 776system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency | 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency 773system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency 774system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency 775system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency 776system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency |
| 783system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 783system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 784system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter. 785system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data. 786system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 787system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 788system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 789system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 784system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution 785system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution 786system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution 787system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution 788system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution 789system.cpu.toL2Bus.trans_dist::ReadCleanReq 38810 # Transaction distribution 790system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution 791system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99591 # Packet count per connected master and slave (bytes) 792system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) 793system.cpu.toL2Bus.pkt_count::total 109851 # Packet count per connected master and slave (bytes) 794system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2483776 # Cumulative packet size per connected master and slave (bytes) 795system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) 796system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) 797system.cpu.toL2Bus.snoops 0 # Total snoops (count) 798system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram | 790system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution 791system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution 792system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution 793system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution 794system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution 795system.cpu.toL2Bus.trans_dist::ReadCleanReq 38810 # Transaction distribution 796system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution 797system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99591 # Packet count per connected master and slave (bytes) 798system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) 799system.cpu.toL2Bus.pkt_count::total 109851 # Packet count per connected master and slave (bytes) 800system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2483776 # Cumulative packet size per connected master and slave (bytes) 801system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) 802system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) 803system.cpu.toL2Bus.snoops 0 # Total snoops (count) 804system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram |
| 799system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 800system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 805system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram 806system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram |
| 801system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 807system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 802system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram | 808system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram 809system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram |
| 804system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 805system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 810system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 811system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 806system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 812system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 807system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 808system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram 809system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) 810system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 811system.cpu.toL2Bus.respLayer0.occupancy 58214498 # Layer occupancy (ticks) 812system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 813system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks) 814system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 826system.membus.snoop_fanout::stdev 0 # Request fanout histogram 827system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 828system.membus.snoop_fanout::0 7582 100.00% 100.00% # Request fanout histogram 829system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 830system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 831system.membus.snoop_fanout::min_value 0 # Request fanout histogram 832system.membus.snoop_fanout::max_value 0 # Request fanout histogram 833system.membus.snoop_fanout::total 7582 # Request fanout histogram | 813system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 814system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram 815system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) 816system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 817system.cpu.toL2Bus.respLayer0.occupancy 58214498 # Layer occupancy (ticks) 818system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 819system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks) 820system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 832system.membus.snoop_fanout::stdev 0 # Request fanout histogram 833system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 834system.membus.snoop_fanout::0 7582 100.00% 100.00% # Request fanout histogram 835system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 836system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 837system.membus.snoop_fanout::min_value 0 # Request fanout histogram 838system.membus.snoop_fanout::max_value 0 # Request fanout histogram 839system.membus.snoop_fanout::total 7582 # Request fanout histogram |
| 834system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) | 840system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks) |
| 835system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 841system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 836system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks) | 842system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks) |
| 837system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 838 839---------- End Simulation Statistics ---------- | 843system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 844 845---------- End Simulation Statistics ---------- |