| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.212377 # Number of seconds simulated 4sim_ticks 212377413000 # Number of ticks simulated 5final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.212377 # Number of seconds simulated 4sim_ticks 212377413000 # Number of ticks simulated 5final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 166098 # Simulator instruction rate (inst/s) 8host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 129195965 # Simulator tick rate (ticks/s) 10host_mem_usage 326468 # Number of bytes of host memory used 11host_seconds 1643.84 # Real time elapsed on the host | 7host_inst_rate 164145 # Simulator instruction rate (inst/s) 8host_op_rate 197075 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 127677508 # Simulator tick rate (ticks/s) 10host_mem_usage 316656 # Number of bytes of host memory used 11host_seconds 1663.39 # Real time elapsed on the host |
| 12sim_insts 273037856 # Number of instructions simulated 13sim_ops 327812213 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory 17system.physmem.bytes_read::total 485312 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory --- 171 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation | 12sim_insts 273037856 # Number of instructions simulated 13sim_ops 327812213 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory 17system.physmem.bytes_read::total 485312 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory --- 171 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation |
| 199system.physmem.totQLat 52122500 # Total ticks spent queuing 200system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM | 199system.physmem.totQLat 52768250 # Total ticks spent queuing 200system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM |
| 201system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers | 201system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers |
| 202system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst | 202system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst |
| 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 204system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst | 204system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst |
| 205system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.02 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 28007013.85 # Average gap between requests 220system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states 222system.physmem.memoryStateTime::REF 7091500000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 205system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.02 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 28007013.85 # Average gap between requests 220system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states 222system.physmem.memoryStateTime::REF 7091500000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 226system.membus.throughput 2285139 # Throughput (bytes/s) | |
| 227system.membus.trans_dist::ReadReq 4730 # Transaction distribution 228system.membus.trans_dist::ReadResp 4730 # Transaction distribution 229system.membus.trans_dist::ReadExReq 2853 # Transaction distribution 230system.membus.trans_dist::ReadExResp 2853 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) | 226system.membus.trans_dist::ReadReq 4730 # Transaction distribution 227system.membus.trans_dist::ReadResp 4730 # Transaction distribution 228system.membus.trans_dist::ReadExReq 2853 # Transaction distribution 229system.membus.trans_dist::ReadExResp 2853 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) |
| 233system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) 234system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) 235system.membus.data_through_bus 485312 # Total data (bytes) 236system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 237system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) | 232system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) 233system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) 234system.membus.snoops 0 # Total snoops (count) 235system.membus.snoop_fanout::samples 7583 # Request fanout histogram 236system.membus.snoop_fanout::mean 0 # Request fanout histogram 237system.membus.snoop_fanout::stdev 0 # Request fanout histogram 238system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 239system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram 240system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 241system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 242system.membus.snoop_fanout::min_value 0 # Request fanout histogram 243system.membus.snoop_fanout::max_value 0 # Request fanout histogram 244system.membus.snoop_fanout::total 7583 # Request fanout histogram 245system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks) |
| 238system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 246system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 239system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) | 247system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks) |
| 240system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 241system.cpu_clk_domain.clock 500 # Clock period in ticks | 248system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 242system.cpu.branchPred.lookups 33146135 # Number of BP lookups | 250system.cpu.branchPred.lookups 33146132 # Number of BP lookups |
| 243system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted 244system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect | 251system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted 252system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect |
| 245system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups | 253system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups |
| 246system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits 247system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 254system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits 255system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 248system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage | 256system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage |
| 249system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. 250system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 251system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 252system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 253system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 254system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 255system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 256system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses --- 76 unchanged lines hidden (view full) --- 333system.cpu.itb.misses 0 # DTB misses 334system.cpu.itb.accesses 0 # DTB accesses 335system.cpu.workload.num_syscalls 191 # Number of system calls 336system.cpu.numCycles 424754826 # number of cpu cycles simulated 337system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 338system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 339system.cpu.committedInsts 273037856 # Number of instructions committed 340system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed | 257system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. 258system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 259system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 260system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 261system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 262system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 263system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 264system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses --- 76 unchanged lines hidden (view full) --- 341system.cpu.itb.misses 0 # DTB misses 342system.cpu.itb.accesses 0 # DTB accesses 343system.cpu.workload.num_syscalls 191 # Number of system calls 344system.cpu.numCycles 424754826 # number of cpu cycles simulated 345system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 347system.cpu.committedInsts 273037856 # Number of instructions committed 348system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed |
| 341system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit | 349system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit |
| 342system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 343system.cpu.cpi 1.555663 # CPI: cycles per instruction 344system.cpu.ipc 0.642813 # IPC: instructions per cycle | 350system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 351system.cpu.cpi 1.555663 # CPI: cycles per instruction 352system.cpu.ipc 0.642813 # IPC: instructions per cycle |
| 345system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked 346system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped | 353system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked 354system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped |
| 347system.cpu.icache.tags.replacements 36952 # number of replacements | 355system.cpu.icache.tags.replacements 36952 # number of replacements |
| 348system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use 349system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. | 356system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use 357system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks. |
| 350system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. | 358system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. |
| 351system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. | 359system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks. |
| 352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 353system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor | 361system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor |
| 354system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id 362system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id | 362system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id 369system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id 370system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id |
| 363system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses 364system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses 365system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits 366system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits 367system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits 368system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits 369system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits 370system.cpu.icache.overall_hits::total 73208047 # number of overall hits | 371system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses 372system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses 373system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits 374system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits 375system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits 376system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits 377system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits 378system.cpu.icache.overall_hits::total 73208046 # number of overall hits |
| 371system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses 372system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses 373system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses 374system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses 375system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses 376system.cpu.icache.overall_misses::total 38890 # number of overall misses | 379system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses 380system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses 381system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses 382system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses 383system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses 384system.cpu.icache.overall_misses::total 38890 # number of overall misses |
| 377system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles 378system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles 379system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles 380system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles 381system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles 382system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles 383system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses) 385system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses 386system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses 387system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses 388system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses | 385system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles 386system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles 387system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles 388system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles 389system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles 390system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles 391system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses) 392system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses) 393system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses 394system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses 395system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses 396system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses |
| 389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses 390system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses 391system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses 392system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses 393system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses 394system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses | 397system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses 398system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses 399system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses 400system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses 401system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses 402system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses |
| 395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency 396system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency 397system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency 398system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency | 403system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency 404system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency 405system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency 406system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency 407system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency 408system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency |
| 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.cpu.icache.fast_writes 0 # number of fast writes performed 408system.cpu.icache.cache_copies 0 # number of cache copies performed 409system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses 410system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses 411system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses 412system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses 413system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses 414system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses | 409system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu.icache.fast_writes 0 # number of fast writes performed 416system.cpu.icache.cache_copies 0 # number of cache copies performed 417system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses 418system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses 419system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses 420system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses 421system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses 422system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses |
| 415system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles 416system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles | 423system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles 424system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles 425system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles 426system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles 427system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles 428system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles |
| 421system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses 422system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses 423system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses 424system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses 425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses 426system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses | 429system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses 430system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses 431system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses 432system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses 433system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses 434system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses |
| 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency | 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency |
| 433system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 441system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 434system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s) | |
| 435system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution 438system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution 440system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) 441system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) | 442system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) |
| 443system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) 444system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) 445system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes) 447system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 450system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) 453system.cpu.toL2Bus.snoops 0 # Total snoops (count) 454system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 467system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram |
| 448system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) 449system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 469system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) 470system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 450system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks) | 471system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks) |
| 451system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 472system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 452system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks) | 473system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks) |
| 453system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 454system.cpu.l2cache.tags.replacements 0 # number of replacements | 474system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 475system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 455system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use | 476system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use |
| 456system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. 457system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. 458system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. 459system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 477system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. 478system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. 479system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. 480system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 460system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor 461system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor | 481system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor 482system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor |
| 462system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 484system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses 485system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses 486system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses 487system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses 488system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses 489system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses 490system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses 491system.cpu.l2cache.overall_misses::total 7626 # number of overall misses | 483system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy 484system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy 485system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy 486system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id 487system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 488system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 489system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 490system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 505system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses 506system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses 507system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses 508system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses 509system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses 510system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses 511system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses 512system.cpu.l2cache.overall_misses::total 7626 # number of overall misses |
| 492system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles 493system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles 494system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles 495system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles 496system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles 497system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles 498system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles 499system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles | 513system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles 514system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles 515system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles 516system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles 517system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles 518system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles 519system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles 520system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles |
| 500system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) 501system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) 502system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) 503system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses) 506system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses 507system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses 508system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses 509system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses 510system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses 511system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses 512system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses 513system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses 514system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses 515system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses 516system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses 517system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses | 521system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) 522system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) 523system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) 524system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses) 525system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses) 526system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses) 527system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses 529system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses 530system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses 531system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses 532system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses 533system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses 534system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses 535system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses 536system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses 537system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses 538system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses |
| 518system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency 519system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency 520system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency 521system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency 522system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency 523system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency 524system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency 525system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency | 539system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency 540system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency 541system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency 542system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency 543system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency 544system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency 545system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency 546system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency |
| 526system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 531system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 532system.cpu.l2cache.fast_writes 0 # number of fast writes performed 533system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 540system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses 541system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses 542system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses 543system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses 544system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses 545system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses 546system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses 547system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses | 547system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.l2cache.fast_writes 0 # number of fast writes performed 554system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 561system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses 562system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses 563system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses 564system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses 565system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses 566system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses 567system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses 568system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses |
| 548system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles 549system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles 550system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles 551system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles 552system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles 553system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles 554system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles 555system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles | 569system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles 570system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles 571system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles 572system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles 573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles 574system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles 575system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles 576system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles |
| 556system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses 558system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses 559system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses 560system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses 561system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses 562system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses 563system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses | 577system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses 578system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses 579system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses 580system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses 581system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses 582system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses 583system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses 584system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses |
| 564system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency 565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency 566system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency 567system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency 568system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency 569system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency 570system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency 571system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency | 585system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency 586system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency 587system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency 588system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency |
| 572system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.dcache.tags.replacements 1353 # number of replacements | 593system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 594system.cpu.dcache.tags.replacements 1353 # number of replacements |
| 574system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use | 595system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use |
| 575system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. 576system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. 577system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. 578system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 596system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. 597system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. 598system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. 599system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 579system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor | 600system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor |
| 580system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy 581system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 583system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id --- 15 unchanged lines hidden (view full) --- 603system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses 604system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses 605system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses 606system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses 607system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses 608system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses 609system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses 610system.cpu.dcache.overall_misses::total 7291 # number of overall misses | 601system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy 602system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy 603system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 604system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 606system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 607system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id 608system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id --- 15 unchanged lines hidden (view full) --- 624system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses 625system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses 626system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses 627system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses 628system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses 629system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses 630system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses 631system.cpu.dcache.overall_misses::total 7291 # number of overall misses |
| 611system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles 612system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles 613system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles 615system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles 616system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles 617system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles 618system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles | 632system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles 633system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles 634system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles 636system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles 637system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles 638system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles 639system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles |
| 619system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) 624system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 625system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) 626system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 631system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses 632system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 633system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses 634system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 635system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses 636system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 637system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses 638system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses | 640system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) 641system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) 645system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 646system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) 647system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 652system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses 653system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 654system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses 655system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 656system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses 657system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 658system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses 659system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses |
| 639system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency 640system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency 641system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency 642system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency 643system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency 644system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency 646system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency | 660system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency 661system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency 662system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency 663system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency 664system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency 665system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency 666system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency 667system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency |
| 647system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.dcache.fast_writes 0 # number of fast writes performed 654system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 665system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses 666system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses 669system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses 670system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses 671system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses 672system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses | 668system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu.dcache.fast_writes 0 # number of fast writes performed 675system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 686system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses 687system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses 688system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses 689system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses 690system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses 691system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses 692system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses 693system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses |
| 673system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles 674system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles 675system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles 676system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles 677system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles 678system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles 679system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles 680system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles | 694system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles 696system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles 697system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles 698system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles 699system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles 701system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles |
| 681system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 683system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 685system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 686system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 687system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 688system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses | 702system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses 703system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 704system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses 705system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 706system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 707system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 708system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 709system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency 690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency 692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency 694system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency | 710system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency 711system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency 712system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency 713system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency 715system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency 717system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency |
| 697system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 698 699---------- End Simulation Statistics ---------- | 718system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 719 720---------- End Simulation Statistics ---------- |