| stats.txt (10260:384d554cea8c) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 153700 # Simulator instruction rate (inst/s) 5host_mem_usage 303376 # Number of bytes of host memory used 6host_op_rate 196498 # Simulator op (including micro ops) rate (op/s) 7host_seconds 1776.44 # Real time elapsed on the host 8host_tick_rate 128034740 # Simulator tick rate (ticks/s) | 3sim_seconds 0.212377 # Number of seconds simulated 4sim_ticks 212377413000 # Number of ticks simulated 5final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 10sim_insts 273037854 # Number of instructions simulated 11sim_ops 349065592 # Number of ops (including micro ops) simulated 12sim_seconds 0.227446 # Number of seconds simulated 13sim_ticks 227445516000 # Number of ticks simulated | 7host_inst_rate 166098 # Simulator instruction rate (inst/s) 8host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 129195965 # Simulator tick rate (ticks/s) 10host_mem_usage 326468 # Number of bytes of host memory used 11host_seconds 1643.84 # Real time elapsed on the host 12sim_insts 273037856 # Number of instructions simulated 13sim_ops 327812213 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 14system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 35363260 # Number of BP lookups 23system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 273037854 # Number of instructions committed 25system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed 26system.cpu.cpi 1.666037 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits 30system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 31system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses) 32system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses) 33system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency 34system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency 35system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency 36system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency 37system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits 38system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits 39system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles 40system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles 41system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 42system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 43system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses 44system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses 45system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits 46system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits 47system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles 48system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles 49system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses 50system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses 51system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses 52system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses 53system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) 54system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 55system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits 56system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 57system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) 58system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 59system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency 60system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency 61system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency 62system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency 63system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits 64system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits 65system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles 66system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles 67system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses 70system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses 71system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits 72system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 77system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2860 # number of WriteReq MSHR misses 78system.cpu.dcache.WriteReq_mshr_misses::total 2860 # number of WriteReq MSHR misses 79system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.cpu.dcache.cache_copies 0 # number of cache copies performed 86system.cpu.dcache.demand_accesses::cpu.inst 177197787 # number of demand (read+write) accesses 87system.cpu.dcache.demand_accesses::total 177197787 # number of demand (read+write) accesses 88system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency 89system.cpu.dcache.demand_avg_miss_latency::total 66547.120044 # average overall miss latency 90system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency 91system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency 92system.cpu.dcache.demand_hits::cpu.inst 177190498 # number of demand (read+write) hits 93system.cpu.dcache.demand_hits::total 177190498 # number of demand (read+write) hits 94system.cpu.dcache.demand_miss_latency::cpu.inst 485061958 # number of demand (read+write) miss cycles 95system.cpu.dcache.demand_miss_latency::total 485061958 # number of demand (read+write) miss cycles 96system.cpu.dcache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses 97system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses 98system.cpu.dcache.demand_misses::cpu.inst 7289 # number of demand (read+write) misses 99system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses 100system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits 101system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles 104system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses 105system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses 106system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses 107system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses 108system.cpu.dcache.fast_writes 0 # number of fast writes performed 109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 110system.cpu.dcache.overall_accesses::cpu.inst 177197787 # number of overall (read+write) accesses 111system.cpu.dcache.overall_accesses::total 177197787 # number of overall (read+write) accesses 112system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency 113system.cpu.dcache.overall_avg_miss_latency::total 66547.120044 # average overall miss latency 114system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency 115system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency 116system.cpu.dcache.overall_hits::cpu.inst 177190498 # number of overall hits 117system.cpu.dcache.overall_hits::total 177190498 # number of overall hits 118system.cpu.dcache.overall_miss_latency::cpu.inst 485061958 # number of overall miss cycles 119system.cpu.dcache.overall_miss_latency::total 485061958 # number of overall miss cycles 120system.cpu.dcache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses 121system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses 122system.cpu.dcache.overall_misses::cpu.inst 7289 # number of overall misses 123system.cpu.dcache.overall_misses::total 7289 # number of overall misses 124system.cpu.dcache.overall_mshr_hits::cpu.inst 2768 # number of overall MSHR hits 125system.cpu.dcache.overall_mshr_hits::total 2768 # number of overall MSHR hits 126system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298702790 # number of overall MSHR miss cycles 127system.cpu.dcache.overall_mshr_miss_latency::total 298702790 # number of overall MSHR miss cycles 128system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses 129system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses 130system.cpu.dcache.overall_mshr_misses::cpu.inst 4521 # number of overall MSHR misses 131system.cpu.dcache.overall_mshr_misses::total 4521 # number of overall MSHR misses 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 135system.cpu.dcache.tags.age_task_id_blocks_1024::3 674 # Occupied blocks per task id 136system.cpu.dcache.tags.age_task_id_blocks_1024::4 2436 # Occupied blocks per task id 137system.cpu.dcache.tags.avg_refs 39197.586375 # Average number of references to valid blocks. 138system.cpu.dcache.tags.data_accesses 354443675 # Number of data accesses 139system.cpu.dcache.tags.occ_blocks::cpu.inst 3089.554835 # Average occupied blocks per requestor 140system.cpu.dcache.tags.occ_percent::cpu.inst 0.754286 # Average percentage of cache occupancy 141system.cpu.dcache.tags.occ_percent::total 0.754286 # Average percentage of cache occupancy 142system.cpu.dcache.tags.occ_task_id_blocks::1024 3161 # Occupied blocks per task id 143system.cpu.dcache.tags.occ_task_id_percent::1024 0.771729 # Percentage of cache occupancy per task id 144system.cpu.dcache.tags.replacements 1360 # number of replacements 145system.cpu.dcache.tags.sampled_refs 4521 # Sample count of references to valid blocks. 146system.cpu.dcache.tags.tag_accesses 354443675 # Number of tag accesses 147system.cpu.dcache.tags.tagsinuse 3089.554835 # Cycle average of tags in use 148system.cpu.dcache.tags.total_refs 177212288 # Total number of references to valid blocks. 149system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 150system.cpu.dcache.writebacks::writebacks 1013 # number of writebacks 151system.cpu.dcache.writebacks::total 1013 # number of writebacks 152system.cpu.discardedOps 6932970 # Number of ops (including micro ops) which were discarded before commit 153system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 154system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 155system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 157system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 158system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 159system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 160system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 161system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 162system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 163system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 164system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 165system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 166system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 167system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 168system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 169system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 170system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 171system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 172system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 173system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 174system.cpu.dtb.accesses 0 # DTB accesses 175system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 176system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 177system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 178system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 179system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 180system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 181system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 182system.cpu.dtb.hits 0 # DTB hits 183system.cpu.dtb.inst_accesses 0 # ITB inst accesses 184system.cpu.dtb.inst_hits 0 # ITB inst hits 185system.cpu.dtb.inst_misses 0 # ITB inst misses 186system.cpu.dtb.misses 0 # DTB misses 187system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 188system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 189system.cpu.dtb.read_accesses 0 # DTB read accesses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_accesses 0 # DTB write accesses 193system.cpu.dtb.write_hits 0 # DTB write hits 194system.cpu.dtb.write_misses 0 # DTB write misses 195system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses) 196system.cpu.icache.ReadReq_accesses::total 77471042 # number of ReadReq accesses(hits+misses) 197system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336 # average ReadReq miss latency 198system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336 # average ReadReq miss latency 199system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083 # average ReadReq mshr miss latency 200system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083 # average ReadReq mshr miss latency 201system.cpu.icache.ReadReq_hits::cpu.inst 77429612 # number of ReadReq hits 202system.cpu.icache.ReadReq_hits::total 77429612 # number of ReadReq hits 203system.cpu.icache.ReadReq_miss_latency::cpu.inst 739892998 # number of ReadReq miss cycles 204system.cpu.icache.ReadReq_miss_latency::total 739892998 # number of ReadReq miss cycles 205system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses 207system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses 208system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses 209system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles 210system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles 211system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses 212system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses 213system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses 214system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses 215system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 217system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 218system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 219system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 220system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 221system.cpu.icache.cache_copies 0 # number of cache copies performed 222system.cpu.icache.demand_accesses::cpu.inst 77471042 # number of demand (read+write) accesses 223system.cpu.icache.demand_accesses::total 77471042 # number of demand (read+write) accesses 224system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency 225system.cpu.icache.demand_avg_miss_latency::total 17858.870336 # average overall miss latency 226system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency 227system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency 228system.cpu.icache.demand_hits::cpu.inst 77429612 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits 230system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles 231system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles 232system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses 233system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses 234system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses 236system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles 237system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles 238system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses 239system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses 240system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses 241system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses 242system.cpu.icache.fast_writes 0 # number of fast writes performed 243system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 244system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses 245system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses 246system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency 247system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency 248system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency 249system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency 250system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits 251system.cpu.icache.overall_hits::total 77429612 # number of overall hits 252system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles 253system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses 256system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses 257system.cpu.icache.overall_misses::total 41430 # number of overall misses 258system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles 259system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles 260system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses 261system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses 262system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses 263system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses 264system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 265system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 266system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 267system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id 268system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id 269system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks. 270system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses 271system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor 272system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy 273system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy 274system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id 275system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id 276system.cpu.icache.tags.replacements 39488 # number of replacements 277system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks. 278system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses 279system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use 280system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks. 281system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 282system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling 283system.cpu.ipc 0.600227 # IPC: instructions per cycle 284system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 285system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 286system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 287system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 288system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 289system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 290system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 291system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 292system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 293system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 294system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 295system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 296system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 297system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 298system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 299system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 300system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 301system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 302system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 303system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 304system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 305system.cpu.itb.accesses 0 # DTB accesses 306system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 307system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 308system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 309system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 310system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 311system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.itb.hits 0 # DTB hits 314system.cpu.itb.inst_accesses 0 # ITB inst accesses 315system.cpu.itb.inst_hits 0 # ITB inst hits 316system.cpu.itb.inst_misses 0 # ITB inst misses 317system.cpu.itb.misses 0 # DTB misses 318system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 320system.cpu.itb.read_accesses 0 # DTB read accesses 321system.cpu.itb.read_hits 0 # DTB read hits 322system.cpu.itb.read_misses 0 # DTB read misses 323system.cpu.itb.write_accesses 0 # DTB write accesses 324system.cpu.itb.write_hits 0 # DTB write hits 325system.cpu.itb.write_misses 0 # DTB write misses 326system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses) 327system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses) 328system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency 329system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency 330system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency 331system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency 332system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits 333system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 334system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles 335system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles 336system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses 337system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses 338system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses 339system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses 340system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles 341system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles 342system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses 343system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses 344system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses 345system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses 346system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses) 347system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses) 348system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency 349system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency 350system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency 351system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency 352system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits 353system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits 354system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles 355system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles 356system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses 357system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses 358system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses 359system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses 360system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits 361system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits 362system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles 363system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles 364system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses 365system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses 366system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses 367system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses 368system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses) 369system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses) 370system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits 371system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits 372system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 373system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 374system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.l2cache.cache_copies 0 # number of cache copies performed 379system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses 380system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses 381system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency 382system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency 383system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency 384system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency 385system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits 386system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits 387system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles 388system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles 389system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses 390system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses 391system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses 392system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses 393system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits 394system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits 395system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses 398system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses 399system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses 400system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses 401system.cpu.l2cache.fast_writes 0 # number of fast writes performed 402system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 403system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses 404system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses 405system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency 406system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency 407system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency 408system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency 409system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits 410system.cpu.l2cache.overall_hits::total 38282 # number of overall hits 411system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles 412system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles 413system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses 414system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses 415system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses 416system.cpu.l2cache.overall_misses::total 7669 # number of overall misses 417system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits 418system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits 419system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles 420system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles 421system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses 422system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses 423system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses 424system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses 425system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id 427system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id 428system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id 429system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id 430system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks. 431system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses 432system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor 433system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor 434system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy 435system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy 436system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy 437system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id 438system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id 439system.cpu.l2cache.tags.replacements 0 # number of replacements 440system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks. 441system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses 442system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use 443system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks. 444system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 445system.cpu.numCycles 454891032 # number of cpu cycles simulated 446system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 447system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 448system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 449system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked 450system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes) 451system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes) 453system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes) 454system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks) 455system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 456system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks) 457system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 458system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks) 459system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 460system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 461system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s) 462system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes) 464system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes) 465system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution 470system.cpu.workload.num_syscalls 191 # Number of system calls 471system.cpu_clk_domain.clock 500 # Clock period in ticks 472system.membus.data_through_bus 488128 # Total data (bytes) 473system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes) 474system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes) 475system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks) 476system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 477system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks) 478system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 479system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 480system.membus.throughput 2146132 # Throughput (bytes/s) 481system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes) 482system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes) 483system.membus.trans_dist::ReadReq 4783 # Transaction distribution 484system.membus.trans_dist::ReadResp 4783 # Transaction distribution 485system.membus.trans_dist::ReadExReq 2844 # Transaction distribution 486system.membus.trans_dist::ReadExResp 2844 # Transaction distribution 487system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 488system.physmem.avgGap 29821084.57 # Average gap between requests 489system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst 490system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst 491system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s 492system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s 493system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 494system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 495system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 496system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 497system.physmem.busUtil 0.02 # Data bus utilization in percentage 498system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 499system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 500system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s) 501system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s) 502system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s) 503system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s) 504system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s) 505system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s) 506system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation 507system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation 508system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation 509system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation 510system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation 520system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM 521system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side | 16system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory 17system.physmem.bytes_read::total 485312 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.readReqs 7583 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 32system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM |
| 522system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 523system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 35system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side |
|
| 524system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side | 36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side |
| 525system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory 526system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory 527system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory 528system.physmem.bytes_read::total 488128 # Number of bytes read from this memory 529system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states 530system.physmem.memoryStateTime::REF 7594860000 # Time in different power states 531system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 532system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states 533system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue |
| 534system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 535system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 536system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 537system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 538system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory 539system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory 540system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined 541system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 542system.physmem.perBankRdBursts::0 637 # Per bank write bursts 543system.physmem.perBankRdBursts::1 850 # Per bank write bursts 544system.physmem.perBankRdBursts::2 633 # Per bank write bursts | 40system.physmem.perBankRdBursts::0 630 # Per bank write bursts 41system.physmem.perBankRdBursts::1 843 # Per bank write bursts 42system.physmem.perBankRdBursts::2 628 # Per bank write bursts |
| 545system.physmem.perBankRdBursts::3 541 # Per bank write bursts | 43system.physmem.perBankRdBursts::3 541 # Per bank write bursts |
| 546system.physmem.perBankRdBursts::4 470 # Per bank write bursts 547system.physmem.perBankRdBursts::5 350 # Per bank write bursts 548system.physmem.perBankRdBursts::6 175 # Per bank write bursts 549system.physmem.perBankRdBursts::7 229 # Per bank write bursts 550system.physmem.perBankRdBursts::8 210 # Per bank write bursts 551system.physmem.perBankRdBursts::9 309 # Per bank write bursts 552system.physmem.perBankRdBursts::10 346 # Per bank write bursts | 44system.physmem.perBankRdBursts::4 466 # Per bank write bursts 45system.physmem.perBankRdBursts::5 349 # Per bank write bursts 46system.physmem.perBankRdBursts::6 173 # Per bank write bursts 47system.physmem.perBankRdBursts::7 228 # Per bank write bursts 48system.physmem.perBankRdBursts::8 209 # Per bank write bursts 49system.physmem.perBankRdBursts::9 310 # Per bank write bursts 50system.physmem.perBankRdBursts::10 342 # Per bank write bursts |
| 553system.physmem.perBankRdBursts::11 428 # Per bank write bursts | 51system.physmem.perBankRdBursts::11 428 # Per bank write bursts |
| 554system.physmem.perBankRdBursts::12 552 # Per bank write bursts 555system.physmem.perBankRdBursts::13 714 # Per bank write bursts 556system.physmem.perBankRdBursts::14 639 # Per bank write bursts 557system.physmem.perBankRdBursts::15 544 # Per bank write bursts | 52system.physmem.perBankRdBursts::12 554 # Per bank write bursts 53system.physmem.perBankRdBursts::13 705 # Per bank write bursts 54system.physmem.perBankRdBursts::14 637 # Per bank write bursts 55system.physmem.perBankRdBursts::15 540 # Per bank write bursts |
| 558system.physmem.perBankWrBursts::0 0 # Per bank write bursts 559system.physmem.perBankWrBursts::1 0 # Per bank write bursts 560system.physmem.perBankWrBursts::2 0 # Per bank write bursts 561system.physmem.perBankWrBursts::3 0 # Per bank write bursts 562system.physmem.perBankWrBursts::4 0 # Per bank write bursts 563system.physmem.perBankWrBursts::5 0 # Per bank write bursts 564system.physmem.perBankWrBursts::6 0 # Per bank write bursts 565system.physmem.perBankWrBursts::7 0 # Per bank write bursts 566system.physmem.perBankWrBursts::8 0 # Per bank write bursts 567system.physmem.perBankWrBursts::9 0 # Per bank write bursts 568system.physmem.perBankWrBursts::10 0 # Per bank write bursts 569system.physmem.perBankWrBursts::11 0 # Per bank write bursts 570system.physmem.perBankWrBursts::12 0 # Per bank write bursts 571system.physmem.perBankWrBursts::13 0 # Per bank write bursts 572system.physmem.perBankWrBursts::14 0 # Per bank write bursts 573system.physmem.perBankWrBursts::15 0 # Per bank write bursts | 56system.physmem.perBankWrBursts::0 0 # Per bank write bursts 57system.physmem.perBankWrBursts::1 0 # Per bank write bursts 58system.physmem.perBankWrBursts::2 0 # Per bank write bursts 59system.physmem.perBankWrBursts::3 0 # Per bank write bursts 60system.physmem.perBankWrBursts::4 0 # Per bank write bursts 61system.physmem.perBankWrBursts::5 0 # Per bank write bursts 62system.physmem.perBankWrBursts::6 0 # Per bank write bursts 63system.physmem.perBankWrBursts::7 0 # Per bank write bursts 64system.physmem.perBankWrBursts::8 0 # Per bank write bursts 65system.physmem.perBankWrBursts::9 0 # Per bank write bursts 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts |
| 574system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see 575system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see 576system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see | 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 74system.physmem.totGap 212377186000 # Total gap between requests 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 7583 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) 89system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see |
| 577system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 578system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 579system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 580system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 581system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 582system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 583system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 584system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 598system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 599system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 600system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 601system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 602system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 603system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 604system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 605system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 606system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue 607system.physmem.readPktSize::0 0 # Read request sizes (log2) 608system.physmem.readPktSize::1 0 # Read request sizes (log2) 609system.physmem.readPktSize::2 0 # Read request sizes (log2) 610system.physmem.readPktSize::3 0 # Read request sizes (log2) 611system.physmem.readPktSize::4 0 # Read request sizes (log2) 612system.physmem.readPktSize::5 0 # Read request sizes (log2) 613system.physmem.readPktSize::6 7627 # Read request sizes (log2) 614system.physmem.readReqs 7627 # Number of read requests accepted 615system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads 616system.physmem.readRowHits 6079 # Number of row buffer hits during reads 617system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 618system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers 619system.physmem.totGap 227445412000 # Total gap between requests 620system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM 621system.physmem.totQLat 52095500 # Total ticks spent queuing | |
| 622system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 623system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 624system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 625system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 626system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 627system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 628system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 629system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 678system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 679system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 680system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 681system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 682system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 683system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 684system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 685system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 686system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 687system.physmem.writePktSize::0 0 # Write request sizes (log2) 688system.physmem.writePktSize::1 0 # Write request sizes (log2) 689system.physmem.writePktSize::2 0 # Write request sizes (log2) 690system.physmem.writePktSize::3 0 # Write request sizes (log2) 691system.physmem.writePktSize::4 0 # Write request sizes (log2) 692system.physmem.writePktSize::5 0 # Write request sizes (log2) 693system.physmem.writePktSize::6 0 # Write request sizes (log2) 694system.physmem.writeReqs 0 # Number of write requests accepted 695system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 185system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation 199system.physmem.totQLat 52122500 # Total ticks spent queuing 200system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM 201system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers 202system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 204system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.02 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 6077 # Number of row buffer hits during reads |
| 696system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 697system.voltage_domain.voltage 1 # Voltage in Volts | 217system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 28007013.85 # Average gap between requests 220system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states 222system.physmem.memoryStateTime::REF 7091500000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 226system.membus.throughput 2285139 # Throughput (bytes/s) 227system.membus.trans_dist::ReadReq 4730 # Transaction distribution 228system.membus.trans_dist::ReadResp 4730 # Transaction distribution 229system.membus.trans_dist::ReadExReq 2853 # Transaction distribution 230system.membus.trans_dist::ReadExResp 2853 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) 233system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) 234system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) 235system.membus.data_through_bus 485312 # Total data (bytes) 236system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 237system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) 238system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 239system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) 240system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 241system.cpu_clk_domain.clock 500 # Clock period in ticks 242system.cpu.branchPred.lookups 33146135 # Number of BP lookups 243system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted 244system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect 245system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups 246system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits 247system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 248system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage 249system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. 250system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 251system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 252system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 253system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 254system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 255system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 256system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 257system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 259system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 261system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 262system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 263system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 264system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 265system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 266system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 267system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 268system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 269system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 270system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 271system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 272system.cpu.dtb.inst_hits 0 # ITB inst hits 273system.cpu.dtb.inst_misses 0 # ITB inst misses 274system.cpu.dtb.read_hits 0 # DTB read hits 275system.cpu.dtb.read_misses 0 # DTB read misses 276system.cpu.dtb.write_hits 0 # DTB write hits 277system.cpu.dtb.write_misses 0 # DTB write misses 278system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 279system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 280system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 281system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 282system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 283system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 284system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 285system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 286system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 287system.cpu.dtb.read_accesses 0 # DTB read accesses 288system.cpu.dtb.write_accesses 0 # DTB write accesses 289system.cpu.dtb.inst_accesses 0 # ITB inst accesses 290system.cpu.dtb.hits 0 # DTB hits 291system.cpu.dtb.misses 0 # DTB misses 292system.cpu.dtb.accesses 0 # DTB accesses 293system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 294system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 295system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 296system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 297system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 298system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 299system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 300system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 301system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 302system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 303system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 304system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 305system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 306system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 308system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 309system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 310system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 311system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 312system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 313system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 314system.cpu.itb.inst_hits 0 # ITB inst hits 315system.cpu.itb.inst_misses 0 # ITB inst misses 316system.cpu.itb.read_hits 0 # DTB read hits 317system.cpu.itb.read_misses 0 # DTB read misses 318system.cpu.itb.write_hits 0 # DTB write hits 319system.cpu.itb.write_misses 0 # DTB write misses 320system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 321system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 322system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 323system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 324system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 325system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 326system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 327system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 329system.cpu.itb.read_accesses 0 # DTB read accesses 330system.cpu.itb.write_accesses 0 # DTB write accesses 331system.cpu.itb.inst_accesses 0 # ITB inst accesses 332system.cpu.itb.hits 0 # DTB hits 333system.cpu.itb.misses 0 # DTB misses 334system.cpu.itb.accesses 0 # DTB accesses 335system.cpu.workload.num_syscalls 191 # Number of system calls 336system.cpu.numCycles 424754826 # number of cpu cycles simulated 337system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 338system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 339system.cpu.committedInsts 273037856 # Number of instructions committed 340system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed 341system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit 342system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 343system.cpu.cpi 1.555663 # CPI: cycles per instruction 344system.cpu.ipc 0.642813 # IPC: instructions per cycle 345system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked 346system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped 347system.cpu.icache.tags.replacements 36952 # number of replacements 348system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use 349system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. 350system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. 351system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. 352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 353system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor 354system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id 362system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id 363system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses 364system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses 365system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits 366system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits 367system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits 368system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits 369system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits 370system.cpu.icache.overall_hits::total 73208047 # number of overall hits 371system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses 372system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses 373system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses 374system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses 375system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses 376system.cpu.icache.overall_misses::total 38890 # number of overall misses 377system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles 378system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles 379system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles 380system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles 381system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles 382system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles 383system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses) 385system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses 386system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses 387system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses 388system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses 389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses 390system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses 391system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses 392system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses 393system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses 394system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses 395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency 396system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency 397system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency 398system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.cpu.icache.fast_writes 0 # number of fast writes performed 408system.cpu.icache.cache_copies 0 # number of cache copies performed 409system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses 410system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses 411system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses 412system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses 413system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses 414system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses 415system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles 416system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles 421system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses 422system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses 423system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses 424system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses 425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses 426system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency 433system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 434system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s) 435system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution 438system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution 440system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) 441system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) 443system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) 444system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) 445system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes) 447system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 448system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) 449system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 450system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks) 451system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 452system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks) 453system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 454system.cpu.l2cache.tags.replacements 0 # number of replacements 455system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use 456system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. 457system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. 458system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. 459system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 460system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor 461system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor 462system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses 474system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits 475system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits 476system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits 477system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits 478system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits 479system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 480system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits 481system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits 482system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits 483system.cpu.l2cache.overall_hits::total 35774 # number of overall hits 484system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses 485system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses 486system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses 487system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses 488system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses 489system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses 490system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses 491system.cpu.l2cache.overall_misses::total 7626 # number of overall misses 492system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles 493system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles 494system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles 495system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles 496system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles 497system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles 498system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles 499system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles 500system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) 501system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) 502system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) 503system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses) 506system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses 507system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses 508system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses 509system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses 510system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses 511system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses 512system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses 513system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses 514system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses 515system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses 516system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses 517system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses 518system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency 519system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency 520system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency 521system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency 522system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency 523system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency 524system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency 525system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency 526system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 531system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 532system.cpu.l2cache.fast_writes 0 # number of fast writes performed 533system.cpu.l2cache.cache_copies 0 # number of cache copies performed 534system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits 535system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits 536system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits 537system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits 538system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits 539system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits 540system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses 541system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses 542system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses 543system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses 544system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses 545system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses 546system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses 547system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses 548system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles 549system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles 550system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles 551system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles 552system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles 553system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles 554system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles 555system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles 556system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses 558system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses 559system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses 560system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses 561system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses 562system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses 563system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses 564system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency 565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency 566system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency 567system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency 568system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency 569system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency 570system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency 571system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency 572system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.dcache.tags.replacements 1353 # number of replacements 574system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use 575system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. 576system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. 577system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. 578system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 579system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor 580system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy 581system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 583system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id 588system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id 589system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses 590system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses 591system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits 592system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits 593system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits 594system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits 595system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits 596system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 597system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits 598system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 599system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits 600system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits 601system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits 602system.cpu.dcache.overall_hits::total 168752750 # number of overall hits 603system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses 604system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses 605system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses 606system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses 607system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses 608system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses 609system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses 610system.cpu.dcache.overall_misses::total 7291 # number of overall misses 611system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles 612system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles 613system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles 615system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles 616system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles 617system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles 618system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles 619system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) 624system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 625system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) 626system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 627system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses 628system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses 629system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses 630system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses 631system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses 632system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 633system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses 634system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 635system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses 636system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 637system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses 638system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses 639system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency 640system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency 641system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency 642system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency 643system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency 644system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency 646system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency 647system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.dcache.fast_writes 0 # number of fast writes performed 654system.cpu.dcache.cache_copies 0 # number of cache copies performed 655system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks 656system.cpu.dcache.writebacks::total 1009 # number of writebacks 657system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits 658system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits 659system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits 660system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits 661system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits 662system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits 663system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits 664system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits 665system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses 666system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses 669system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses 670system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses 671system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses 672system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses 673system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles 674system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles 675system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles 676system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles 677system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles 678system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles 679system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles 680system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles 681system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 683system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 685system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 686system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 687system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 688system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency 690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency 692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency 694system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency 697system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 698 699---------- End Simulation Statistics ---------- | 698 699---------- End Simulation Statistics ---------- |