1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.225207 # Number of seconds simulated 4sim_ticks 225206521000 # Number of ticks simulated 5final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 289736 # Simulator instruction rate (inst/s) 8host_op_rate 347860 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 238979319 # Simulator tick rate (ticks/s) 10host_mem_usage 279872 # Number of bytes of host memory used 11host_seconds 942.37 # Real time elapsed on the host |
12sim_insts 273037855 # Number of instructions simulated 13sim_ops 327812212 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory 19system.physmem.bytes_read::total 485568 # Number of bytes read from this memory --- 176 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation |
204system.physmem.totQLat 232471000 # Total ticks spent queuing 205system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM |
206system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers |
207system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst |
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
209system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst |
210system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.02 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 29683177.41 # Average gap between requests 225system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) |
231system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ) |
232system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) |
233system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ) |
235system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) |
236system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ) 237system.physmem_0.averagePower 244.071435 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank |
239system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states |
242system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states |
244system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states 245system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) |
250system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ) |
251system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) |
252system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ) |
253system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) 256system.physmem_1.averagePower 245.505361 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states --- 180 unchanged lines hidden (view full) --- 441system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 442system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction 443system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction 444system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction 445system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction 446system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 447system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::total 327812212 # Class of committed instruction |
449system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked 450system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped |
451system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states 452system.cpu.dcache.tags.replacements 1355 # number of replacements |
453system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use |
454system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
458system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor |
459system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy 461system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 464system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 465system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 466system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id --- 118 unchanged lines hidden (view full) --- 585system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency 586system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency 587system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency 588system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency 589system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency 590system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency 591system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states 592system.cpu.icache.tags.replacements 38188 # number of replacements |
593system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use |
594system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. 595system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. 596system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. 597system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
598system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor |
599system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy 600system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy 601system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 603system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 604system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 605system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id 606system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id --- 8 unchanged lines hidden (view full) --- 615system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits 616system.cpu.icache.overall_hits::total 69819801 # number of overall hits 617system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses 618system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses 619system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses 620system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses 621system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses 622system.cpu.icache.overall_misses::total 40126 # number of overall misses |
623system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles 624system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles 625system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles 626system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles 627system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles 628system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles |
629system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) 630system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) 631system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses 632system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses 633system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses 634system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses 635system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses 636system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses 637system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses 638system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses 639system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses 640system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses |
641system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency 642system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency 643system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency 644system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency 645system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency 646system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency |
647system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.icache.writebacks::writebacks 38188 # number of writebacks 654system.cpu.icache.writebacks::total 38188 # number of writebacks 655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses 656system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses 657system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses 658system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses 659system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses 660system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses |
661system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles 663system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles |
667system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses 668system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses 669system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses 670system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses 671system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses 672system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses |
673system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency |
679system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states 680system.cpu.l2cache.tags.replacements 0 # number of replacements |
681system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use |
682system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
686system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor |
688system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy 689system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id --- 27 unchanged lines hidden (view full) --- 723system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses 724system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses 725system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses 726system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses 727system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses 728system.cpu.l2cache.overall_misses::total 7630 # number of overall misses 729system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles 730system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles |
731system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles 732system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles |
733system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles 734system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles |
735system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles |
736system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles |
737system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles 738system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles |
739system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles |
740system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles |
741system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) 742system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) 743system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) 744system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses) 745system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) 746system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) 747system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40126 # number of ReadCleanReq accesses(hits+misses) 748system.cpu.l2cache.ReadCleanReq_accesses::total 40126 # number of ReadCleanReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 763system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses 764system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::total 0.170931 # miss rate for demand accesses 766system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses 767system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses 769system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency 770system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency |
771system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency 772system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency |
773system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency 774system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency |
775system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency |
776system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency |
777system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency |
779system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency |
780system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency |
781system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 788system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits --- 14 unchanged lines hidden (view full) --- 803system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses 804system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses 805system.cpu.l2cache.demand_mshr_misses::total 7587 # number of demand (read+write) MSHR misses 806system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses 807system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses 808system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses 809system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles 810system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles |
811system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles 812system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles |
813system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles 814system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles |
815system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles |
816system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles |
817system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles 818system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles |
819system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles |
820system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles |
821system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses 822system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses 823system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses 824system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses 825system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses 826system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses 827system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses 828system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses 829system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses 830system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses 831system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses 832system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses 833system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency 834system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency |
835system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency 836system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency |
837system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency 838system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency |
839system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency |
840system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency |
841system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency 842system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency |
843system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency |
844system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency |
845system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. 846system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. 847system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 848system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 849system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 850system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 851system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states 852system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution --- 51 unchanged lines hidden (view full) --- 904system.membus.snoop_fanout::stdev 0 # Request fanout histogram 905system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 906system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram 907system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 908system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 909system.membus.snoop_fanout::min_value 0 # Request fanout histogram 910system.membus.snoop_fanout::max_value 0 # Request fanout histogram 911system.membus.snoop_fanout::total 7587 # Request fanout histogram |
912system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks) |
913system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 914system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) 915system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 916 917---------- End Simulation Statistics ---------- |