1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.211715 # Number of seconds simulated 4sim_ticks 211714953000 # Number of ticks simulated 5final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 196459 # Simulator instruction rate (inst/s) 8host_op_rate 235871 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152335465 # Simulator tick rate (ticks/s) 10host_mem_usage 280176 # Number of bytes of host memory used 11host_seconds 1389.79 # Real time elapsed on the host |
12sim_insts 273037857 # Number of instructions simulated 13sim_ops 327812214 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory 18system.physmem.bytes_read::total 485504 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory --- 490 unchanged lines hidden (view full) --- 510system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency 512system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
518system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks 519system.cpu.dcache.writebacks::total 1010 # number of writebacks 520system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits 521system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits 522system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits 523system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits 524system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits 525system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 560system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency 561system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency 562system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency 563system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency 564system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency 565system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency 566system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency 567system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency |
568system.cpu.icache.tags.replacements 38168 # number of replacements 569system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use 570system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks. 571system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks. 572system.cpu.icache.tags.avg_refs 1736.520946 # Average number of references to valid blocks. 573system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 574system.cpu.icache.tags.occ_blocks::cpu.inst 1923.744161 # Average occupied blocks per requestor 575system.cpu.icache.tags.occ_percent::cpu.inst 0.939328 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 620system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency 621system.cpu.icache.overall_avg_miss_latency::total 18888.617379 # average overall miss latency 622system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 623system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 625system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 627system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
628system.cpu.icache.writebacks::writebacks 38168 # number of writebacks 629system.cpu.icache.writebacks::total 38168 # number of writebacks 630system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40105 # number of ReadReq MSHR misses 631system.cpu.icache.ReadReq_mshr_misses::total 40105 # number of ReadReq MSHR misses 632system.cpu.icache.demand_mshr_misses::cpu.inst 40105 # number of demand (read+write) MSHR misses 633system.cpu.icache.demand_mshr_misses::total 40105 # number of demand (read+write) MSHR misses 634system.cpu.icache.overall_mshr_misses::cpu.inst 40105 # number of overall MSHR misses 635system.cpu.icache.overall_mshr_misses::total 40105 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 646system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for overall accesses 647system.cpu.icache.overall_mshr_miss_rate::total 0.000576 # mshr miss rate for overall accesses 648system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17888.642314 # average ReadReq mshr miss latency 649system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314 # average ReadReq mshr miss latency 650system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency 651system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency 652system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency 653system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency |
654system.cpu.l2cache.tags.replacements 0 # number of replacements 655system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use 656system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks. 657system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks. 658system.cpu.l2cache.tags.avg_refs 10.716891 # Average number of references to valid blocks. 659system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 660system.cpu.l2cache.tags.occ_blocks::writebacks 353.800339 # Average occupied blocks per requestor 661system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.579629 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 754system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency 755system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801 # average overall miss latency 756system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 758system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 760system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
762system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 763system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 764system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 42 # number of ReadSharedReq MSHR hits 765system.cpu.l2cache.ReadSharedReq_mshr_hits::total 42 # number of ReadSharedReq MSHR hits 766system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 767system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits 768system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits 769system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits --- 42 unchanged lines hidden (view full) --- 812system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency 813system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency 814system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency 817system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency |
820system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter. 821system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data. 822system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 823system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 824system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 825system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 826system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution --- 55 unchanged lines hidden --- |