1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 0.216828 # Number of seconds simulated 4sim_ticks 216828260500 # Number of ticks simulated 5final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 172164 # Simulator instruction rate (inst/s) 8host_op_rate 206702 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 136721287 # Simulator tick rate (ticks/s) 10host_mem_usage 262128 # Number of bytes of host memory used 11host_seconds 1585.91 # Real time elapsed on the host |
12sim_insts 273037856 # Number of instructions simulated 13sim_ops 327812213 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.bytes_read::cpu.inst 485440 # Number of bytes read from this memory 17system.physmem.bytes_read::total 485440 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 7585 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2238823 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 2238823 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.readReqs 7585 # Number of read requests accepted |
29system.physmem.writeReqs 0 # Number of write requests accepted |
30system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue |
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
32system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM |
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
35system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side |
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 40system.physmem.perBankRdBursts::0 630 # Per bank write bursts 41system.physmem.perBankRdBursts::1 843 # Per bank write bursts 42system.physmem.perBankRdBursts::2 628 # Per bank write bursts 43system.physmem.perBankRdBursts::3 541 # Per bank write bursts 44system.physmem.perBankRdBursts::4 466 # Per bank write bursts 45system.physmem.perBankRdBursts::5 349 # Per bank write bursts |
46system.physmem.perBankRdBursts::6 172 # Per bank write bursts |
47system.physmem.perBankRdBursts::7 228 # Per bank write bursts 48system.physmem.perBankRdBursts::8 209 # Per bank write bursts |
49system.physmem.perBankRdBursts::9 311 # Per bank write bursts |
50system.physmem.perBankRdBursts::10 342 # Per bank write bursts 51system.physmem.perBankRdBursts::11 428 # Per bank write bursts 52system.physmem.perBankRdBursts::12 554 # Per bank write bursts |
53system.physmem.perBankRdBursts::13 706 # Per bank write bursts |
54system.physmem.perBankRdBursts::14 637 # Per bank write bursts |
55system.physmem.perBankRdBursts::15 541 # Per bank write bursts |
56system.physmem.perBankWrBursts::0 0 # Per bank write bursts 57system.physmem.perBankWrBursts::1 0 # Per bank write bursts 58system.physmem.perBankWrBursts::2 0 # Per bank write bursts 59system.physmem.perBankWrBursts::3 0 # Per bank write bursts 60system.physmem.perBankWrBursts::4 0 # Per bank write bursts 61system.physmem.perBankWrBursts::5 0 # Per bank write bursts 62system.physmem.perBankWrBursts::6 0 # Per bank write bursts 63system.physmem.perBankWrBursts::7 0 # Per bank write bursts 64system.physmem.perBankWrBursts::8 0 # Per bank write bursts 65system.physmem.perBankWrBursts::9 0 # Per bank write bursts 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
74system.physmem.totGap 216828031000 # Total gap between requests |
75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) |
81system.physmem.readPktSize::6 7585 # Read request sizes (log2) |
82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) |
89system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see |
91system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
185system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 189.317321 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 333.826076 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 548 36.41% 36.41% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 349 23.19% 59.60% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 163 10.83% 70.43% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 69 4.58% 79.53% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 60 3.99% 83.52% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 33 2.19% 85.71% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation 199system.physmem.totQLat 50683250 # Total ticks spent queuing 200system.physmem.totMemAccLat 192902000 # Total ticks spent from burst creation until serviced by the DRAM 201system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers 202system.physmem.avgQLat 6682.04 # Average queueing delay per DRAM burst |
203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
204system.physmem.avgMemAccLat 25432.04 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s |
206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
207system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s |
208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.02 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
215system.physmem.readRowHits 6073 # Number of row buffer hits during reads |
216system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
217system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads |
218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
219system.physmem.avgGap 28586424.65 # Average gap between requests 220system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 207228229000 # Time in different power states 222system.physmem.memoryStateTime::REF 7240220000 # Time in different power states |
223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
224system.physmem.memoryStateTime::ACT 2356912000 # Time in different power states |
225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
226system.physmem.actEnergy::0 5012280 # Energy for activate commands per rank (pJ) 227system.physmem.actEnergy::1 6342840 # Energy for activate commands per rank (pJ) 228system.physmem.preEnergy::0 2734875 # Energy for precharge commands per rank (pJ) 229system.physmem.preEnergy::1 3460875 # Energy for precharge commands per rank (pJ) 230system.physmem.readEnergy::0 29905200 # Energy for read commands per rank (pJ) 231system.physmem.readEnergy::1 29000400 # Energy for read commands per rank (pJ) |
232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) |
234system.physmem.refreshEnergy::0 14161870320 # Energy for refresh commands per rank (pJ) 235system.physmem.refreshEnergy::1 14161870320 # Energy for refresh commands per rank (pJ) 236system.physmem.actBackEnergy::0 5651949285 # Energy for active background per rank (pJ) 237system.physmem.actBackEnergy::1 5745162240 # Energy for active background per rank (pJ) 238system.physmem.preBackEnergy::0 125136528000 # Energy for precharge background per rank (pJ) 239system.physmem.preBackEnergy::1 125054762250 # Energy for precharge background per rank (pJ) 240system.physmem.totalEnergy::0 144987999960 # Total energy per rank (pJ) 241system.physmem.totalEnergy::1 145000598925 # Total energy per rank (pJ) 242system.physmem.averagePower::0 668.689925 # Core power per rank (mW) 243system.physmem.averagePower::1 668.748031 # Core power per rank (mW) 244system.cpu.branchPred.lookups 33221230 # Number of BP lookups 245system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted 246system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect 247system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits |
249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
250system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage 251system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. |
252system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. |
253system.cpu_clk_domain.clock 500 # Clock period in ticks |
254system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 255system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 256system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 257system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 258system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 259system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 331system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 332system.cpu.itb.read_accesses 0 # DTB read accesses 333system.cpu.itb.write_accesses 0 # DTB write accesses 334system.cpu.itb.inst_accesses 0 # ITB inst accesses 335system.cpu.itb.hits 0 # DTB hits 336system.cpu.itb.misses 0 # DTB misses 337system.cpu.itb.accesses 0 # DTB accesses 338system.cpu.workload.num_syscalls 191 # Number of system calls |
339system.cpu.numCycles 433656521 # number of cpu cycles simulated |
340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 342system.cpu.committedInsts 273037856 # Number of instructions committed 343system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed |
344system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit |
345system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
346system.cpu.cpi 1.588265 # CPI: cycles per instruction 347system.cpu.ipc 0.629618 # IPC: instructions per cycle 348system.cpu.tickCycles 430211091 # Number of cycles that the object actually ticked 349system.cpu.idleCycles 3445430 # Total number of cycles that the object has spent stopped 350system.cpu.dcache.tags.replacements 1354 # number of replacements 351system.cpu.dcache.tags.tagsinuse 3086.009332 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. 353system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. 354system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. |
355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
356system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009332 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy |
359system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id |
360system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id |
362system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id |
363system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id 364system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id |
365system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id |
366system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses 367system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses 368system.cpu.dcache.ReadReq_hits::cpu.inst 86714567 # number of ReadReq hits 369system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits 370system.cpu.dcache.WriteReq_hits::cpu.inst 82047450 # number of WriteReq hits 371system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits |
372system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits 373system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 374system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits 375system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
376system.cpu.dcache.demand_hits::cpu.inst 168762017 # number of demand (read+write) hits 377system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits 378system.cpu.dcache.overall_hits::cpu.inst 168762017 # number of overall hits 379system.cpu.dcache.overall_hits::total 168762017 # number of overall hits 380system.cpu.dcache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses 381system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses 382system.cpu.dcache.WriteReq_misses::cpu.inst 5227 # number of WriteReq misses 383system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses 384system.cpu.dcache.demand_misses::cpu.inst 7290 # number of demand (read+write) misses 385system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses 386system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses 387system.cpu.dcache.overall_misses::total 7290 # number of overall misses 388system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126122956 # number of ReadReq miss cycles 389system.cpu.dcache.ReadReq_miss_latency::total 126122956 # number of ReadReq miss cycles 390system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360338500 # number of WriteReq miss cycles 391system.cpu.dcache.WriteReq_miss_latency::total 360338500 # number of WriteReq miss cycles 392system.cpu.dcache.demand_miss_latency::cpu.inst 486461456 # number of demand (read+write) miss cycles 393system.cpu.dcache.demand_miss_latency::total 486461456 # number of demand (read+write) miss cycles 394system.cpu.dcache.overall_miss_latency::cpu.inst 486461456 # number of overall miss cycles 395system.cpu.dcache.overall_miss_latency::total 486461456 # number of overall miss cycles 396system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses) 397system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) |
398system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) 401system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 402system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) 403system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
404system.cpu.dcache.demand_accesses::cpu.inst 168769307 # number of demand (read+write) accesses 405system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses 406system.cpu.dcache.overall_accesses::cpu.inst 168769307 # number of overall (read+write) accesses 407system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses |
408system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses 409system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 410system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses 411system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 412system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses 413system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 414system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses 415system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses |
416system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345 # average ReadReq miss latency 417system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345 # average ReadReq miss latency 418system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500 # average WriteReq miss latency 419system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500 # average WriteReq miss latency 420system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency 421system.cpu.dcache.demand_avg_miss_latency::total 66729.966529 # average overall miss latency 422system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency 423system.cpu.dcache.overall_avg_miss_latency::total 66729.966529 # average overall miss latency |
424system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 430system.cpu.dcache.fast_writes 0 # number of fast writes performed 431system.cpu.dcache.cache_copies 0 # number of cache copies performed |
432system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks 433system.cpu.dcache.writebacks::total 1010 # number of writebacks 434system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 422 # number of ReadReq MSHR hits 435system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits |
436system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits 437system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits |
438system.cpu.dcache.demand_mshr_hits::cpu.inst 2779 # number of demand (read+write) MSHR hits 439system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits 440system.cpu.dcache.overall_mshr_hits::cpu.inst 2779 # number of overall MSHR hits 441system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits |
442system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses 443system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses |
444system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2870 # number of WriteReq MSHR misses 445system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses 446system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 # number of demand (read+write) MSHR misses 447system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses 448system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses 449system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses 450system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 99847542 # number of ReadReq MSHR miss cycles 451system.cpu.dcache.ReadReq_mshr_miss_latency::total 99847542 # number of ReadReq MSHR miss cycles 452system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197786250 # number of WriteReq MSHR miss cycles 453system.cpu.dcache.WriteReq_mshr_miss_latency::total 197786250 # number of WriteReq MSHR miss cycles 454system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297633792 # number of demand (read+write) MSHR miss cycles 455system.cpu.dcache.demand_mshr_miss_latency::total 297633792 # number of demand (read+write) MSHR miss cycles 456system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297633792 # number of overall MSHR miss cycles 457system.cpu.dcache.overall_mshr_miss_latency::total 297633792 # number of overall MSHR miss cycles |
458system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses 459system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 460system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses 461system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 462system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 463system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 464system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 465system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
466system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618 # average ReadReq mshr miss latency 467system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618 # average ReadReq mshr miss latency 468system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686 # average WriteReq mshr miss latency 469system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686 # average WriteReq mshr miss latency 470system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency 471system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency 472system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency 473system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency |
474system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
475system.cpu.icache.tags.replacements 36927 # number of replacements 476system.cpu.icache.tags.tagsinuse 1924.993605 # Cycle average of tags in use 477system.cpu.icache.tags.total_refs 73270396 # Total number of references to valid blocks. 478system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. 479system.cpu.icache.tags.avg_refs 1885.302491 # Average number of references to valid blocks. 480system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 481system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993605 # Average occupied blocks per requestor 482system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy 483system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy 484system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id 485system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 486system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id 487system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id 488system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id 489system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id 490system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id 491system.cpu.icache.tags.tag_accesses 146657386 # Number of tag accesses 492system.cpu.icache.tags.data_accesses 146657386 # Number of data accesses 493system.cpu.icache.ReadReq_hits::cpu.inst 73270396 # number of ReadReq hits 494system.cpu.icache.ReadReq_hits::total 73270396 # number of ReadReq hits 495system.cpu.icache.demand_hits::cpu.inst 73270396 # number of demand (read+write) hits 496system.cpu.icache.demand_hits::total 73270396 # number of demand (read+write) hits 497system.cpu.icache.overall_hits::cpu.inst 73270396 # number of overall hits 498system.cpu.icache.overall_hits::total 73270396 # number of overall hits 499system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses 500system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses 501system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses 502system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses 503system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses 504system.cpu.icache.overall_misses::total 38865 # number of overall misses 505system.cpu.icache.ReadReq_miss_latency::cpu.inst 703294747 # number of ReadReq miss cycles 506system.cpu.icache.ReadReq_miss_latency::total 703294747 # number of ReadReq miss cycles 507system.cpu.icache.demand_miss_latency::cpu.inst 703294747 # number of demand (read+write) miss cycles 508system.cpu.icache.demand_miss_latency::total 703294747 # number of demand (read+write) miss cycles 509system.cpu.icache.overall_miss_latency::cpu.inst 703294747 # number of overall miss cycles 510system.cpu.icache.overall_miss_latency::total 703294747 # number of overall miss cycles 511system.cpu.icache.ReadReq_accesses::cpu.inst 73309261 # number of ReadReq accesses(hits+misses) 512system.cpu.icache.ReadReq_accesses::total 73309261 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.demand_accesses::cpu.inst 73309261 # number of demand (read+write) accesses 514system.cpu.icache.demand_accesses::total 73309261 # number of demand (read+write) accesses 515system.cpu.icache.overall_accesses::cpu.inst 73309261 # number of overall (read+write) accesses 516system.cpu.icache.overall_accesses::total 73309261 # number of overall (read+write) accesses 517system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses 518system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses 519system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses 520system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses 521system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses 522system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses 523system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081 # average ReadReq miss latency 524system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081 # average ReadReq miss latency 525system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency 526system.cpu.icache.demand_avg_miss_latency::total 18095.838081 # average overall miss latency 527system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::total 18095.838081 # average overall miss latency 529system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 530system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 531system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 533system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 534system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 535system.cpu.icache.fast_writes 0 # number of fast writes performed 536system.cpu.icache.cache_copies 0 # number of cache copies performed 537system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses 538system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses 539system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses 540system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses 541system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses 542system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses 543system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624165253 # number of ReadReq MSHR miss cycles 544system.cpu.icache.ReadReq_mshr_miss_latency::total 624165253 # number of ReadReq MSHR miss cycles 545system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624165253 # number of demand (read+write) MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::total 624165253 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624165253 # number of overall MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::total 624165253 # number of overall MSHR miss cycles 549system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses 550system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses 551system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses 552system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses 553system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses 554system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses 555system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972 # average ReadReq mshr miss latency 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972 # average ReadReq mshr miss latency 557system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency 559system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency 561system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 562system.cpu.l2cache.tags.replacements 0 # number of replacements 563system.cpu.l2cache.tags.tagsinuse 4198.559652 # Cycle average of tags in use 564system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks. 565system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. 566system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. 567system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 568system.cpu.l2cache.tags.occ_blocks::writebacks 353.760812 # Average occupied blocks per requestor 569system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798840 # Average occupied blocks per requestor 570system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy 571system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy 572system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy 573system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id 574system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 575system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 576system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 577system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id 578system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id 579system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id 580system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses 581system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses 582system.cpu.l2cache.ReadReq_hits::cpu.inst 35730 # number of ReadReq hits 583system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits 584system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits 585system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits 586system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits 587system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 588system.cpu.l2cache.demand_hits::cpu.inst 35746 # number of demand (read+write) hits 589system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits 590system.cpu.l2cache.overall_hits::cpu.inst 35746 # number of overall hits 591system.cpu.l2cache.overall_hits::total 35746 # number of overall hits 592system.cpu.l2cache.ReadReq_misses::cpu.inst 4776 # number of ReadReq misses 593system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses 594system.cpu.l2cache.ReadExReq_misses::cpu.inst 2854 # number of ReadExReq misses 595system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses 596system.cpu.l2cache.demand_misses::cpu.inst 7630 # number of demand (read+write) misses 597system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses 598system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses 599system.cpu.l2cache.overall_misses::total 7630 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326194750 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::total 326194750 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194720750 # number of ReadExReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::total 194720750 # number of ReadExReq miss cycles 604system.cpu.l2cache.demand_miss_latency::cpu.inst 520915500 # number of demand (read+write) miss cycles 605system.cpu.l2cache.demand_miss_latency::total 520915500 # number of demand (read+write) miss cycles 606system.cpu.l2cache.overall_miss_latency::cpu.inst 520915500 # number of overall miss cycles 607system.cpu.l2cache.overall_miss_latency::total 520915500 # number of overall miss cycles 608system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses) 609system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) 610system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) 611system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) 612system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2870 # number of ReadExReq accesses(hits+misses) 613system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) 614system.cpu.l2cache.demand_accesses::cpu.inst 43376 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses 616system.cpu.l2cache.overall_accesses::cpu.inst 43376 # number of overall (read+write) accesses 617system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses 618system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117908 # miss rate for ReadReq accesses 619system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses 620system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994425 # miss rate for ReadExReq accesses 621system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses 622system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 # miss rate for demand accesses 623system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses 624system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses 625system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses 626system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250 # average ReadReq miss latency 627system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250 # average ReadReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544 # average ReadExReq miss latency 629system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544 # average ReadExReq miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349 # average overall miss latency 632system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349 # average overall miss latency 634system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 635system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 636system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 638system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 639system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.cpu.l2cache.fast_writes 0 # number of fast writes performed 641system.cpu.l2cache.cache_copies 0 # number of cache copies performed 642system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 45 # number of ReadReq MSHR hits 643system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits 644system.cpu.l2cache.demand_mshr_hits::cpu.inst 45 # number of demand (read+write) MSHR hits 645system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits 646system.cpu.l2cache.overall_mshr_hits::cpu.inst 45 # number of overall MSHR hits 647system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits 648system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4731 # number of ReadReq MSHR misses 649system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses 650system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2854 # number of ReadExReq MSHR misses 651system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses 655system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses 656system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264387500 # number of ReadReq MSHR miss cycles 657system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264387500 # number of ReadReq MSHR miss cycles 658system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158755250 # number of ReadExReq MSHR miss cycles 659system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158755250 # number of ReadExReq MSHR miss cycles 660system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423142750 # number of demand (read+write) MSHR miss cycles 661system.cpu.l2cache.demand_mshr_miss_latency::total 423142750 # number of demand (read+write) MSHR miss cycles 662system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423142750 # number of overall MSHR miss cycles 663system.cpu.l2cache.overall_mshr_miss_latency::total 423142750 # number of overall MSHR miss cycles 664system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses 665system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses 666system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses 667system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses 668system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for demand accesses 669system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses 670system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses 671system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses 672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566 # average ReadReq mshr miss latency 673system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566 # average ReadReq mshr miss latency 674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578 # average ReadExReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578 # average ReadExReq mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency 678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency 680system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 681system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution 682system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution 683system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution 684system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution 685system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution 686system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes) 687system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) 688system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes) 689system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes) 690system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) 691system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes) 692system.cpu.toL2Bus.snoops 0 # Total snoops (count) 693system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram 694system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 695system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 696system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 697system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 698system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 699system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 700system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 701system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 702system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram 703system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 704system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 705system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 706system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 707system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram 708system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks) 709system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 710system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) 711system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 712system.cpu.toL2Bus.respLayer1.occupancy 7500208 # Layer occupancy (ticks) 713system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 714system.membus.trans_dist::ReadReq 4731 # Transaction distribution 715system.membus.trans_dist::ReadResp 4731 # Transaction distribution 716system.membus.trans_dist::ReadExReq 2854 # Transaction distribution 717system.membus.trans_dist::ReadExResp 2854 # Transaction distribution 718system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) 719system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) 720system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) 721system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) 722system.membus.snoops 0 # Total snoops (count) 723system.membus.snoop_fanout::samples 7585 # Request fanout histogram 724system.membus.snoop_fanout::mean 0 # Request fanout histogram 725system.membus.snoop_fanout::stdev 0 # Request fanout histogram 726system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 727system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram 728system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 729system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 730system.membus.snoop_fanout::min_value 0 # Request fanout histogram 731system.membus.snoop_fanout::max_value 0 # Request fanout histogram 732system.membus.snoop_fanout::total 7585 # Request fanout histogram 733system.membus.reqLayer0.occupancy 8963500 # Layer occupancy (ticks) 734system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 735system.membus.respLayer1.occupancy 71030250 # Layer occupancy (ticks) 736system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
737 738---------- End Simulation Statistics ---------- |