Cross Reference: /gem5/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11754:c209cb86278a ) new ( 11860:67dee11badea )

full compact

3,5c3,5
< sim_seconds 0.225207 # Number of seconds simulated
< sim_ticks 225206521000 # Number of ticks simulated
< final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.225185 # Number of seconds simulated
> sim_ticks 225184887000 # Number of ticks simulated
> final_tick 225184887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 289736 # Simulator instruction rate (inst/s)
< host_op_rate 347860 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 238979319 # Simulator tick rate (ticks/s)
< host_mem_usage 279872 # Number of bytes of host memory used
< host_seconds 942.37 # Real time elapsed on the host
---
> host_inst_rate 292846 # Simulator instruction rate (inst/s)
> host_op_rate 351594 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 241521552 # Simulator tick rate (ticks/s)
> host_mem_usage 280036 # Number of bytes of host memory used
> host_seconds 932.36 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 485568 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7587 # Number of read requests accepted
---
> system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 972854 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1183170 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2156024 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 972854 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 972854 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 972854 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1183170 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2156024 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7586 # Number of read requests accepted
35c35
< system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side
60c60
< system.physmem.perBankRdBursts::15 543 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 542 # Per bank write bursts
79c79
< system.physmem.totGap 225206267000 # Total gap between requests
---
> system.physmem.totGap 225184633000 # Total gap between requests
86c86
< system.physmem.readPktSize::6 7587 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7586 # Read request sizes (log2)
94c94
< system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6690 # What read queue length does an incoming req see
190,207c190,207
< system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
< system.physmem.totQLat 232471000 # Total ticks spent queuing
< system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1509 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 321.017893 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 191.649066 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 328.624854 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 538 35.65% 35.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 351 23.26% 58.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 166 11.00% 69.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 79 5.24% 75.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 78 5.17% 80.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 56 3.71% 84.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 32 2.12% 86.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 36 2.39% 88.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 173 11.46% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1509 # Bytes accessed per row activation
> system.physmem.totQLat 232077250 # Total ticks spent queuing
> system.physmem.totMemAccLat 374314750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 30592.84 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 49342.84 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 6073 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6074 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 29683177.41 # Average gap between requests
< system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 29684238.47 # Average gap between requests
> system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined
231,239c231,239
< system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ)
< system.physmem_0.averagePower 244.071435 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states
---
> system.physmem_0.actBackEnergy 100520070 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 15505920 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 721291110 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 385301760 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 53419321200 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 54961303020 # Total energy per rank (pJ)
> system.physmem_0.averagePower 244.071899 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 224923904000 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 29388000 # Time in different power states
241,247c241,247
< system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states
< system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ)
---
> system.physmem_0.memoryStateTime::SREF 222338897000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 1003385750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 110367750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 1581838500 # Time in different power states
> system.physmem_1.actEnergy 6069000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3221955 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 26610780 # Energy for read commands per rank (pJ)
250,258c250,258
< system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ)
< system.physmem_1.averagePower 245.505361 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states
---
> system.physmem_1.actBackEnergy 121194540 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 22344960 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 914224140 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 605228160 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 53190600045 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 55284153510 # Total energy per rank (pJ)
> system.physmem_1.averagePower 245.505612 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 224860041750 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 42127000 # Time in different power states
260,269c260,269
< system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 32430299 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::SREF 221279795000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 1576124250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 114092500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 2004910250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 32421416 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16919401 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 734831 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17534346 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 12860140 # Number of BTB hits
271,272c271,272
< system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 73.342570 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6521085 # Number of times the RAS was used to get a target.
274,277c274,277
< system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 2302887 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 2263691 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 39196 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 128438 # Number of mispredicted indirect branches.
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 450413042 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 225184887000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 450369774 # number of cpu cycles simulated
406c406
< system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2044614 # Number of ops (including micro ops) which were discarded before commit
408,409c408,409
< system.cpu.cpi 1.649636 # CPI: cycles per instruction
< system.cpu.ipc 0.606194 # IPC: instructions per cycle
---
> system.cpu.cpi 1.649477 # CPI: cycles per instruction
> system.cpu.ipc 0.606253 # IPC: instructions per cycle
449,451c449,451
< system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 434912818 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 15456956 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
453,454c453,454
< system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3085.765100 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168647477 # Total number of references to valid blocks.
456c456
< system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37377.543661 # Average number of references to valid blocks.
458c458
< system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.765100 # Average occupied blocks per requestor
468,472c468,472
< system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 337313356 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337313356 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 86514704 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86514704 # number of ReadReq hits
475,476c475,476
< system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits
---
> system.cpu.dcache.SoftPFReq_hits::cpu.data 63536 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 63536 # number of SoftPFReq hits
481,484c481,484
< system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits
< system.cpu.dcache.overall_hits::total 168632415 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168562151 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168562151 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168625687 # number of overall hits
> system.cpu.dcache.overall_hits::total 168625687 # number of overall hits
495,504c495,504
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 177071500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 177071500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 487051000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 487051000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 664122500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 664122500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 664122500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 664122500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86516414 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86516414 # number of ReadReq accesses(hits+misses)
507,508c507,508
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 63541 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 63541 # number of SoftPFReq accesses(hits+misses)
513,516c513,516
< system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168569091 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168569091 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168632632 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168632632 # number of overall (read+write) accesses
527,534c527,534
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103550.584795 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 103550.584795 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93126.386233 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 93126.386233 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 95694.884726 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 95694.884726 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 95625.989921 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 95625.989921 # average overall miss latency
561,564c561,564
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171838500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 171838500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285292000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 285292000 # number of WriteReq MSHR miss cycles
567,570c567,570
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457130500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 457130500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 457389500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 457389500 # number of overall MSHR miss cycles
581,584c581,584
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104843.502135 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104843.502135 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99404.878049 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99404.878049 # average WriteReq mshr miss latency
587,596c587,596
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 38188 # number of replacements
< system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101381.791972 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 101381.791972 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101371.786348 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 101371.786348 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 38251 # number of replacements
> system.cpu.icache.tags.tagsinuse 1924.799688 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 69805458 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 40188 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1736.972678 # Average number of references to valid blocks.
598c598
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.799688 # Average occupied blocks per requestor
608,646c608,646
< system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits
< system.cpu.icache.overall_hits::total 69819801 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses
< system.cpu.icache.overall_misses::total 40126 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 139731482 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 139731482 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 69805458 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 69805458 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 69805458 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 69805458 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 69805458 # number of overall hits
> system.cpu.icache.overall_hits::total 69805458 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 40189 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 40189 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 40189 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 40189 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 40189 # number of overall misses
> system.cpu.icache.overall_misses::total 40189 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 818936000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 818936000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 818936000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 818936000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 818936000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 818936000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 69845647 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 69845647 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 69845647 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 69845647 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 69845647 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 69845647 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000575 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000575 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000575 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000575 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000575 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000575 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20377.118117 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20377.118117 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20377.118117 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20377.118117 # average overall miss latency
653,679c653,679
< system.cpu.icache.writebacks::writebacks 38188 # number of writebacks
< system.cpu.icache.writebacks::total 38188 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.writebacks::writebacks 38251 # number of writebacks
> system.cpu.icache.writebacks::total 38251 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40189 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 40189 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 40189 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 40189 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 40189 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 40189 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 778748000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 778748000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 778748000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 778748000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 778748000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 778748000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000575 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000575 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000575 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19377.142999 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19377.142999 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
681,684c681,684
< system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 6596.199570 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 61643 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 7586 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 8.125890 # Average number of references to valid blocks.
686,688c686,688
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.827893 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.371677 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096674 # Average percentage of cache occupancy
690,691c690,691
< system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::total 0.201300 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 7586 # Occupied blocks per task id
695c695
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 788 # Occupied blocks per task id
697,700c697,700
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231506 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 561762 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 561762 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
703,704c703,704
< system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits
---
> system.cpu.l2cache.WritebackClean_hits::writebacks 23333 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 23333 # number of WritebackClean hits
707,708c707,708
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36700 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 36700 # number of ReadCleanReq hits
---
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36764 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 36764 # number of ReadCleanReq hits
711c711
< system.cpu.l2cache.demand_hits::cpu.inst 36700 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 36764 # number of demand (read+write) hits
713,714c713,714
< system.cpu.l2cache.demand_hits::total 37008 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 36700 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 37072 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 36764 # number of overall hits
716c716
< system.cpu.l2cache.overall_hits::total 37008 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 37072 # number of overall hits
719,720c719,720
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3426 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 3426 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses
723c723
< system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses
725,726c725,726
< system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 7629 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses
728,740c728,740
< system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::total 7629 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 280789500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 280789500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317508500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 317508500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166371500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 166371500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 317508500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 447161000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 764669500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 317508500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 447161000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 764669500 # number of overall miss cycles
743,744c743,744
< system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.WritebackClean_accesses::writebacks 23333 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 23333 # number of WritebackClean accesses(hits+misses)
747,748c747,748
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40126 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 40126 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40189 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 40189 # number of ReadCleanReq accesses(hits+misses)
751c751
< system.cpu.l2cache.demand_accesses::cpu.inst 40126 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 40189 # number of demand (read+write) accesses
753,754c753,754
< system.cpu.l2cache.demand_accesses::total 44638 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 40126 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 44701 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 40189 # number of overall (read+write) accesses
756c756
< system.cpu.l2cache.overall_accesses::total 44638 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 44701 # number of overall (read+write) accesses
759,760c759,760
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085381 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085381 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085222 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085222 # miss rate for ReadCleanReq accesses
763c763
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085222 # miss rate for demand accesses
765,766c765,766
< system.cpu.l2cache.demand_miss_rate::total 0.170931 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.170667 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085222 # miss rate for overall accesses
768,780c768,780
< system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.170667 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98384.548003 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98384.548003 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92703.211679 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92703.211679 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123238.148148 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123238.148148 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 100231.943898 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 100231.943898 # average overall miss latency
799,800c799,800
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3424 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3424 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses
803c803
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses
805,806c805,806
< system.cpu.l2cache.demand_mshr_misses::total 7587 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses
808,820c808,820
< system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252249500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252249500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283130000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283130000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150320500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150320500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283130000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 402570000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 685700000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283130000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 402570000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 685700000 # number of overall MSHR miss cycles
823,824c823,824
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085173 # mshr miss rate for ReadCleanReq accesses
827c827
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for demand accesses
829,830c829,830
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.169705 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for overall accesses
832,846c832,846
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.169705 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88384.548003 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88384.548003 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82713.993573 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82713.993573 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114836.134454 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114836.134454 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 84307 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 39708 # Number of requests hitting in the snoop filter with a single holder of the requested data.
851,852c851,852
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 41830 # Transaction distribution
854c854
< system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackClean 38251 # Transaction distribution
858c858
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 40189 # Transaction distribution
860c860
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118439 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118628 # Packet count per connected master and slave (bytes)
862,863c862,863
< system.cpu.toL2Bus.pkt_count::total 128818 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5012032 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 129007 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5020096 # Cumulative packet size per connected master and slave (bytes)
865c865
< system.cpu.toL2Bus.pkt_size::total 5365440 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 5373504 # Cumulative packet size per connected master and slave (bytes)
868,870c868,870
< system.cpu.toL2Bus.snoop_fanout::samples 44638 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.339106 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.473411 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 44701 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.338628 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.473248 # Request fanout histogram
872,873c872,873
< system.cpu.toL2Bus.snoop_fanout::0 29501 66.09% 66.09% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 15137 33.91% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 29564 66.14% 66.14% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 15137 33.86% 100.00% # Request fanout histogram
878,879c878,879
< system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 44701 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 81414500 # Layer occupancy (ticks)
881c881
< system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 60282998 # Layer occupancy (ticks)
885c885
< system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter.
---
> system.membus.snoop_filter.tot_requests 7586 # Total number of requests made to the snoop filter.
891,892c891,892
< system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 4733 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 4732 # Transaction distribution
895,899c895,899
< system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes)
902c902
< system.membus.snoop_fanout::samples 7587 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 7586 # Request fanout histogram
906c906
< system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram
911,912c911,912
< system.membus.snoop_fanout::total 7587 # Request fanout histogram
< system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 7586 # Request fanout histogram
> system.membus.reqLayer0.occupancy 9076000 # Layer occupancy (ticks)
914c914
< system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40293000 # Layer occupancy (ticks)