7,11c7,11
< host_inst_rate 284094 # Simulator instruction rate (inst/s)
< host_op_rate 341086 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 234325505 # Simulator tick rate (ticks/s)
< host_mem_usage 279956 # Number of bytes of host memory used
< host_seconds 961.08 # Real time elapsed on the host
---
> host_inst_rate 289736 # Simulator instruction rate (inst/s)
> host_op_rate 347860 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 238979319 # Simulator tick rate (ticks/s)
> host_mem_usage 279872 # Number of bytes of host memory used
> host_seconds 942.37 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 232482000 # Total ticks spent queuing
< system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 232471000 # Total ticks spent queuing
> system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ)
233,234c233,234
< system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ)
< system.physmem_0.averagePower 244.071438 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ)
> system.physmem_0.averagePower 244.071435 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank
242,243c242,243
< system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states
250c250
< system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ)
449,450c449,450
< system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped
453c453
< system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use
458c458
< system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor
593c593
< system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use
598c598
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor
623,628c623,628
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles
641,646c641,646
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency
661,666c661,666
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles
673,678c673,678
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
681c681
< system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use
686,687c686,687
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor
731,732c731,732
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles
735c735
< system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles
737,738c737,738
< system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles
740c740
< system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles
771,772c771,772
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency
775c775
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
777,778c777,778
< system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
780c780
< system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency
811,812c811,812
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles
815c815
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles
817,818c817,818
< system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles
820c820
< system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles
835,836c835,836
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency
839c839
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
841,842c841,842
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
844c844
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
912c912
< system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks)
< host_inst_rate 284094 # Simulator instruction rate (inst/s)
< host_op_rate 341086 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 234325505 # Simulator tick rate (ticks/s)
< host_mem_usage 279956 # Number of bytes of host memory used
< host_seconds 961.08 # Real time elapsed on the host
---
> host_inst_rate 289736 # Simulator instruction rate (inst/s)
> host_op_rate 347860 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 238979319 # Simulator tick rate (ticks/s)
> host_mem_usage 279872 # Number of bytes of host memory used
> host_seconds 942.37 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 232482000 # Total ticks spent queuing
< system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 232471000 # Total ticks spent queuing
> system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ)
233,234c233,234
< system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ)
< system.physmem_0.averagePower 244.071438 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ)
> system.physmem_0.averagePower 244.071435 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank
242,243c242,243
< system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states
250c250
< system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ)
449,450c449,450
< system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped
453c453
< system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use
458c458
< system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor
593c593
< system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use
598c598
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor
623,628c623,628
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles
641,646c641,646
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency
661,666c661,666
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles
673,678c673,678
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
681c681
< system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use
686,687c686,687
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor
731,732c731,732
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles
735c735
< system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles
737,738c737,738
< system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles
740c740
< system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles
771,772c771,772
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency
775c775
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
777,778c777,778
< system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
780c780
< system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency
811,812c811,812
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles
815c815
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles
817,818c817,818
< system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles
820c820
< system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles
835,836c835,836
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency
839c839
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
841,842c841,842
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
844c844
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
912c912
< system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks)