3,5c3,5
< sim_seconds 0.225041 # Number of seconds simulated
< sim_ticks 225040911000 # Number of ticks simulated
< final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.225207 # Number of seconds simulated
> sim_ticks 225206521000 # Number of ticks simulated
> final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 161529 # Simulator instruction rate (inst/s)
< host_op_rate 193933 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 133133968 # Simulator tick rate (ticks/s)
< host_mem_usage 280148 # Number of bytes of host memory used
< host_seconds 1690.33 # Real time elapsed on the host
---
> host_inst_rate 132189 # Simulator instruction rate (inst/s)
> host_op_rate 158707 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 109031633 # Simulator tick rate (ticks/s)
> host_mem_usage 278744 # Number of bytes of host memory used
> host_seconds 2065.52 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 225040663000 # Total gap between requests
---
> system.physmem.totGap 225206267000 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 6713 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 823 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see
190,205c190,205
< system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation
< system.physmem.totQLat 55497500 # Total ticks spent queuing
< system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
> system.physmem.totQLat 232482000 # Total ticks spent queuing
> system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 6044 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6073 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 29661350.07 # Average gap between requests
< system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 29683177.41 # Average gap between requests
> system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ)
230,242c230,247
< system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.691134 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ)
> system.physmem_0.averagePower 244.071438 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states
> system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ)
244,256c249,266
< system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.800930 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 32430292 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted
---
> system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ)
> system.physmem_1.averagePower 245.505361 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 32430299 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted
258,259c268,269
< system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits
261,262c271,272
< system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target.
269c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
299c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
329c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
359c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
390,391c400,401
< system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 450081822 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 450413042 # number of cpu cycles simulated
396c406
< system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit
398,399c408,409
< system.cpu.cpi 1.648423 # CPI: cycles per instruction
< system.cpu.ipc 0.606640 # IPC: instructions per cycle
---
> system.cpu.cpi 1.649636 # CPI: cycles per instruction
> system.cpu.ipc 0.606194 # IPC: instructions per cycle
435,437c445,447
< system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
439,440c449,450
< system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks.
442c452
< system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks.
444,446c454,456
< system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy
448,449c458,459
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
454,460c464,470
< system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits
467,470c477,480
< system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits
< system.cpu.dcache.overall_hits::total 168632429 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits
> system.cpu.dcache.overall_hits::total 168632415 # number of overall hits
473,474c483,484
< system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses
477,490c487,500
< system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses
< system.cpu.dcache.overall_misses::total 6935 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses
> system.cpu.dcache.overall_misses::total 6945 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses)
499,502c509,512
< system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses
513,520c523,530
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency
531,536c541,546
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits
547,556c557,566
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles
567,577c577,587
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
579,580c589,590
< system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks.
582c592
< system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks.
584,586c594,596
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy
588,589c598,599
< system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
594,602c604,612
< system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits
< system.cpu.icache.overall_hits::total 69819782 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits
> system.cpu.icache.overall_hits::total 69819801 # number of overall hits
609,620c619,630
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses
627,632c637,642
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency
647,652c657,662
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles
659,665c669,675
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
667c677
< system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use
672,676c682,686
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy
678,679c688,689
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
686c696
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
715,726c725,736
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles
755,766c765,776
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency
795,806c805,816
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles
819,830c829,840
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
837c847
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
877c887
< system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
898c908
< system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks)
900c910
< system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks)
< sim_seconds 0.225041 # Number of seconds simulated
< sim_ticks 225040911000 # Number of ticks simulated
< final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.225207 # Number of seconds simulated
> sim_ticks 225206521000 # Number of ticks simulated
> final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 161529 # Simulator instruction rate (inst/s)
< host_op_rate 193933 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 133133968 # Simulator tick rate (ticks/s)
< host_mem_usage 280148 # Number of bytes of host memory used
< host_seconds 1690.33 # Real time elapsed on the host
---
> host_inst_rate 132189 # Simulator instruction rate (inst/s)
> host_op_rate 158707 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 109031633 # Simulator tick rate (ticks/s)
> host_mem_usage 278744 # Number of bytes of host memory used
> host_seconds 2065.52 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 225040663000 # Total gap between requests
---
> system.physmem.totGap 225206267000 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 6713 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 823 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see
190,205c190,205
< system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation
< system.physmem.totQLat 55497500 # Total ticks spent queuing
< system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
> system.physmem.totQLat 232482000 # Total ticks spent queuing
> system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 6044 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6073 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 29661350.07 # Average gap between requests
< system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 29683177.41 # Average gap between requests
> system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ)
230,242c230,247
< system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.691134 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ)
> system.physmem_0.averagePower 244.071438 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states
> system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ)
244,256c249,266
< system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.800930 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 32430292 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted
---
> system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ)
> system.physmem_1.averagePower 245.505361 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 32430299 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted
258,259c268,269
< system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits
261,262c271,272
< system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target.
269c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
299c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
329c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
359c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
390,391c400,401
< system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 450081822 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 450413042 # number of cpu cycles simulated
396c406
< system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit
398,399c408,409
< system.cpu.cpi 1.648423 # CPI: cycles per instruction
< system.cpu.ipc 0.606640 # IPC: instructions per cycle
---
> system.cpu.cpi 1.649636 # CPI: cycles per instruction
> system.cpu.ipc 0.606194 # IPC: instructions per cycle
435,437c445,447
< system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
439,440c449,450
< system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks.
442c452
< system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks.
444,446c454,456
< system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy
448,449c458,459
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
454,460c464,470
< system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits
467,470c477,480
< system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits
< system.cpu.dcache.overall_hits::total 168632429 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits
> system.cpu.dcache.overall_hits::total 168632415 # number of overall hits
473,474c483,484
< system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses
477,490c487,500
< system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses
< system.cpu.dcache.overall_misses::total 6935 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses
> system.cpu.dcache.overall_misses::total 6945 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses)
499,502c509,512
< system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses
513,520c523,530
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency
531,536c541,546
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits
547,556c557,566
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles
567,577c577,587
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
579,580c589,590
< system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks.
582c592
< system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks.
584,586c594,596
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy
588,589c598,599
< system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
594,602c604,612
< system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits
< system.cpu.icache.overall_hits::total 69819782 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits
> system.cpu.icache.overall_hits::total 69819801 # number of overall hits
609,620c619,630
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses
627,632c637,642
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency
647,652c657,662
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles
659,665c669,675
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
667c677
< system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use
672,676c682,686
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy
678,679c688,689
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
686c696
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
715,726c725,736
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles
755,766c765,776
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency
795,806c805,816
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles
819,830c829,840
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency
837c847
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
877c887
< system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
898c908
< system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks)
900c910
< system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks)