3,5c3,5
< sim_seconds 0.225030 # Number of seconds simulated
< sim_ticks 225030243000 # Number of ticks simulated
< final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.225041 # Number of seconds simulated
> sim_ticks 225040911000 # Number of ticks simulated
> final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 131394 # Simulator instruction rate (inst/s)
< host_op_rate 157754 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 108291606 # Simulator tick rate (ticks/s)
< host_mem_usage 275248 # Number of bytes of host memory used
< host_seconds 2078.00 # Real time elapsed on the host
---
> host_inst_rate 161529 # Simulator instruction rate (inst/s)
> host_op_rate 193933 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 133133968 # Simulator tick rate (ticks/s)
> host_mem_usage 280148 # Number of bytes of host memory used
> host_seconds 1690.33 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 225029996000 # Total gap between requests
---
> system.physmem.totGap 225040663000 # Total gap between requests
190,205c190,205
< system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
< system.physmem.totQLat 51456750 # Total ticks spent queuing
< system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation
> system.physmem.totQLat 55497500 # Total ticks spent queuing
> system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 6068 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6044 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 29659944.11 # Average gap between requests
< system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 29661350.07 # Average gap between requests
> system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ)
230,236c230,236
< system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.664832 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states
---
> system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.691134 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states
240,241c240,241
< system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ)
---
> system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ)
244,250c244,250
< system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.764823 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states
---
> system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.800930 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states
> system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states
254,255c254,255
< system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 32430290 # Number of BP lookups
---
> system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 32430292 # Number of BP lookups
258,259c258,259
< system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits
261c261
< system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 450060486 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 450081822 # number of cpu cycles simulated
396c396
< system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit
398,399c398,399
< system.cpu.cpi 1.648345 # CPI: cycles per instruction
< system.cpu.ipc 0.606669 # IPC: instructions per cycle
---
> system.cpu.cpi 1.648423 # CPI: cycles per instruction
> system.cpu.ipc 0.606640 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
439,440c439,440
< system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks.
442c442
< system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks.
444,446c444,446
< system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy
454,460c454,460
< system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
467,470c467,470
< system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits
< system.cpu.dcache.overall_hits::total 168632427 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits
> system.cpu.dcache.overall_hits::total 168632429 # number of overall hits
473,474c473,474
< system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
477,490c477,490
< system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses
< system.cpu.dcache.overall_misses::total 6936 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses
> system.cpu.dcache.overall_misses::total 6935 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses)
499,502c499,502
< system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses
513,520c513,520
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency
531,536c531,536
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits
547,556c547,556
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles
567,577c567,577
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
579,580c579,580
< system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks.
582c582
< system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks.
584,586c584,586
< system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy
588,589c588,589
< system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
594,602c594,602
< system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits
< system.cpu.icache.overall_hits::total 69819783 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits
> system.cpu.icache.overall_hits::total 69819782 # number of overall hits
609,620c609,620
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses
627,632c627,632
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency
647,652c647,652
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles
659,665c659,665
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
667,670c667,670
< system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks.
672,681c672,679
< system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
683,688c681,686
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
717,728c715,726
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles
757,768c755,766
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency
797,808c795,806
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles
821,832c819,830
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
839c837
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
873c871,877
< system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
894c898
< system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks)
896c900
< system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks)
< sim_seconds 0.225030 # Number of seconds simulated
< sim_ticks 225030243000 # Number of ticks simulated
< final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.225041 # Number of seconds simulated
> sim_ticks 225040911000 # Number of ticks simulated
> final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 131394 # Simulator instruction rate (inst/s)
< host_op_rate 157754 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 108291606 # Simulator tick rate (ticks/s)
< host_mem_usage 275248 # Number of bytes of host memory used
< host_seconds 2078.00 # Real time elapsed on the host
---
> host_inst_rate 161529 # Simulator instruction rate (inst/s)
> host_op_rate 193933 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 133133968 # Simulator tick rate (ticks/s)
> host_mem_usage 280148 # Number of bytes of host memory used
> host_seconds 1690.33 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 225029996000 # Total gap between requests
---
> system.physmem.totGap 225040663000 # Total gap between requests
190,205c190,205
< system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
< system.physmem.totQLat 51456750 # Total ticks spent queuing
< system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation
> system.physmem.totQLat 55497500 # Total ticks spent queuing
> system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 6068 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6044 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 29659944.11 # Average gap between requests
< system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 29661350.07 # Average gap between requests
> system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ)
230,236c230,236
< system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.664832 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states
---
> system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.691134 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states
240,241c240,241
< system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ)
---
> system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ)
244,250c244,250
< system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.764823 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states
---
> system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.800930 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states
> system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states
254,255c254,255
< system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 32430290 # Number of BP lookups
---
> system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 32430292 # Number of BP lookups
258,259c258,259
< system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits
261c261
< system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 450060486 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 450081822 # number of cpu cycles simulated
396c396
< system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit
398,399c398,399
< system.cpu.cpi 1.648345 # CPI: cycles per instruction
< system.cpu.ipc 0.606669 # IPC: instructions per cycle
---
> system.cpu.cpi 1.648423 # CPI: cycles per instruction
> system.cpu.ipc 0.606640 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
439,440c439,440
< system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks.
442c442
< system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks.
444,446c444,446
< system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy
454,460c454,460
< system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
467,470c467,470
< system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits
< system.cpu.dcache.overall_hits::total 168632427 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits
> system.cpu.dcache.overall_hits::total 168632429 # number of overall hits
473,474c473,474
< system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
477,490c477,490
< system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses
< system.cpu.dcache.overall_misses::total 6936 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses
> system.cpu.dcache.overall_misses::total 6935 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses)
499,502c499,502
< system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses
513,520c513,520
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency
531,536c531,536
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits
547,556c547,556
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles
567,577c567,577
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
579,580c579,580
< system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks.
582c582
< system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks.
584,586c584,586
< system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy
588,589c588,589
< system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
594,602c594,602
< system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits
< system.cpu.icache.overall_hits::total 69819783 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits
> system.cpu.icache.overall_hits::total 69819782 # number of overall hits
609,620c609,620
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses
627,632c627,632
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency
647,652c647,652
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles
659,665c659,665
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
667,670c667,670
< system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks.
672,681c672,679
< system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
683,688c681,686
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
717,728c715,726
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles
757,768c755,766
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency
797,808c795,806
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles
821,832c819,830
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
839c837
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
873c871,877
< system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
894c898
< system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks)
896c900
< system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks)