3,5c3,5
< sim_seconds 0.216744 # Number of seconds simulated
< sim_ticks 216744260000 # Number of ticks simulated
< final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.216140 # Number of seconds simulated
> sim_ticks 216139917000 # Number of ticks simulated
> final_tick 216139917000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 172626 # Simulator instruction rate (inst/s)
< host_op_rate 207257 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 137034779 # Simulator tick rate (ticks/s)
< host_mem_usage 322768 # Number of bytes of host memory used
< host_seconds 1581.67 # Real time elapsed on the host
---
> host_inst_rate 173188 # Simulator instruction rate (inst/s)
> host_op_rate 207931 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 137097336 # Simulator tick rate (ticks/s)
> host_mem_usage 323040 # Number of bytes of host memory used
> host_seconds 1576.54 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7583 # Number of read requests accepted
---
> system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1013862 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1232387 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2246249 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1013862 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1013862 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1013862 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1232387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2246249 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7586 # Number of read requests accepted
34c34
< system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::5 348 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 349 # Per bank write bursts
58,59c58,59
< system.physmem.perBankRdBursts::14 637 # Per bank write bursts
< system.physmem.perBankRdBursts::15 540 # Per bank write bursts
---
> system.physmem.perBankRdBursts::14 638 # Per bank write bursts
> system.physmem.perBankRdBursts::15 541 # Per bank write bursts
78c78
< system.physmem.totGap 216744023500 # Total gap between requests
---
> system.physmem.totGap 216139680500 # Total gap between requests
85c85
< system.physmem.readPktSize::6 7583 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7586 # Read request sizes (log2)
93,95c93,95
< system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6624 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation
< system.physmem.totQLat 54921500 # Total ticks spent queuing
< system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 318.319107 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 188.795582 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 330.243204 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 551 36.18% 36.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 346 22.72% 58.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 176 11.56% 70.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 81 5.32% 75.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 75 4.92% 80.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 50 3.28% 83.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 32 2.10% 86.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 28 1.84% 87.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 184 12.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
> system.physmem.totQLat 53007250 # Total ticks spent queuing
> system.physmem.totMemAccLat 195244750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 6987.51 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 25737.51 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.readRowHits 6057 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6060 # Number of row buffer hits during reads
223c223
< system.physmem.avgGap 28582885.86 # Average gap between requests
---
> system.physmem.avgGap 28491916.75 # Average gap between requests
225,227c225,227
< system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
---
> system.physmem_0.actEnergy 5004720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2730750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 30022200 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.684406 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states
---
> system.physmem_0.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5648540400 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 124728404250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 144531819360 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.699173 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 207494790250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 7217340000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1426657250 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 6509160 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3551625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 29062800 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.812768 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states
---
> system.physmem_1.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5781551040 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 124611728250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 144549519915 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.781068 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 207298156250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 7217340000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1623563250 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 33185861 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits
---
> system.cpu.branchPred.lookups 33139216 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17107199 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1560655 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17520877 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15610870 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 89.098679 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6611023 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 433488520 # number of cpu cycles simulated
---
> system.cpu.numCycles 432279834 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 4207498 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.587650 # CPI: cycles per instruction
< system.cpu.ipc 0.629862 # IPC: instructions per cycle
< system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.583223 # CPI: cycles per instruction
> system.cpu.ipc 0.631623 # IPC: instructions per cycle
> system.cpu.tickCycles 428628441 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 3651393 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3085.737950 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168771151 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37413.245622 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.737950 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753354 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753354 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
407,414c407,414
< system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 337561379 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337561379 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 86638362 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86638362 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047459 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047459 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits
419,422c419,422
< system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits
< system.cpu.dcache.overall_hits::total 168747655 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168685821 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168685821 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168749361 # number of overall hits
> system.cpu.dcache.overall_hits::total 168749361 # number of overall hits
425,426c425,426
< system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 5218 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5218 # number of WriteReq misses
429,442c429,442
< system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses
< system.cpu.dcache.overall_misses::total 7285 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 7277 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7277 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 7283 # number of overall misses
> system.cpu.dcache.overall_misses::total 7283 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 136967456 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 136967456 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 400451000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 400451000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 537418456 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 537418456 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 537418456 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 537418456 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86640421 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86640421 # number of ReadReq accesses(hits+misses)
445,446c445,446
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses)
451,454c451,454
< system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168693098 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168693098 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168756644 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168756644 # number of overall (read+write) accesses
465,472c465,472
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73851.649856 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73790.808183 # average overall miss latency
485,490c485,490
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2348 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2348 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2770 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2770 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2770 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2770 # number of overall MSHR hits
501,504c501,504
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108888792 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 108888792 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220256750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 220256750 # number of WriteReq MSHR miss cycles
507,510c507,510
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329145542 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 329145542 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329466292 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 329466292 # number of overall MSHR miss cycles
521,524c521,524
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195 # average WriteReq mshr miss latency
527,530c527,530
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626 # average overall mshr miss latency
532,536c532,536
< system.cpu.icache.tags.replacements 36918 # number of replacements
< system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 36928 # number of replacements
> system.cpu.icache.tags.tagsinuse 1924.841098 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 73108223 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 38865 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1881.081256 # Average number of references to valid blocks.
538,540c538,540
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.841098 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939864 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939864 # Average percentage of cache occupancy
542,546c542,546
< system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id
548,573c548,573
< system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits
< system.cpu.icache.overall_hits::total 73120141 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses
< system.cpu.icache.overall_misses::total 38856 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 146333043 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146333043 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 73108223 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 73108223 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 73108223 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 73108223 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 73108223 # number of overall hits
> system.cpu.icache.overall_hits::total 73108223 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 38866 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 38866 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 38866 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 38866 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 38866 # number of overall misses
> system.cpu.icache.overall_misses::total 38866 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 728130248 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 728130248 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 728130248 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 728130248 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 728130248 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 728130248 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 73147089 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 73147089 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 73147089 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 73147089 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 73147089 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 73147089 # number of overall (read+write) accesses
580,585c580,585
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18742.414247 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18742.414247 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18734.375753 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18734.375753 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18734.375753 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18734.375753 # average overall miss latency
594,605c594,605
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38856 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 38856 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 38856 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 38856 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 38856 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 38856 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668527252 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 668527252 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668527252 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 668527252 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668527252 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 668527252 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38866 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 38866 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 38866 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 38866 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 38866 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 38866 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668381252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 668381252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668381252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 668381252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668381252 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 668381252 # number of overall MSHR miss cycles
612,617c612,617
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17205.251493 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17205.251493 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17197.068183 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17197.068183 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency
620,623c620,623
< system.cpu.l2cache.tags.tagsinuse 4198.154832 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 35803 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5645 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.342427 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 4199.211257 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 35810 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.340297 # Average number of references to valid blocks.
625,629c625,629
< system.cpu.l2cache.tags.occ_blocks::writebacks 353.729151 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.134287 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 678.291394 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096623 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 353.787736 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.125698 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 678.297823 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096653 # Average percentage of cache occupancy
631,634c631,634
< system.cpu.l2cache.tags.occ_percent::total 0.128118 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5645 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::total 0.128150 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
636,641c636,641
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1250 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172272 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 363531 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 363531 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 35433 # number of ReadReq hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4261 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 363614 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 363614 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 35440 # number of ReadReq hits
643c643
< system.cpu.l2cache.ReadReq_hits::total 35724 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 35731 # number of ReadReq hits
648c648
< system.cpu.l2cache.demand_hits::cpu.inst 35433 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 35440 # number of demand (read+write) hits
650,651c650,651
< system.cpu.l2cache.demand_hits::total 35740 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 35433 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 35747 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 35440 # number of overall hits
653,654c653,654
< system.cpu.l2cache.overall_hits::total 35740 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3423 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 35747 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses
656c656
< system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses
659c659
< system.cpu.l2cache.demand_misses::cpu.inst 3423 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses
661,662c661,662
< system.cpu.l2cache.demand_misses::total 7627 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3423 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
664,676c664,676
< system.cpu.l2cache.overall_misses::total 7627 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 257633750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105610250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 363244000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217699750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 217699750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 257633750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 323310000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 580943750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 257633750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 323310000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 580943750 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 38856 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 257404250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104503500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 361907750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 217183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 257404250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 321687250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 579091500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 257404250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 321687250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 579091500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 38866 # number of ReadReq accesses(hits+misses)
678c678
< system.cpu.l2cache.ReadReq_accesses::total 40497 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 40507 # number of ReadReq accesses(hits+misses)
683c683
< system.cpu.l2cache.demand_accesses::cpu.inst 38856 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 38866 # number of demand (read+write) accesses
685,686c685,686
< system.cpu.l2cache.demand_accesses::total 43367 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 38856 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 43377 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 38866 # number of overall (read+write) accesses
688,689c688,689
< system.cpu.l2cache.overall_accesses::total 43367 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088095 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 43377 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088149 # miss rate for ReadReq accesses
691c691
< system.cpu.l2cache.ReadReq_miss_rate::total 0.117861 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.117906 # miss rate for ReadReq accesses
694c694
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088095 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088149 # miss rate for demand accesses
696,697c696,697
< system.cpu.l2cache.demand_miss_rate::total 0.175871 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088095 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.175900 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088149 # miss rate for overall accesses
699,710c699,710
< system.cpu.l2cache.overall_miss_rate::total 0.175871 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75265.483494 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78229.814815 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 76103.917871 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76278.819201 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76278.819201 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76169.365412 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.175900 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75132.589025 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77410 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75776.329564 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76098.020322 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76098.020322 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75896.657929 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75896.657929 # average overall miss latency
728c728
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3424 # number of ReadReq MSHR misses
730c730
< system.cpu.l2cache.ReadReq_mshr_misses::total 4729 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 4732 # number of ReadReq MSHR misses
733c733
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses
735,736c735,736
< system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses
738,750c738,750
< system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214398750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85427750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 299826500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181482250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181482250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214398750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266910000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 481308750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214398750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266910000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 481308750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for ReadReq accesses
752c752
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116819 # mshr miss rate for ReadReq accesses
755c755
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for demand accesses
757,758c757,758
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.174885 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for overall accesses
760,771c760,771
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.174885 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency
773,774c773,774
< system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 40507 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 40506 # Transaction distribution
778c778
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77731 # Packet count per connected master and slave (bytes)
780,781c780,781
< system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 87763 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487360 # Cumulative packet size per connected master and slave (bytes)
783c783
< system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 2840704 # Cumulative packet size per connected master and slave (bytes)
785c785
< system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 44387 # Request fanout histogram
790c790
< system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 44387 100.00% 100.00% # Request fanout histogram
795,796c795,796
< system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 44387 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 23203500 # Layer occupancy (ticks)
798c798
< system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 59023248 # Layer occupancy (ticks)
800c800
< system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 7574708 # Layer occupancy (ticks)
802,803c802,803
< system.membus.trans_dist::ReadReq 4729 # Transaction distribution
< system.membus.trans_dist::ReadResp 4729 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 4732 # Transaction distribution
> system.membus.trans_dist::ReadResp 4732 # Transaction distribution
806,809c806,809
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes)
811c811
< system.membus.snoop_fanout::samples 7583 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 7586 # Request fanout histogram
815c815
< system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram
820,821c820,821
< system.membus.snoop_fanout::total 7583 # Request fanout histogram
< system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 7586 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8848500 # Layer occupancy (ticks)
823c823
< system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40266750 # Layer occupancy (ticks)
< sim_seconds 0.216744 # Number of seconds simulated
< sim_ticks 216744260000 # Number of ticks simulated
< final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.216140 # Number of seconds simulated
> sim_ticks 216139917000 # Number of ticks simulated
> final_tick 216139917000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 172626 # Simulator instruction rate (inst/s)
< host_op_rate 207257 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 137034779 # Simulator tick rate (ticks/s)
< host_mem_usage 322768 # Number of bytes of host memory used
< host_seconds 1581.67 # Real time elapsed on the host
---
> host_inst_rate 173188 # Simulator instruction rate (inst/s)
> host_op_rate 207931 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 137097336 # Simulator tick rate (ticks/s)
> host_mem_usage 323040 # Number of bytes of host memory used
> host_seconds 1576.54 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7583 # Number of read requests accepted
---
> system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1013862 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1232387 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2246249 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1013862 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1013862 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1013862 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1232387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2246249 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7586 # Number of read requests accepted
34c34
< system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::5 348 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 349 # Per bank write bursts
58,59c58,59
< system.physmem.perBankRdBursts::14 637 # Per bank write bursts
< system.physmem.perBankRdBursts::15 540 # Per bank write bursts
---
> system.physmem.perBankRdBursts::14 638 # Per bank write bursts
> system.physmem.perBankRdBursts::15 541 # Per bank write bursts
78c78
< system.physmem.totGap 216744023500 # Total gap between requests
---
> system.physmem.totGap 216139680500 # Total gap between requests
85c85
< system.physmem.readPktSize::6 7583 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7586 # Read request sizes (log2)
93,95c93,95
< system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6624 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation
< system.physmem.totQLat 54921500 # Total ticks spent queuing
< system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 318.319107 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 188.795582 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 330.243204 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 551 36.18% 36.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 346 22.72% 58.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 176 11.56% 70.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 81 5.32% 75.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 75 4.92% 80.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 50 3.28% 83.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 32 2.10% 86.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 28 1.84% 87.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 184 12.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
> system.physmem.totQLat 53007250 # Total ticks spent queuing
> system.physmem.totMemAccLat 195244750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 6987.51 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 25737.51 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.readRowHits 6057 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6060 # Number of row buffer hits during reads
223c223
< system.physmem.avgGap 28582885.86 # Average gap between requests
---
> system.physmem.avgGap 28491916.75 # Average gap between requests
225,227c225,227
< system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
---
> system.physmem_0.actEnergy 5004720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2730750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 30022200 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.684406 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states
---
> system.physmem_0.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5648540400 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 124728404250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 144531819360 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.699173 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 207494790250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 7217340000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1426657250 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 6509160 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3551625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 29062800 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.812768 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states
---
> system.physmem_1.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5781551040 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 124611728250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 144549519915 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.781068 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 207298156250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 7217340000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1623563250 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 33185861 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits
---
> system.cpu.branchPred.lookups 33139216 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17107199 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1560655 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17520877 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15610870 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 89.098679 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6611023 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 433488520 # number of cpu cycles simulated
---
> system.cpu.numCycles 432279834 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 4207498 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.587650 # CPI: cycles per instruction
< system.cpu.ipc 0.629862 # IPC: instructions per cycle
< system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.583223 # CPI: cycles per instruction
> system.cpu.ipc 0.631623 # IPC: instructions per cycle
> system.cpu.tickCycles 428628441 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 3651393 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3085.737950 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168771151 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37413.245622 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.737950 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753354 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753354 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
407,414c407,414
< system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 337561379 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337561379 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 86638362 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86638362 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047459 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047459 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits
419,422c419,422
< system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits
< system.cpu.dcache.overall_hits::total 168747655 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168685821 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168685821 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168749361 # number of overall hits
> system.cpu.dcache.overall_hits::total 168749361 # number of overall hits
425,426c425,426
< system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 5218 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5218 # number of WriteReq misses
429,442c429,442
< system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses
< system.cpu.dcache.overall_misses::total 7285 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 7277 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7277 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 7283 # number of overall misses
> system.cpu.dcache.overall_misses::total 7283 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 136967456 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 136967456 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 400451000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 400451000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 537418456 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 537418456 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 537418456 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 537418456 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86640421 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86640421 # number of ReadReq accesses(hits+misses)
445,446c445,446
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses)
451,454c451,454
< system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168693098 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168693098 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168756644 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168756644 # number of overall (read+write) accesses
465,472c465,472
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73851.649856 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73790.808183 # average overall miss latency
485,490c485,490
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2348 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2348 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2770 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2770 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2770 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2770 # number of overall MSHR hits
501,504c501,504
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108888792 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 108888792 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220256750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 220256750 # number of WriteReq MSHR miss cycles
507,510c507,510
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329145542 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 329145542 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329466292 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 329466292 # number of overall MSHR miss cycles
521,524c521,524
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195 # average WriteReq mshr miss latency
527,530c527,530
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626 # average overall mshr miss latency
532,536c532,536
< system.cpu.icache.tags.replacements 36918 # number of replacements
< system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 36928 # number of replacements
> system.cpu.icache.tags.tagsinuse 1924.841098 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 73108223 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 38865 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1881.081256 # Average number of references to valid blocks.
538,540c538,540
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.841098 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939864 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939864 # Average percentage of cache occupancy
542,546c542,546
< system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id
548,573c548,573
< system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits
< system.cpu.icache.overall_hits::total 73120141 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses
< system.cpu.icache.overall_misses::total 38856 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 146333043 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146333043 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 73108223 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 73108223 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 73108223 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 73108223 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 73108223 # number of overall hits
> system.cpu.icache.overall_hits::total 73108223 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 38866 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 38866 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 38866 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 38866 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 38866 # number of overall misses
> system.cpu.icache.overall_misses::total 38866 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 728130248 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 728130248 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 728130248 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 728130248 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 728130248 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 728130248 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 73147089 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 73147089 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 73147089 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 73147089 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 73147089 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 73147089 # number of overall (read+write) accesses
580,585c580,585
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18742.414247 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18742.414247 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18734.375753 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18734.375753 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18734.375753 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18734.375753 # average overall miss latency
594,605c594,605
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38856 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 38856 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 38856 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 38856 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 38856 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 38856 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668527252 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 668527252 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668527252 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 668527252 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668527252 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 668527252 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38866 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 38866 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 38866 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 38866 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 38866 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 38866 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668381252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 668381252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668381252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 668381252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668381252 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 668381252 # number of overall MSHR miss cycles
612,617c612,617
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17205.251493 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17205.251493 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17197.068183 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17197.068183 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency
620,623c620,623
< system.cpu.l2cache.tags.tagsinuse 4198.154832 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 35803 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5645 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.342427 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 4199.211257 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 35810 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.340297 # Average number of references to valid blocks.
625,629c625,629
< system.cpu.l2cache.tags.occ_blocks::writebacks 353.729151 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.134287 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 678.291394 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096623 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 353.787736 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.125698 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 678.297823 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096653 # Average percentage of cache occupancy
631,634c631,634
< system.cpu.l2cache.tags.occ_percent::total 0.128118 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5645 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::total 0.128150 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
636,641c636,641
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1250 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172272 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 363531 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 363531 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 35433 # number of ReadReq hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4261 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 363614 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 363614 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 35440 # number of ReadReq hits
643c643
< system.cpu.l2cache.ReadReq_hits::total 35724 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 35731 # number of ReadReq hits
648c648
< system.cpu.l2cache.demand_hits::cpu.inst 35433 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 35440 # number of demand (read+write) hits
650,651c650,651
< system.cpu.l2cache.demand_hits::total 35740 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 35433 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 35747 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 35440 # number of overall hits
653,654c653,654
< system.cpu.l2cache.overall_hits::total 35740 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3423 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 35747 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses
656c656
< system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses
659c659
< system.cpu.l2cache.demand_misses::cpu.inst 3423 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses
661,662c661,662
< system.cpu.l2cache.demand_misses::total 7627 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3423 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
664,676c664,676
< system.cpu.l2cache.overall_misses::total 7627 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 257633750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105610250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 363244000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217699750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 217699750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 257633750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 323310000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 580943750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 257633750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 323310000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 580943750 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 38856 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 257404250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104503500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 361907750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 217183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 257404250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 321687250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 579091500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 257404250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 321687250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 579091500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 38866 # number of ReadReq accesses(hits+misses)
678c678
< system.cpu.l2cache.ReadReq_accesses::total 40497 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 40507 # number of ReadReq accesses(hits+misses)
683c683
< system.cpu.l2cache.demand_accesses::cpu.inst 38856 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 38866 # number of demand (read+write) accesses
685,686c685,686
< system.cpu.l2cache.demand_accesses::total 43367 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 38856 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 43377 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 38866 # number of overall (read+write) accesses
688,689c688,689
< system.cpu.l2cache.overall_accesses::total 43367 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088095 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 43377 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088149 # miss rate for ReadReq accesses
691c691
< system.cpu.l2cache.ReadReq_miss_rate::total 0.117861 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.117906 # miss rate for ReadReq accesses
694c694
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088095 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088149 # miss rate for demand accesses
696,697c696,697
< system.cpu.l2cache.demand_miss_rate::total 0.175871 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088095 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.175900 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088149 # miss rate for overall accesses
699,710c699,710
< system.cpu.l2cache.overall_miss_rate::total 0.175871 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75265.483494 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78229.814815 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 76103.917871 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76278.819201 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76278.819201 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76169.365412 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.175900 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75132.589025 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77410 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75776.329564 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76098.020322 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76098.020322 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75896.657929 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75896.657929 # average overall miss latency
728c728
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3424 # number of ReadReq MSHR misses
730c730
< system.cpu.l2cache.ReadReq_mshr_misses::total 4729 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 4732 # number of ReadReq MSHR misses
733c733
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses
735,736c735,736
< system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses
738,750c738,750
< system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214398750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85427750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 299826500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181482250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181482250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214398750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266910000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 481308750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214398750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266910000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 481308750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for ReadReq accesses
752c752
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116819 # mshr miss rate for ReadReq accesses
755c755
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for demand accesses
757,758c757,758
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.174885 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for overall accesses
760,771c760,771
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.174885 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency
773,774c773,774
< system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 40507 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 40506 # Transaction distribution
778c778
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77731 # Packet count per connected master and slave (bytes)
780,781c780,781
< system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 87763 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487360 # Cumulative packet size per connected master and slave (bytes)
783c783
< system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 2840704 # Cumulative packet size per connected master and slave (bytes)
785c785
< system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 44387 # Request fanout histogram
790c790
< system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 44387 100.00% 100.00% # Request fanout histogram
795,796c795,796
< system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 44387 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 23203500 # Layer occupancy (ticks)
798c798
< system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 59023248 # Layer occupancy (ticks)
800c800
< system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 7574708 # Layer occupancy (ticks)
802,803c802,803
< system.membus.trans_dist::ReadReq 4729 # Transaction distribution
< system.membus.trans_dist::ReadResp 4729 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 4732 # Transaction distribution
> system.membus.trans_dist::ReadResp 4732 # Transaction distribution
806,809c806,809
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes)
811c811
< system.membus.snoop_fanout::samples 7583 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 7586 # Request fanout histogram
815c815
< system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram
820,821c820,821
< system.membus.snoop_fanout::total 7583 # Request fanout histogram
< system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 7586 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8848500 # Layer occupancy (ticks)
823c823
< system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40266750 # Layer occupancy (ticks)