3,5c3,5
< sim_seconds 0.216828 # Number of seconds simulated
< sim_ticks 216828260500 # Number of ticks simulated
< final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.216865 # Number of seconds simulated
> sim_ticks 216864820000 # Number of ticks simulated
> final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 113548 # Simulator instruction rate (inst/s)
< host_op_rate 136327 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 90171945 # Simulator tick rate (ticks/s)
< host_mem_usage 309844 # Number of bytes of host memory used
< host_seconds 2404.61 # Real time elapsed on the host
---
> host_inst_rate 175540 # Simulator instruction rate (inst/s)
> host_op_rate 210755 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 139425507 # Simulator tick rate (ticks/s)
> host_mem_usage 321524 # Number of bytes of host memory used
> host_seconds 1555.42 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 485440 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 485376 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7585 # Number of read requests accepted
---
> system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7584 # Number of read requests accepted
34c34
< system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side
56c56
< system.physmem.perBankRdBursts::12 554 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 553 # Per bank write bursts
78c78
< system.physmem.totGap 216828031000 # Total gap between requests
---
> system.physmem.totGap 216864583500 # Total gap between requests
85c85
< system.physmem.readPktSize::6 7585 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7584 # Read request sizes (log2)
93,95c93,95
< system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation
< system.physmem.totQLat 50845500 # Total ticks spent queuing
< system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
> system.physmem.totQLat 53728750 # Total ticks spent queuing
> system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst
219c219
< system.physmem.readRowHits 6073 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6056 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 28586424.65 # Average gap between requests
< system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 28595013.65 # Average gap between requests
> system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.690273 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states
---
> system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.698913 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.748242 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states
---
> system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.797614 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 33221230 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits
---
> system.cpu.branchPred.lookups 33219592 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 433656521 # number of cpu cycles simulated
---
> system.cpu.numCycles 433729640 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.588265 # CPI: cycles per instruction
< system.cpu.ipc 0.629618 # IPC: instructions per cycle
< system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.588533 # CPI: cycles per instruction
> system.cpu.ipc 0.629512 # IPC: instructions per cycle
> system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
407,412c407,412
< system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits
417,438c417,438
< system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits
< system.cpu.dcache.overall_hits::total 168762017 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses
< system.cpu.dcache.overall_misses::total 7290 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits
> system.cpu.dcache.overall_hits::total 168760435 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses
> system.cpu.dcache.overall_misses::total 7280 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses)
445,448c445,448
< system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses
457,464c457,464
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency
475,482c475,482
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits
491,498c491,498
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles
507,514c507,514
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
516,520c516,520
< system.cpu.icache.tags.replacements 36927 # number of replacements
< system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 36897 # number of replacements
> system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks.
522,524c522,524
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy
526,527c526,527
< system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
532,557c532,557
< system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits
< system.cpu.icache.overall_hits::total 73270394 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses
< system.cpu.icache.overall_misses::total 38865 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits
> system.cpu.icache.overall_hits::total 73252005 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses
> system.cpu.icache.overall_misses::total 38835 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses
564,569c564,569
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency
578,589c578,589
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 38835 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 38835 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles
596,601c596,601
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
604,607c604,607
< system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks.
609,618c609,618
< system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.451697 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 678.347263 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096632 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.020702 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.128088 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 5646 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
621,625c621,625
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 35439 # number of ReadReq hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172302 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 363364 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 363364 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 35411 # number of ReadReq hits
627c627
< system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 35702 # number of ReadReq hits
632c632
< system.cpu.l2cache.demand_hits::cpu.inst 35439 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 35411 # number of demand (read+write) hits
634,635c634,635
< system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 35439 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 35718 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 35411 # number of overall hits
637,638c637,638
< system.cpu.l2cache.overall_hits::total 35746 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 35718 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3424 # number of ReadReq misses
640c640
< system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 4774 # number of ReadReq misses
643c643
< system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 3424 # number of demand (read+write) misses
645,646c645,646
< system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 7628 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses
648,660c648,660
< system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 230834250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95696250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 194789750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 230834250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 290486000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 230834250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 290486000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 38865 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 7628 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses)
662c662
< system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses)
667c667
< system.cpu.l2cache.demand_accesses::cpu.inst 38865 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 38835 # number of demand (read+write) accesses
669,670c669,670
< system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 38865 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 43346 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 38835 # number of overall (read+write) accesses
672,673c672,673
< system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088151 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 43346 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088168 # miss rate for ReadReq accesses
675c675
< system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.117946 # miss rate for ReadReq accesses
678c678
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088151 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088168 # miss rate for demand accesses
680,681c680,681
< system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088151 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.175979 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses
683,694c683,694
< system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67377.189142 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70886.111111 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68251.489138 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency
703c703
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
705,706c705,706
< system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
708,709c708,709
< system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
711,712c711,712
< system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3423 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3422 # number of ReadReq MSHR misses
714c714
< system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses
717c717
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3422 # number of demand (read+write) MSHR misses
719,720c719,720
< system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses
722,734c722,734
< system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses
736c736
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses
739c739
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses
741,742c741,742
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses
744,755c744,755
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
757,758c757,758
< system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution
762c762
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes)
764,765c764,765
< system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes)
767c767
< system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes)
769,770c769,770
< system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
776,779c776,777
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
781,784c779,782
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks)
786c784
< system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks)
788c786
< system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks)
790,791c788,789
< system.membus.trans_dist::ReadReq 4731 # Transaction distribution
< system.membus.trans_dist::ReadResp 4731 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 4730 # Transaction distribution
> system.membus.trans_dist::ReadResp 4730 # Transaction distribution
794,797c792,795
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes)
799c797
< system.membus.snoop_fanout::samples 7585 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 7584 # Request fanout histogram
803c801
< system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram
808,809c806,807
< system.membus.snoop_fanout::total 7585 # Request fanout histogram
< system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 7584 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks)
811c809
< system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks)
< sim_seconds 0.216828 # Number of seconds simulated
< sim_ticks 216828260500 # Number of ticks simulated
< final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.216865 # Number of seconds simulated
> sim_ticks 216864820000 # Number of ticks simulated
> final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 113548 # Simulator instruction rate (inst/s)
< host_op_rate 136327 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 90171945 # Simulator tick rate (ticks/s)
< host_mem_usage 309844 # Number of bytes of host memory used
< host_seconds 2404.61 # Real time elapsed on the host
---
> host_inst_rate 175540 # Simulator instruction rate (inst/s)
> host_op_rate 210755 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 139425507 # Simulator tick rate (ticks/s)
> host_mem_usage 321524 # Number of bytes of host memory used
> host_seconds 1555.42 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 485440 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 485376 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7585 # Number of read requests accepted
---
> system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7584 # Number of read requests accepted
34c34
< system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side
56c56
< system.physmem.perBankRdBursts::12 554 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 553 # Per bank write bursts
78c78
< system.physmem.totGap 216828031000 # Total gap between requests
---
> system.physmem.totGap 216864583500 # Total gap between requests
85c85
< system.physmem.readPktSize::6 7585 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7584 # Read request sizes (log2)
93,95c93,95
< system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation
< system.physmem.totQLat 50845500 # Total ticks spent queuing
< system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
> system.physmem.totQLat 53728750 # Total ticks spent queuing
> system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst
219c219
< system.physmem.readRowHits 6073 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6056 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 28586424.65 # Average gap between requests
< system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 28595013.65 # Average gap between requests
> system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.690273 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states
---
> system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.698913 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.748242 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states
---
> system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.797614 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 33221230 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits
---
> system.cpu.branchPred.lookups 33219592 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 433656521 # number of cpu cycles simulated
---
> system.cpu.numCycles 433729640 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.588265 # CPI: cycles per instruction
< system.cpu.ipc 0.629618 # IPC: instructions per cycle
< system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.588533 # CPI: cycles per instruction
> system.cpu.ipc 0.629512 # IPC: instructions per cycle
> system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
407,412c407,412
< system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits
417,438c417,438
< system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits
< system.cpu.dcache.overall_hits::total 168762017 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses
< system.cpu.dcache.overall_misses::total 7290 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits
> system.cpu.dcache.overall_hits::total 168760435 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses
> system.cpu.dcache.overall_misses::total 7280 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses)
445,448c445,448
< system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses
457,464c457,464
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency
475,482c475,482
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits
491,498c491,498
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles
507,514c507,514
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
516,520c516,520
< system.cpu.icache.tags.replacements 36927 # number of replacements
< system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 36897 # number of replacements
> system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks.
522,524c522,524
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy
526,527c526,527
< system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
532,557c532,557
< system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits
< system.cpu.icache.overall_hits::total 73270394 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses
< system.cpu.icache.overall_misses::total 38865 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits
> system.cpu.icache.overall_hits::total 73252005 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses
> system.cpu.icache.overall_misses::total 38835 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses
564,569c564,569
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency
578,589c578,589
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 38835 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 38835 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles
596,601c596,601
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
604,607c604,607
< system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks.
609,618c609,618
< system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.451697 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 678.347263 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096632 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.020702 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.128088 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 5646 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
621,625c621,625
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 35439 # number of ReadReq hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172302 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 363364 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 363364 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 35411 # number of ReadReq hits
627c627
< system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 35702 # number of ReadReq hits
632c632
< system.cpu.l2cache.demand_hits::cpu.inst 35439 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 35411 # number of demand (read+write) hits
634,635c634,635
< system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 35439 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 35718 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 35411 # number of overall hits
637,638c637,638
< system.cpu.l2cache.overall_hits::total 35746 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 35718 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3424 # number of ReadReq misses
640c640
< system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 4774 # number of ReadReq misses
643c643
< system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 3424 # number of demand (read+write) misses
645,646c645,646
< system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 7628 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses
648,660c648,660
< system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 230834250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95696250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 194789750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 230834250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 290486000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 230834250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 290486000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 38865 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 7628 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses)
662c662
< system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses)
667c667
< system.cpu.l2cache.demand_accesses::cpu.inst 38865 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 38835 # number of demand (read+write) accesses
669,670c669,670
< system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 38865 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 43346 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 38835 # number of overall (read+write) accesses
672,673c672,673
< system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088151 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 43346 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088168 # miss rate for ReadReq accesses
675c675
< system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.117946 # miss rate for ReadReq accesses
678c678
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088151 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088168 # miss rate for demand accesses
680,681c680,681
< system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088151 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.175979 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses
683,694c683,694
< system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67377.189142 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70886.111111 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68251.489138 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency
703c703
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
705,706c705,706
< system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
708,709c708,709
< system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
711,712c711,712
< system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3423 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3422 # number of ReadReq MSHR misses
714c714
< system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses
717c717
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3422 # number of demand (read+write) MSHR misses
719,720c719,720
< system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses
722,734c722,734
< system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses
736c736
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses
739c739
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses
741,742c741,742
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses
744,755c744,755
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
757,758c757,758
< system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution
762c762
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes)
764,765c764,765
< system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes)
767c767
< system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes)
769,770c769,770
< system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
776,779c776,777
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
781,784c779,782
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks)
786c784
< system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks)
788c786
< system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks)
790,791c788,789
< system.membus.trans_dist::ReadReq 4731 # Transaction distribution
< system.membus.trans_dist::ReadResp 4731 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 4730 # Transaction distribution
> system.membus.trans_dist::ReadResp 4730 # Transaction distribution
794,797c792,795
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes)
799c797
< system.membus.snoop_fanout::samples 7585 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 7584 # Request fanout histogram
803c801
< system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram
808,809c806,807
< system.membus.snoop_fanout::total 7585 # Request fanout histogram
< system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 7584 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks)
811c809
< system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks)