3,5c3,5
< sim_seconds 0.212377 # Number of seconds simulated
< sim_ticks 212377413000 # Number of ticks simulated
< final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.216828 # Number of seconds simulated
> sim_ticks 216828260500 # Number of ticks simulated
> final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 195363 # Simulator instruction rate (inst/s)
< host_op_rate 234555 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 151959329 # Simulator tick rate (ticks/s)
< host_mem_usage 264884 # Number of bytes of host memory used
< host_seconds 1397.59 # Real time elapsed on the host
---
> host_inst_rate 172164 # Simulator instruction rate (inst/s)
> host_op_rate 206702 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 136721287 # Simulator tick rate (ticks/s)
> host_mem_usage 262128 # Number of bytes of host memory used
> host_seconds 1585.91 # Real time elapsed on the host
16,28c16,28
< system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory
< system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 7583 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 485440 # Number of bytes read from this memory
> system.physmem.bytes_read::total 485440 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 7585 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2238823 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2238823 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 7585 # Number of read requests accepted
30c30
< system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue
32c32
< system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM
35c35
< system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side
46c46
< system.physmem.perBankRdBursts::6 173 # Per bank write bursts
---
> system.physmem.perBankRdBursts::6 172 # Per bank write bursts
49c49
< system.physmem.perBankRdBursts::9 310 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 311 # Per bank write bursts
53c53
< system.physmem.perBankRdBursts::13 705 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 706 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::15 540 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 541 # Per bank write bursts
74c74
< system.physmem.totGap 212377186000 # Total gap between requests
---
> system.physmem.totGap 216828031000 # Total gap between requests
81c81
< system.physmem.readPktSize::6 7583 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 7585 # Read request sizes (log2)
89,90c89,90
< system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see
185,202c185,202
< system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation
< system.physmem.totQLat 52768250 # Total ticks spent queuing
< system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 189.317321 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 333.826076 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 548 36.41% 36.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 349 23.19% 59.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 163 10.83% 70.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 69 4.58% 79.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 60 3.99% 83.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 33 2.19% 85.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation
> system.physmem.totQLat 50683250 # Total ticks spent queuing
> system.physmem.totMemAccLat 192902000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 6682.04 # Average queueing delay per DRAM burst
204,205c204,205
< system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 25432.04 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
207c207
< system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
215c215
< system.physmem.readRowHits 6077 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 6073 # Number of row buffer hits during reads
217c217
< system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads
219,222c219,222
< system.physmem.avgGap 28007013.85 # Average gap between requests
< system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states
< system.physmem.memoryStateTime::REF 7091500000 # Time in different power states
---
> system.physmem.avgGap 28586424.65 # Average gap between requests
> system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 207228229000 # Time in different power states
> system.physmem.memoryStateTime::REF 7240220000 # Time in different power states
224c224
< system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 2356912000 # Time in different power states
226,231c226,231
< system.physmem.actEnergy::0 4921560 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 6380640 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 2685375 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 3481500 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 29897400 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 28977000 # Energy for read commands per rank (pJ)
---
> system.physmem.actEnergy::0 5012280 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 6342840 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 2734875 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 3460875 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 29905200 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 29000400 # Energy for read commands per rank (pJ)
234,272c234,248
< system.physmem.refreshEnergy::0 13870974000 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 13870974000 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 5549858010 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 5731608780 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 122553840750 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 122394410250 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 142012177095 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 142035832170 # Total energy per rank (pJ)
< system.physmem.averagePower::0 668.700966 # Core power per rank (mW)
< system.physmem.averagePower::1 668.812352 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 4730 # Transaction distribution
< system.membus.trans_dist::ReadResp 4730 # Transaction distribution
< system.membus.trans_dist::ReadExReq 2853 # Transaction distribution
< system.membus.trans_dist::ReadExResp 2853 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 7583 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 7583 # Request fanout histogram
< system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 33146132 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits
---
> system.physmem.refreshEnergy::0 14161870320 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 14161870320 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 5651949285 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 5745162240 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 125136528000 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 125054762250 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 144987999960 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 145000598925 # Total energy per rank (pJ)
> system.physmem.averagePower::0 668.689925 # Core power per rank (mW)
> system.physmem.averagePower::1 668.748031 # Core power per rank (mW)
> system.cpu.branchPred.lookups 33221230 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits
274,275c250,251
< system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target.
276a253
> system.cpu_clk_domain.clock 500 # Clock period in ticks
362c339
< system.cpu.numCycles 424754826 # number of cpu cycles simulated
---
> system.cpu.numCycles 433656521 # number of cpu cycles simulated
367c344
< system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit
369,616c346,354
< system.cpu.cpi 1.555663 # CPI: cycles per instruction
< system.cpu.ipc 0.642813 # IPC: instructions per cycle
< system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
< system.cpu.icache.tags.replacements 36952 # number of replacements
< system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
< system.cpu.icache.overall_hits::total 73208046 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses
< system.cpu.icache.overall_misses::total 38890 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.cpu.l2cache.tags.replacements 0 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits
< system.cpu.l2cache.overall_hits::total 35774 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses
< system.cpu.l2cache.overall_misses::total 7626 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.dcache.tags.replacements 1353 # number of replacements
< system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks.
---
> system.cpu.cpi 1.588265 # CPI: cycles per instruction
> system.cpu.ipc 0.629618 # IPC: instructions per cycle
> system.cpu.tickCycles 430211091 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 3445430 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 1354 # number of replacements
> system.cpu.dcache.tags.tagsinuse 3086.009332 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks.
618,620c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009332 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy
622,623c360,361
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
625,626c363,364
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
628,633c366,371
< system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 86714567 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 82047450 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits
638,659c376,397
< system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits
< system.cpu.dcache.overall_hits::total 168752750 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses
< system.cpu.dcache.overall_misses::total 7291 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.inst 168762017 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 168762017 # number of overall hits
> system.cpu.dcache.overall_hits::total 168762017 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 5227 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.inst 7290 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses
> system.cpu.dcache.overall_misses::total 7290 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126122956 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 126122956 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360338500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 360338500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 486461456 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 486461456 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 486461456 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 486461456 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses)
666,669c404,407
< system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.inst 168769307 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 168769307 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses
678,685c416,423
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66729.966529 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66729.966529 # average overall miss latency
694,697c432,435
< system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks
< system.cpu.dcache.writebacks::total 1009 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
> system.cpu.dcache.writebacks::total 1010 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 422 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
700,703c438,441
< system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.inst 2779 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 2779 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits
706,719c444,457
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2870 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 99847542 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 99847542 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197786250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 197786250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297633792 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 297633792 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297633792 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 297633792 # number of overall MSHR miss cycles
728,735c466,473
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency
736a475,736
> system.cpu.icache.tags.replacements 36927 # number of replacements
> system.cpu.icache.tags.tagsinuse 1924.993605 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 73270396 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1885.302491 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993605 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 146657386 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146657386 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 73270396 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 73270396 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 73270396 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 73270396 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 73270396 # number of overall hits
> system.cpu.icache.overall_hits::total 73270396 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses
> system.cpu.icache.overall_misses::total 38865 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 703294747 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 703294747 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 703294747 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 703294747 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 703294747 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 703294747 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 73309261 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 73309261 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 73309261 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 73309261 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 73309261 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 73309261 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18095.838081 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18095.838081 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.icache.fast_writes 0 # number of fast writes performed
> system.cpu.icache.cache_copies 0 # number of cache copies performed
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624165253 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 624165253 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624165253 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 624165253 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624165253 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 624165253 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency
> system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.l2cache.tags.replacements 0 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 4198.559652 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 353.760812 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798840 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 35730 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 35746 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 35746 # number of overall hits
> system.cpu.l2cache.overall_hits::total 35746 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 4776 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 2854 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 7630 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses
> system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326194750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 326194750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194720750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 194720750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 520915500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 520915500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 520915500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 520915500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2870 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 43376 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 43376 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117908 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994425 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 45 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 45 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 45 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4731 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2854 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264387500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264387500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158755250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158755250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423142750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 423142750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423142750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 423142750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 7500208 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
> system.membus.trans_dist::ReadReq 4731 # Transaction distribution
> system.membus.trans_dist::ReadResp 4731 # Transaction distribution
> system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
> system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 7585 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 7585 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8963500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer1.occupancy 71030250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.0 # Layer utilization (%)