7,11c7,11
< host_inst_rate 166098 # Simulator instruction rate (inst/s)
< host_op_rate 199419 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 129195965 # Simulator tick rate (ticks/s)
< host_mem_usage 326468 # Number of bytes of host memory used
< host_seconds 1643.84 # Real time elapsed on the host
---
> host_inst_rate 164145 # Simulator instruction rate (inst/s)
> host_op_rate 197075 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 127677508 # Simulator tick rate (ticks/s)
> host_mem_usage 316656 # Number of bytes of host memory used
> host_seconds 1663.39 # Real time elapsed on the host
199,200c199,200
< system.physmem.totQLat 52122500 # Total ticks spent queuing
< system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 52768250 # Total ticks spent queuing
> system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
204c204
< system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
226d225
< system.membus.throughput 2285139 # Throughput (bytes/s)
233,237c232,245
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 485312 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 7583 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 7583 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
239c247
< system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
242c250
< system.cpu.branchPred.lookups 33146135 # Number of BP lookups
---
> system.cpu.branchPred.lookups 33146132 # Number of BP lookups
245c253
< system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
248c256
< system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
341c349
< system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
345,346c353,354
< system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
348,349c356,357
< system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
351c359
< system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
353c361
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
363,370c371,378
< system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits
< system.cpu.icache.overall_hits::total 73208047 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
> system.cpu.icache.overall_hits::total 73208046 # number of overall hits
377,388c385,396
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses
395,400c403,408
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency
415,420c423,428
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles
427,432c435,440
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
434d441
< system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s)
443,447c450,468
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram
450c471
< system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks)
452c473
< system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks)
455c476
< system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use
460,461c481,482
< system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor
492,499c513,520
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles
518,525c539,546
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency
548,555c569,576
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles
564,571c585,592
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
574c595
< system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use
579c600
< system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor
611,618c632,639
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
639,646c660,667
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
673,680c694,701
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
689,696c710,717
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
< host_inst_rate 166098 # Simulator instruction rate (inst/s)
< host_op_rate 199419 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 129195965 # Simulator tick rate (ticks/s)
< host_mem_usage 326468 # Number of bytes of host memory used
< host_seconds 1643.84 # Real time elapsed on the host
---
> host_inst_rate 164145 # Simulator instruction rate (inst/s)
> host_op_rate 197075 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 127677508 # Simulator tick rate (ticks/s)
> host_mem_usage 316656 # Number of bytes of host memory used
> host_seconds 1663.39 # Real time elapsed on the host
199,200c199,200
< system.physmem.totQLat 52122500 # Total ticks spent queuing
< system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 52768250 # Total ticks spent queuing
> system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
204c204
< system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
226d225
< system.membus.throughput 2285139 # Throughput (bytes/s)
233,237c232,245
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 485312 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 7583 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 7583 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
239c247
< system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
242c250
< system.cpu.branchPred.lookups 33146135 # Number of BP lookups
---
> system.cpu.branchPred.lookups 33146132 # Number of BP lookups
245c253
< system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
248c256
< system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
341c349
< system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
345,346c353,354
< system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
348,349c356,357
< system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
351c359
< system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
353c361
< system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
363,370c371,378
< system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits
< system.cpu.icache.overall_hits::total 73208047 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
> system.cpu.icache.overall_hits::total 73208046 # number of overall hits
377,388c385,396
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses
395,400c403,408
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency
415,420c423,428
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles
427,432c435,440
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
434d441
< system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s)
443,447c450,468
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram
450c471
< system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks)
452c473
< system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks)
455c476
< system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use
460,461c481,482
< system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor
492,499c513,520
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles
518,525c539,546
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency
548,555c569,576
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles
564,571c585,592
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
574c595
< system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use
579c600
< system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor
611,618c632,639
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
639,646c660,667
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
673,680c694,701
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
689,696c710,717
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency