1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.212377 # Number of seconds simulated
4sim_ticks 212377413000 # Number of ticks simulated
5final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 195363 # Simulator instruction rate (inst/s)
8host_op_rate 234555 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 151959329 # Simulator tick rate (ticks/s)
10host_mem_usage 264884 # Number of bytes of host memory used
11host_seconds 1397.59 # Real time elapsed on the host
12sim_insts 273037856 # Number of instructions simulated
13sim_ops 327812213 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory
17system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 7583 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 630 # Per bank write bursts
41system.physmem.perBankRdBursts::1 843 # Per bank write bursts
42system.physmem.perBankRdBursts::2 628 # Per bank write bursts
43system.physmem.perBankRdBursts::3 541 # Per bank write bursts
44system.physmem.perBankRdBursts::4 466 # Per bank write bursts
45system.physmem.perBankRdBursts::5 349 # Per bank write bursts
46system.physmem.perBankRdBursts::6 173 # Per bank write bursts
47system.physmem.perBankRdBursts::7 228 # Per bank write bursts
48system.physmem.perBankRdBursts::8 209 # Per bank write bursts
49system.physmem.perBankRdBursts::9 310 # Per bank write bursts
50system.physmem.perBankRdBursts::10 342 # Per bank write bursts
51system.physmem.perBankRdBursts::11 428 # Per bank write bursts
52system.physmem.perBankRdBursts::12 554 # Per bank write bursts
53system.physmem.perBankRdBursts::13 705 # Per bank write bursts
54system.physmem.perBankRdBursts::14 637 # Per bank write bursts
55system.physmem.perBankRdBursts::15 540 # Per bank write bursts
56system.physmem.perBankWrBursts::0 0 # Per bank write bursts
57system.physmem.perBankWrBursts::1 0 # Per bank write bursts
58system.physmem.perBankWrBursts::2 0 # Per bank write bursts
59system.physmem.perBankWrBursts::3 0 # Per bank write bursts
60system.physmem.perBankWrBursts::4 0 # Per bank write bursts
61system.physmem.perBankWrBursts::5 0 # Per bank write bursts
62system.physmem.perBankWrBursts::6 0 # Per bank write bursts
63system.physmem.perBankWrBursts::7 0 # Per bank write bursts
64system.physmem.perBankWrBursts::8 0 # Per bank write bursts
65system.physmem.perBankWrBursts::9 0 # Per bank write bursts
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 212377186000 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 7583 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 78 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation
199system.physmem.totQLat 52768250 # Total ticks spent queuing
200system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
201system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
202system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
204system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
205system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
207system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
210system.physmem.busUtil 0.02 # Data bus utilization in percentage
211system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
213system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
215system.physmem.readRowHits 6077 # Number of row buffer hits during reads
216system.physmem.writeRowHits 0 # Number of row buffer hits during writes
217system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads
218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
219system.physmem.avgGap 28007013.85 # Average gap between requests
220system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
221system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states
222system.physmem.memoryStateTime::REF 7091500000 # Time in different power states
223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
224system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states
225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
226system.physmem.actEnergy::0 4921560 # Energy for activate commands per rank (pJ)
227system.physmem.actEnergy::1 6380640 # Energy for activate commands per rank (pJ)
228system.physmem.preEnergy::0 2685375 # Energy for precharge commands per rank (pJ)
229system.physmem.preEnergy::1 3481500 # Energy for precharge commands per rank (pJ)
230system.physmem.readEnergy::0 29897400 # Energy for read commands per rank (pJ)
231system.physmem.readEnergy::1 28977000 # Energy for read commands per rank (pJ)
232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
234system.physmem.refreshEnergy::0 13870974000 # Energy for refresh commands per rank (pJ)
235system.physmem.refreshEnergy::1 13870974000 # Energy for refresh commands per rank (pJ)
236system.physmem.actBackEnergy::0 5549858010 # Energy for active background per rank (pJ)
237system.physmem.actBackEnergy::1 5731608780 # Energy for active background per rank (pJ)
238system.physmem.preBackEnergy::0 122553840750 # Energy for precharge background per rank (pJ)
239system.physmem.preBackEnergy::1 122394410250 # Energy for precharge background per rank (pJ)
240system.physmem.totalEnergy::0 142012177095 # Total energy per rank (pJ)
241system.physmem.totalEnergy::1 142035832170 # Total energy per rank (pJ)
242system.physmem.averagePower::0 668.700966 # Core power per rank (mW)
243system.physmem.averagePower::1 668.812352 # Core power per rank (mW)
244system.membus.trans_dist::ReadReq 4730 # Transaction distribution
245system.membus.trans_dist::ReadResp 4730 # Transaction distribution
246system.membus.trans_dist::ReadExReq 2853 # Transaction distribution
247system.membus.trans_dist::ReadExResp 2853 # Transaction distribution
248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
249system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
250system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
251system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
252system.membus.snoops 0 # Total snoops (count)
253system.membus.snoop_fanout::samples 7583 # Request fanout histogram
254system.membus.snoop_fanout::mean 0 # Request fanout histogram
255system.membus.snoop_fanout::stdev 0 # Request fanout histogram
256system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
257system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
258system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
259system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
260system.membus.snoop_fanout::min_value 0 # Request fanout histogram
261system.membus.snoop_fanout::max_value 0 # Request fanout histogram
262system.membus.snoop_fanout::total 7583 # Request fanout histogram
263system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
264system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
265system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
266system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
267system.cpu_clk_domain.clock 500 # Clock period in ticks
268system.cpu.branchPred.lookups 33146132 # Number of BP lookups
269system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted
270system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect
271system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
272system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits
273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
274system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
275system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target.
276system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355system.cpu.itb.read_accesses 0 # DTB read accesses
356system.cpu.itb.write_accesses 0 # DTB write accesses
357system.cpu.itb.inst_accesses 0 # ITB inst accesses
358system.cpu.itb.hits 0 # DTB hits
359system.cpu.itb.misses 0 # DTB misses
360system.cpu.itb.accesses 0 # DTB accesses
361system.cpu.workload.num_syscalls 191 # Number of system calls
362system.cpu.numCycles 424754826 # number of cpu cycles simulated
363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
365system.cpu.committedInsts 273037856 # Number of instructions committed
366system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
367system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
369system.cpu.cpi 1.555663 # CPI: cycles per instruction
370system.cpu.ipc 0.642813 # IPC: instructions per cycle
371system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
372system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
373system.cpu.icache.tags.replacements 36952 # number of replacements
374system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
375system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
376system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks.
377system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
378system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
379system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
380system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy
381system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy
382system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
383system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
384system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
385system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
386system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
387system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id
388system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
389system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
390system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
391system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
392system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
393system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
394system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
395system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
396system.cpu.icache.overall_hits::total 73208046 # number of overall hits
397system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses
398system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses
399system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses
400system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses
401system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses
402system.cpu.icache.overall_misses::total 38890 # number of overall misses
403system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles
404system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles
405system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles
406system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles
407system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles
408system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles
409system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses)
410system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses)
411system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses
412system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses
413system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses
414system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses
415system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses
416system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses
417system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses
418system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses
419system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses
420system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses
421system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency
422system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency
423system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
424system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency
425system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
426system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency
427system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
428system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
429system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
430system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
431system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
432system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
433system.cpu.icache.fast_writes 0 # number of fast writes performed
434system.cpu.icache.cache_copies 0 # number of cache copies performed
435system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses
436system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses
437system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses
438system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses
439system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses
440system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses
441system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles
442system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles
443system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles
444system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles
445system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles
446system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles
447system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses
448system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses
449system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses
450system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses
451system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses
452system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses
453system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency
454system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency
455system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
456system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
457system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
458system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
459system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
460system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution
463system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution
464system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution
465system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes)
467system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes)
468system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
470system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
471system.cpu.toL2Bus.snoops 0 # Total snoops (count)
472system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram
487system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks)
488system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
489system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks)
490system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
491system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks)
492system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
493system.cpu.l2cache.tags.replacements 0 # number of replacements
494system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use
495system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks.
496system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks.
497system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks.
498system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
499system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor
500system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor
501system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy
502system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy
503system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy
504system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id
505system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
506system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
507system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
508system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
509system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
510system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id
511system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses
512system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses
513system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits
514system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits
515system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits
516system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits
517system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits
518system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
519system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits
520system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits
521system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits
522system.cpu.l2cache.overall_hits::total 35774 # number of overall hits
523system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses
524system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses
525system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses
526system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses
527system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses
528system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses
529system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses
530system.cpu.l2cache.overall_misses::total 7626 # number of overall misses
531system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles
532system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles
533system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles
534system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles
535system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles
536system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles
537system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles
538system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles
539system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses)
540system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses)
541system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses)
542system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses)
543system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses)
544system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses)
545system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses
546system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses
547system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses
548system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses
549system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses
550system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses
551system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses
552system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses
553system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses
554system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses
555system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses
556system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses
557system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency
558system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency
559system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency
560system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency
561system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
562system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency
563system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
564system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency
565system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
566system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
567system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
568system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
569system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
570system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
571system.cpu.l2cache.fast_writes 0 # number of fast writes performed
572system.cpu.l2cache.cache_copies 0 # number of cache copies performed
573system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits
574system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits
575system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits
576system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits
577system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits
578system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits
579system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses
580system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses
581system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses
582system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses
583system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses
584system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
585system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses
586system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
587system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles
588system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles
589system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles
590system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles
591system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles
592system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles
593system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles
594system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles
595system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses
596system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses
597system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses
598system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses
599system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses
600system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses
601system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses
602system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses
603system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency
604system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency
605system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency
606system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency
607system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
608system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
610system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
611system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
612system.cpu.dcache.tags.replacements 1353 # number of replacements
613system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use
614system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks.
615system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks.
616system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks.
617system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
618system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor
619system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy
620system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy
621system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
622system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
623system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
624system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
625system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id
626system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id
627system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
628system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses
629system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses
630system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits
631system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits
632system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits
633system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
634system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits
635system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
636system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits
637system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
638system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits
639system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits
640system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits
641system.cpu.dcache.overall_hits::total 168752750 # number of overall hits
642system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses
643system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses
644system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses
645system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
646system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses
647system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses
648system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses
649system.cpu.dcache.overall_misses::total 7291 # number of overall misses
650system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles
651system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles
652system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles
653system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles
654system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
655system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
656system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
657system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
658system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses)
659system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses)
660system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses)
661system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
662system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses)
663system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
664system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses)
665system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
666system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses
667system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses
668system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses
669system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses
670system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses
671system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
672system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses
673system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
674system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses
675system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
676system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
677system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
678system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
679system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
680system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
681system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
682system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
683system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
684system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
685system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
686system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
687system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
688system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
689system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
690system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
691system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
692system.cpu.dcache.fast_writes 0 # number of fast writes performed
693system.cpu.dcache.cache_copies 0 # number of cache copies performed
694system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks
695system.cpu.dcache.writebacks::total 1009 # number of writebacks
696system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits
697system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits
698system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits
699system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits
700system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits
701system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits
702system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits
703system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits
704system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses
705system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses
706system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses
707system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses
708system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses
709system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses
710system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses
711system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses
712system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
713system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
714system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
715system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
716system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
717system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
718system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
719system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
720system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses
721system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
722system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses
723system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
724system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
725system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
726system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
727system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
728system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
729system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
730system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
731system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
732system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
733system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
734system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
735system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
736system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
737
738---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.212377 # Number of seconds simulated
4sim_ticks 212377413000 # Number of ticks simulated
5final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 195363 # Simulator instruction rate (inst/s)
8host_op_rate 234555 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 151959329 # Simulator tick rate (ticks/s)
10host_mem_usage 264884 # Number of bytes of host memory used
11host_seconds 1397.59 # Real time elapsed on the host
12sim_insts 273037856 # Number of instructions simulated
13sim_ops 327812213 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory
17system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 7583 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 630 # Per bank write bursts
41system.physmem.perBankRdBursts::1 843 # Per bank write bursts
42system.physmem.perBankRdBursts::2 628 # Per bank write bursts
43system.physmem.perBankRdBursts::3 541 # Per bank write bursts
44system.physmem.perBankRdBursts::4 466 # Per bank write bursts
45system.physmem.perBankRdBursts::5 349 # Per bank write bursts
46system.physmem.perBankRdBursts::6 173 # Per bank write bursts
47system.physmem.perBankRdBursts::7 228 # Per bank write bursts
48system.physmem.perBankRdBursts::8 209 # Per bank write bursts
49system.physmem.perBankRdBursts::9 310 # Per bank write bursts
50system.physmem.perBankRdBursts::10 342 # Per bank write bursts
51system.physmem.perBankRdBursts::11 428 # Per bank write bursts
52system.physmem.perBankRdBursts::12 554 # Per bank write bursts
53system.physmem.perBankRdBursts::13 705 # Per bank write bursts
54system.physmem.perBankRdBursts::14 637 # Per bank write bursts
55system.physmem.perBankRdBursts::15 540 # Per bank write bursts
56system.physmem.perBankWrBursts::0 0 # Per bank write bursts
57system.physmem.perBankWrBursts::1 0 # Per bank write bursts
58system.physmem.perBankWrBursts::2 0 # Per bank write bursts
59system.physmem.perBankWrBursts::3 0 # Per bank write bursts
60system.physmem.perBankWrBursts::4 0 # Per bank write bursts
61system.physmem.perBankWrBursts::5 0 # Per bank write bursts
62system.physmem.perBankWrBursts::6 0 # Per bank write bursts
63system.physmem.perBankWrBursts::7 0 # Per bank write bursts
64system.physmem.perBankWrBursts::8 0 # Per bank write bursts
65system.physmem.perBankWrBursts::9 0 # Per bank write bursts
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 212377186000 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 7583 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 78 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation
199system.physmem.totQLat 52768250 # Total ticks spent queuing
200system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
201system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
202system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
204system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
205system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
207system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
210system.physmem.busUtil 0.02 # Data bus utilization in percentage
211system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
213system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
215system.physmem.readRowHits 6077 # Number of row buffer hits during reads
216system.physmem.writeRowHits 0 # Number of row buffer hits during writes
217system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads
218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
219system.physmem.avgGap 28007013.85 # Average gap between requests
220system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
221system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states
222system.physmem.memoryStateTime::REF 7091500000 # Time in different power states
223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
224system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states
225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
226system.physmem.actEnergy::0 4921560 # Energy for activate commands per rank (pJ)
227system.physmem.actEnergy::1 6380640 # Energy for activate commands per rank (pJ)
228system.physmem.preEnergy::0 2685375 # Energy for precharge commands per rank (pJ)
229system.physmem.preEnergy::1 3481500 # Energy for precharge commands per rank (pJ)
230system.physmem.readEnergy::0 29897400 # Energy for read commands per rank (pJ)
231system.physmem.readEnergy::1 28977000 # Energy for read commands per rank (pJ)
232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
234system.physmem.refreshEnergy::0 13870974000 # Energy for refresh commands per rank (pJ)
235system.physmem.refreshEnergy::1 13870974000 # Energy for refresh commands per rank (pJ)
236system.physmem.actBackEnergy::0 5549858010 # Energy for active background per rank (pJ)
237system.physmem.actBackEnergy::1 5731608780 # Energy for active background per rank (pJ)
238system.physmem.preBackEnergy::0 122553840750 # Energy for precharge background per rank (pJ)
239system.physmem.preBackEnergy::1 122394410250 # Energy for precharge background per rank (pJ)
240system.physmem.totalEnergy::0 142012177095 # Total energy per rank (pJ)
241system.physmem.totalEnergy::1 142035832170 # Total energy per rank (pJ)
242system.physmem.averagePower::0 668.700966 # Core power per rank (mW)
243system.physmem.averagePower::1 668.812352 # Core power per rank (mW)
244system.membus.trans_dist::ReadReq 4730 # Transaction distribution
245system.membus.trans_dist::ReadResp 4730 # Transaction distribution
246system.membus.trans_dist::ReadExReq 2853 # Transaction distribution
247system.membus.trans_dist::ReadExResp 2853 # Transaction distribution
248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
249system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
250system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
251system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
252system.membus.snoops 0 # Total snoops (count)
253system.membus.snoop_fanout::samples 7583 # Request fanout histogram
254system.membus.snoop_fanout::mean 0 # Request fanout histogram
255system.membus.snoop_fanout::stdev 0 # Request fanout histogram
256system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
257system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
258system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
259system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
260system.membus.snoop_fanout::min_value 0 # Request fanout histogram
261system.membus.snoop_fanout::max_value 0 # Request fanout histogram
262system.membus.snoop_fanout::total 7583 # Request fanout histogram
263system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
264system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
265system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
266system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
267system.cpu_clk_domain.clock 500 # Clock period in ticks
268system.cpu.branchPred.lookups 33146132 # Number of BP lookups
269system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted
270system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect
271system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
272system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits
273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
274system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
275system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target.
276system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355system.cpu.itb.read_accesses 0 # DTB read accesses
356system.cpu.itb.write_accesses 0 # DTB write accesses
357system.cpu.itb.inst_accesses 0 # ITB inst accesses
358system.cpu.itb.hits 0 # DTB hits
359system.cpu.itb.misses 0 # DTB misses
360system.cpu.itb.accesses 0 # DTB accesses
361system.cpu.workload.num_syscalls 191 # Number of system calls
362system.cpu.numCycles 424754826 # number of cpu cycles simulated
363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
365system.cpu.committedInsts 273037856 # Number of instructions committed
366system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
367system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
369system.cpu.cpi 1.555663 # CPI: cycles per instruction
370system.cpu.ipc 0.642813 # IPC: instructions per cycle
371system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
372system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
373system.cpu.icache.tags.replacements 36952 # number of replacements
374system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
375system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
376system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks.
377system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
378system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
379system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
380system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy
381system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy
382system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
383system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
384system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
385system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
386system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
387system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id
388system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
389system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
390system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
391system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
392system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
393system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
394system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
395system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
396system.cpu.icache.overall_hits::total 73208046 # number of overall hits
397system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses
398system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses
399system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses
400system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses
401system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses
402system.cpu.icache.overall_misses::total 38890 # number of overall misses
403system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles
404system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles
405system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles
406system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles
407system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles
408system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles
409system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses)
410system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses)
411system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses
412system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses
413system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses
414system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses
415system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses
416system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses
417system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses
418system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses
419system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses
420system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses
421system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency
422system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency
423system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
424system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency
425system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
426system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency
427system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
428system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
429system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
430system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
431system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
432system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
433system.cpu.icache.fast_writes 0 # number of fast writes performed
434system.cpu.icache.cache_copies 0 # number of cache copies performed
435system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses
436system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses
437system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses
438system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses
439system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses
440system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses
441system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles
442system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles
443system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles
444system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles
445system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles
446system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles
447system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses
448system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses
449system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses
450system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses
451system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses
452system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses
453system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency
454system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency
455system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
456system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
457system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
458system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
459system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
460system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution
463system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution
464system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution
465system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes)
467system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes)
468system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
470system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
471system.cpu.toL2Bus.snoops 0 # Total snoops (count)
472system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram
487system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks)
488system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
489system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks)
490system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
491system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks)
492system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
493system.cpu.l2cache.tags.replacements 0 # number of replacements
494system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use
495system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks.
496system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks.
497system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks.
498system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
499system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor
500system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor
501system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy
502system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy
503system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy
504system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id
505system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
506system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
507system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
508system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
509system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
510system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id
511system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses
512system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses
513system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits
514system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits
515system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits
516system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits
517system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits
518system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
519system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits
520system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits
521system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits
522system.cpu.l2cache.overall_hits::total 35774 # number of overall hits
523system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses
524system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses
525system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses
526system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses
527system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses
528system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses
529system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses
530system.cpu.l2cache.overall_misses::total 7626 # number of overall misses
531system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles
532system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles
533system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles
534system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles
535system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles
536system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles
537system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles
538system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles
539system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses)
540system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses)
541system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses)
542system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses)
543system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses)
544system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses)
545system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses
546system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses
547system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses
548system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses
549system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses
550system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses
551system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses
552system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses
553system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses
554system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses
555system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses
556system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses
557system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency
558system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency
559system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency
560system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency
561system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
562system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency
563system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
564system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency
565system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
566system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
567system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
568system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
569system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
570system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
571system.cpu.l2cache.fast_writes 0 # number of fast writes performed
572system.cpu.l2cache.cache_copies 0 # number of cache copies performed
573system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits
574system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits
575system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits
576system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits
577system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits
578system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits
579system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses
580system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses
581system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses
582system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses
583system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses
584system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
585system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses
586system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
587system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles
588system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles
589system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles
590system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles
591system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles
592system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles
593system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles
594system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles
595system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses
596system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses
597system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses
598system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses
599system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses
600system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses
601system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses
602system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses
603system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency
604system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency
605system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency
606system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency
607system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
608system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
610system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
611system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
612system.cpu.dcache.tags.replacements 1353 # number of replacements
613system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use
614system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks.
615system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks.
616system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks.
617system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
618system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor
619system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy
620system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy
621system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
622system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
623system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
624system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
625system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id
626system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id
627system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
628system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses
629system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses
630system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits
631system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits
632system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits
633system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
634system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits
635system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
636system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits
637system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
638system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits
639system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits
640system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits
641system.cpu.dcache.overall_hits::total 168752750 # number of overall hits
642system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses
643system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses
644system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses
645system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
646system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses
647system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses
648system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses
649system.cpu.dcache.overall_misses::total 7291 # number of overall misses
650system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles
651system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles
652system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles
653system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles
654system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
655system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
656system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
657system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
658system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses)
659system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses)
660system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses)
661system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
662system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses)
663system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
664system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses)
665system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
666system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses
667system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses
668system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses
669system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses
670system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses
671system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
672system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses
673system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
674system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses
675system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
676system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
677system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
678system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
679system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
680system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
681system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
682system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
683system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
684system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
685system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
686system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
687system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
688system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
689system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
690system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
691system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
692system.cpu.dcache.fast_writes 0 # number of fast writes performed
693system.cpu.dcache.cache_copies 0 # number of cache copies performed
694system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks
695system.cpu.dcache.writebacks::total 1009 # number of writebacks
696system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits
697system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits
698system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits
699system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits
700system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits
701system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits
702system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits
703system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits
704system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses
705system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses
706system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses
707system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses
708system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses
709system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses
710system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses
711system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses
712system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
713system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
714system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
715system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
716system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
717system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
718system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
719system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
720system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses
721system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
722system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses
723system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
724system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
725system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
726system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
727system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
728system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
729system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
730system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
731system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
732system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
733system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
734system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
735system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
736system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
737
738---------- End Simulation Statistics ----------