| stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated 4sim_ticks 1647872849000 # Number of ticks simulated 5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 533286 # Simulator instruction rate (inst/s) 8host_op_rate 986105 # Simulator op (including micro ops) rate (op/s) --- 20 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated 4sim_ticks 1647872849000 # Number of ticks simulated 5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 533286 # Simulator instruction rate (inst/s) 8host_op_rate 986105 # Simulator op (including micro ops) rate (op/s) --- 20 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) |
| 37system.membus.throughput 26154600 # Throughput (bytes/s) 38system.membus.trans_dist::ReadReq 174452 # Transaction distribution 39system.membus.trans_dist::ReadResp 174452 # Transaction distribution 40system.membus.trans_dist::Writeback 292286 # Transaction distribution 41system.membus.trans_dist::ReadExReq 206691 # Transaction distribution 42system.membus.trans_dist::ReadExResp 206691 # Transaction distribution 43system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) 44system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) 49system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) 50system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) 51system.membus.data_through_bus 43099456 # Total data (bytes) 52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 53system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 55system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
|
| 37system.cpu.workload.num_syscalls 551 # Number of system calls 38system.cpu.numCycles 3295745698 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 826877110 # Number of instructions committed 42system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 323 unchanged lines hidden (view full) --- 368system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency 369system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency 370system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency 371system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 372system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 373system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 374system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 375system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 57system.cpu.workload.num_syscalls 551 # Number of system calls 58system.cpu.numCycles 3295745698 # number of cpu cycles simulated 59system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 60system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 61system.cpu.committedInsts 826877110 # Number of instructions committed 62system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed 63system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses 64system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 323 unchanged lines hidden (view full) --- 388system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency 389system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency 390system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency 391system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 392system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 393system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 394system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 395system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 396system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s) 397system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution 398system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution 399system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution 400system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution 401system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution 402system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes) 403system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes) 404system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes) 405system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes) 406system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes) 407system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes) 408system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes) 409system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 410system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) 411system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 412system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 413system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 414system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) 415system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
|
| 376 377---------- End Simulation Statistics ---------- | 416 417---------- End Simulation Statistics ---------- |