Cross Reference: /gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

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sdiff udiff text old ( 9322:01c8c5ff2c3b ) new ( 9373:26ba525347fe )

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stats.txt (9322:01c8c5ff2c3b)	stats.txt (9373:26ba525347fe)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated
4sim_ticks 1647872847000 # Number of ticks simulated 5final_tick 1647872847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)	4sim_ticks 1647872848000 # Number of ticks simulated 5final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks	6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 897428 # Simulator instruction rate (inst/s) 8host_op_rate 1659445 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1788472844 # Simulator tick rate (ticks/s) 10host_mem_usage 230968 # Number of bytes of host memory used 11host_seconds 921.39 # Real time elapsed on the host	7host_inst_rate 488671 # Simulator instruction rate (inst/s) 8host_op_rate 903607 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 973865405 # Simulator tick rate (ticks/s) 10host_mem_usage 280376 # Number of bytes of host memory used 11host_seconds 1692.10 # Real time elapsed on the host
12sim_insts 826877110 # Number of instructions simulated	12sim_insts 826877110 # Number of instructions simulated
13sim_ops 1528988700 # Number of ops (including micro ops) simulated	13sim_ops 1528988701 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory --- 6 unchanged lines hidden (view full) --- 28system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)	14system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory --- 6 unchanged lines hidden (view full) --- 28system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 26154601 # Total bandwidth to/from this memory (bytes/s)	36system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
37system.cpu.workload.num_syscalls 551 # Number of system calls	37system.cpu.workload.num_syscalls 551 # Number of system calls
38system.cpu.numCycles 3295745694 # number of cpu cycles simulated	38system.cpu.numCycles 3295745696 # number of cpu cycles simulated
39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 826877110 # Number of instructions committed	39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 826877110 # Number of instructions committed
42system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses	42system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses
44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls	44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
47system.cpu.num_int_insts 1528317558 # number of integer instructions	47system.cpu.num_int_insts 1528317560 # number of integer instructions
48system.cpu.num_fp_insts 0 # number of float instructions	48system.cpu.num_fp_insts 0 # number of float instructions
49system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read 50system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written	49system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read 50system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written
51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written	51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
53system.cpu.num_mem_refs 533262341 # number of memory refs	53system.cpu.num_mem_refs 533262342 # number of memory refs
54system.cpu.num_load_insts 384102156 # Number of load instructions	54system.cpu.num_load_insts 384102156 # Number of load instructions
55system.cpu.num_store_insts 149160185 # Number of store instructions	55system.cpu.num_store_insts 149160186 # Number of store instructions
56system.cpu.num_idle_cycles 0 # Number of idle cycles	56system.cpu.num_idle_cycles 0 # Number of idle cycles
57system.cpu.num_busy_cycles 3295745694 # Number of busy cycles	57system.cpu.num_busy_cycles 3295745696 # Number of busy cycles
58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 1253 # number of replacements	58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 1253 # number of replacements
61system.cpu.icache.tagsinuse 881.356492 # Cycle average of tags in use	61system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use
62system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.	62system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
66system.cpu.icache.occ_blocks::cpu.inst 881.356492 # Average occupied blocks per requestor	66system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
67system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 68system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits 70system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits 71system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits 72system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits 73system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits 74system.cpu.icache.overall_hits::total 1068344252 # number of overall hits --- 56 unchanged lines hidden (view full) --- 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 2514362 # number of replacements	67system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 68system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits 70system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits 71system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits 72system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits 73system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits 74system.cpu.icache.overall_hits::total 1068344252 # number of overall hits --- 56 unchanged lines hidden (view full) --- 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 2514362 # number of replacements
139system.cpu.dcache.tagsinuse 4086.415788 # Cycle average of tags in use 140system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.	139system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use 140system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks.
141system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.	141system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
143system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit. 144system.cpu.dcache.occ_blocks::cpu.data 4086.415788 # Average occupied blocks per requestor	143system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit. 144system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits	145system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
149system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits 151system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits 152system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits 154system.cpu.dcache.overall_hits::total 530743928 # number of overall hits	149system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits 151system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits 152system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits 154system.cpu.dcache.overall_hits::total 530743929 # number of overall hits
155system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 156system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 157system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 158system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 159system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 160system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 161system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 162system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 163system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles 164system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles 165system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles 166system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles 167system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles 168system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles 169system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles 170system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles 171system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)	155system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 156system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 157system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 158system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 159system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 160system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 161system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 162system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 163system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles 164system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles 165system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles 166system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles 167system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles 168system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles 169system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles 170system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles 171system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
173system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses	173system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses
179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses 183system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 184system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses 185system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 186system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses --- 44 unchanged lines hidden (view full) --- 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 348459 # number of replacements	179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses 183system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 184system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses 185system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 186system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses --- 44 unchanged lines hidden (view full) --- 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 348459 # number of replacements
239system.cpu.l2cache.tagsinuse 29286.402699 # Cycle average of tags in use	239system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks.	240system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks.
243system.cpu.l2cache.warmup_cycle 755936429000 # Cycle when the warmup percentage was hit. 244system.cpu.l2cache.occ_blocks::writebacks 21041.299363 # Average occupied blocks per requestor	243system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit. 244system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor	245system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 8105.344817 # Average occupied blocks per requestor	246system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor