stats.txt (9096:8971a998190a) stats.txt (9150:a2370fa5c793)
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.652607 # Number of seconds simulated
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.652607 # Number of seconds simulated
4sim_ticks 1652606875000 # Number of ticks simulated
5final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
4sim_ticks 1652606827000 # Number of ticks simulated
5final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 673883 # Simulator instruction rate (inst/s)
8host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1346830511 # Simulator tick rate (ticks/s)
10host_mem_usage 232676 # Number of bytes of host memory used
11host_seconds 1227.03 # Real time elapsed on the host
12sim_insts 826877145 # Number of instructions simulated
13sim_ops 1528988757 # Number of ops (including micro ops) simulated
7host_inst_rate 715148 # Simulator instruction rate (inst/s)
8host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1429304042 # Simulator tick rate (ticks/s)
10host_mem_usage 236556 # Number of bytes of host memory used
11host_seconds 1156.23 # Real time elapsed on the host
12sim_insts 826877110 # Number of instructions simulated
13sim_ops 1528988700 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
16system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s)
14system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
16system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s)
37system.cpu.workload.num_syscalls 551 # Number of system calls
36system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s)
37system.cpu.workload.num_syscalls 551 # Number of system calls
38system.cpu.numCycles 3305213750 # number of cpu cycles simulated
38system.cpu.numCycles 3305213654 # number of cpu cycles simulated
39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41system.cpu.committedInsts 826877145 # Number of instructions committed
42system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
43system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
41system.cpu.committedInsts 826877110 # Number of instructions committed
42system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
43system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
45system.cpu.num_func_calls 0 # number of times a function call or return occured
44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
45system.cpu.num_func_calls 0 # number of times a function call or return occured
46system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
47system.cpu.num_int_insts 1528317615 # number of integer instructions
46system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
47system.cpu.num_int_insts 1528317558 # number of integer instructions
48system.cpu.num_fp_insts 0 # number of float instructions
48system.cpu.num_fp_insts 0 # number of float instructions
49system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
50system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
49system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read
50system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written
51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
53system.cpu.num_mem_refs 533262345 # number of memory refs
54system.cpu.num_load_insts 384102160 # Number of load instructions
53system.cpu.num_mem_refs 533262341 # number of memory refs
54system.cpu.num_load_insts 384102156 # Number of load instructions
55system.cpu.num_store_insts 149160185 # Number of store instructions
56system.cpu.num_idle_cycles 0 # Number of idle cycles
55system.cpu.num_store_insts 149160185 # Number of store instructions
56system.cpu.num_idle_cycles 0 # Number of idle cycles
57system.cpu.num_busy_cycles 3305213750 # Number of busy cycles
57system.cpu.num_busy_cycles 3305213654 # Number of busy cycles
58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59system.cpu.idle_fraction 0 # Percentage of idle cycles
60system.cpu.icache.replacements 1253 # number of replacements
58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59system.cpu.idle_fraction 0 # Percentage of idle cycles
60system.cpu.icache.replacements 1253 # number of replacements
61system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use
62system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
61system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use
62system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
63system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
63system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
64system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
64system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
66system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor
66system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor
67system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy
67system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy
69system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
70system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
71system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
72system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits
73system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits
74system.cpu.icache.overall_hits::total 1068344296 # number of overall hits
69system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
70system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
71system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
72system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
73system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
74system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
75system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
76system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
77system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
78system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
79system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
80system.cpu.icache.overall_misses::total 2814 # number of overall misses
81system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles
75system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
76system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
77system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
78system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
79system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
80system.cpu.icache.overall_misses::total 2814 # number of overall misses
81system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles
87system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
88system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
89system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
90system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses
91system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
92system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
87system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
88system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
89system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
90system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
91system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
92system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
94system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
95system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
96system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
97system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
98system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency

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131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138system.cpu.dcache.replacements 2514362 # number of replacements
93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
94system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
95system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
96system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
97system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
98system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency

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131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138system.cpu.dcache.replacements 2514362 # number of replacements
139system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use
140system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
139system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use
140system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
141system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
141system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
142system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
143system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit.
144system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor
142system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
143system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit.
144system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy
145system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy
147system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
148system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
147system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
148system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
149system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
150system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
149system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
150system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
151system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits
152system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits
153system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits
154system.cpu.dcache.overall_hits::total 530743932 # number of overall hits
151system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
152system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
153system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
154system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
155system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
156system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
157system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
158system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
159system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
160system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
161system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
162system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
163system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles
155system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
156system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
157system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
158system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
159system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
160system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
161system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
162system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
163system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles
171system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
172system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
171system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
172system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
173system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
174system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
173system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
174system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
175system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses
176system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses
177system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
178system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
175system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
176system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
177system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
178system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
180system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
183system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
184system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
185system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
186system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses

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231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
238system.cpu.l2cache.replacements 403150 # number of replacements
179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
180system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
183system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
184system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
185system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
186system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses

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231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
238system.cpu.l2cache.replacements 403150 # number of replacements
239system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use
239system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
240system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
243system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor
243system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
253system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits
254system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits

--- 123 unchanged lines hidden ---
247system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
253system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits
254system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits

--- 123 unchanged lines hidden ---