Cross Reference: /gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 1.658730 # Number of seconds simulated
4sim_ticks 1658729604000 # Number of ticks simulated
5final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 1.652422 # Number of seconds simulated
4sim_ticks 1652422044000 # Number of ticks simulated
5final_tick 1652422044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 615589 # Simulator instruction rate (inst/s)
8host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1234881669 # Simulator tick rate (ticks/s)
10host_mem_usage 229524 # Number of bytes of host memory used
11host_seconds 1343.23 # Real time elapsed on the host

7host_inst_rate 1001096 # Simulator instruction rate (inst/s)
8host_op_rate 1851139 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2000579398 # Simulator tick rate (ticks/s)
10host_mem_usage 231692 # Number of bytes of host memory used
11host_seconds 825.97 # Real time elapsed on the host

12sim_insts 826877145 # Number of instructions simulated
13sim_ops 1528988757 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory
16system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory
20system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s)

14system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
16system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 74790 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 16557436 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 16632225 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 74790 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 74790 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 12532198 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 12532198 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 12532198 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 74790 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 16557436 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 29164423 # Total bandwidth to/from this memory (bytes/s)

37system.cpu.workload.num_syscalls 551 # Number of system calls

38system.cpu.numCycles 3317459208 # number of cpu cycles simulated

38system.cpu.numCycles 3304844088 # number of cpu cycles simulated

39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41system.cpu.committedInsts 826877145 # Number of instructions committed
42system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
43system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
45system.cpu.num_func_calls 0 # number of times a function call or return occured
46system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
47system.cpu.num_int_insts 1528317615 # number of integer instructions
48system.cpu.num_fp_insts 0 # number of float instructions
49system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
50system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
53system.cpu.num_mem_refs 533262345 # number of memory refs
54system.cpu.num_load_insts 384102160 # Number of load instructions
55system.cpu.num_store_insts 149160185 # Number of store instructions
56system.cpu.num_idle_cycles 0 # Number of idle cycles

57system.cpu.num_busy_cycles 3317459208 # Number of busy cycles

57system.cpu.num_busy_cycles 3304844088 # Number of busy cycles

58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59system.cpu.idle_fraction 0 # Percentage of idle cycles
60system.cpu.icache.replacements 1253 # number of replacements

61system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use

61system.cpu.icache.tagsinuse 881.582723 # Cycle average of tags in use

62system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
63system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
64system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

66system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor
67system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy

66system.cpu.icache.occ_blocks::cpu.inst 881.582723 # Average occupied blocks per requestor
67system.cpu.icache.occ_percent::cpu.inst 0.430460 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.430460 # Average percentage of cache occupancy

69system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
70system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
71system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
72system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits
73system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits
74system.cpu.icache.overall_hits::total 1068344296 # number of overall hits
75system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
76system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
77system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
78system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
79system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
80system.cpu.icache.overall_misses::total 2814 # number of overall misses

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 120498000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 120498000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 120498000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 120498000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 120498000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 120498000 # number of overall miss cycles

87system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
88system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
89system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
90system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses
91system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
92system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
94system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
95system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
96system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
97system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
98system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42820.895522 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 42820.895522 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 42820.895522 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 42820.895522 # average overall miss latency

105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
111system.cpu.icache.fast_writes 0 # number of fast writes performed
112system.cpu.icache.cache_copies 0 # number of cache copies performed
113system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
114system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
115system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
116system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
117system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
118system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112056000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 112056000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112056000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 112056000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112056000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 112056000 # number of overall MSHR miss cycles

125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
128system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
130system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39820.895522 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39820.895522 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency

137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138system.cpu.dcache.replacements 2514362 # number of replacements

139system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use

139system.cpu.dcache.tagsinuse 4086.435686 # Cycle average of tags in use

140system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
141system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
142system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
143system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.

144system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy

144system.cpu.dcache.occ_blocks::cpu.data 4086.435686 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.997665 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.997665 # Average percentage of cache occupancy

147system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
148system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
149system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
150system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
151system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits
152system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits
153system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits
154system.cpu.dcache.overall_hits::total 530743932 # number of overall hits
155system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
156system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
157system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
158system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
159system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
160system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
161system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
162system.cpu.dcache.overall_misses::total 2518458 # number of overall misses

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 33321318000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 33321318000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892023500 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 19892023500 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 53213341500 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 53213341500 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 53213341500 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 53213341500 # number of overall miss cycles

171system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
172system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
173system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
174system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
175system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses
176system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses
177system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
178system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
180system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
183system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
184system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
185system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
186system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19289.711673 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 19289.711673 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25146.544946 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 25146.544946 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 21129.334498 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 21129.334498 # average overall miss latency

195system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
197system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
198system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
199system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
200system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
201system.cpu.dcache.fast_writes 0 # number of fast writes performed
202system.cpu.dcache.cache_copies 0 # number of cache copies performed

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204system.cpu.dcache.writebacks::total 2223170 # number of writebacks

203system.cpu.dcache.writebacks::writebacks 2297113 # number of writebacks
204system.cpu.dcache.writebacks::total 2297113 # number of writebacks

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206system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
207system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
208system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
209system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
210system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
211system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
212system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139074000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139074000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518883000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518883000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45657957000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 45657957000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45657957000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 45657957000 # number of overall MSHR miss cycles

221system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
222system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
223system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
224system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
225system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
226system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
227system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
228system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.710515 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.710515 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.534200 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.534200 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency

237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

238system.cpu.l2cache.replacements 568906 # number of replacements
239system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
243system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits
253system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits
254system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits
255system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits
256system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # number of ReadExReq hits
257system.cpu.l2cache.ReadExReq_hits::total 543011 # number of ReadExReq hits
258system.cpu.l2cache.demand_hits::cpu.inst 493 # number of demand (read+write) hits
259system.cpu.l2cache.demand_hits::cpu.data 1941170 # number of demand (read+write) hits
260system.cpu.l2cache.demand_hits::total 1941663 # number of demand (read+write) hits
261system.cpu.l2cache.overall_hits::cpu.inst 493 # number of overall hits
262system.cpu.l2cache.overall_hits::cpu.data 1941170 # number of overall hits
263system.cpu.l2cache.overall_hits::total 1941663 # number of overall hits
264system.cpu.l2cache.ReadReq_misses::cpu.inst 2321 # number of ReadReq misses
265system.cpu.l2cache.ReadReq_misses::cpu.data 329255 # number of ReadReq misses
266system.cpu.l2cache.ReadReq_misses::total 331576 # number of ReadReq misses
267system.cpu.l2cache.ReadExReq_misses::cpu.data 248033 # number of ReadExReq misses
268system.cpu.l2cache.ReadExReq_misses::total 248033 # number of ReadExReq misses
269system.cpu.l2cache.demand_misses::cpu.inst 2321 # number of demand (read+write) misses
270system.cpu.l2cache.demand_misses::cpu.data 577288 # number of demand (read+write) misses
271system.cpu.l2cache.demand_misses::total 579609 # number of demand (read+write) misses
272system.cpu.l2cache.overall_misses::cpu.inst 2321 # number of overall misses
273system.cpu.l2cache.overall_misses::cpu.data 577288 # number of overall misses
274system.cpu.l2cache.overall_misses::total 579609 # number of overall misses
275system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120692000 # number of ReadReq miss cycles
276system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17121260000 # number of ReadReq miss cycles
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278system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12897722000 # number of ReadExReq miss cycles
279system.cpu.l2cache.ReadExReq_miss_latency::total 12897722000 # number of ReadExReq miss cycles
280system.cpu.l2cache.demand_miss_latency::cpu.inst 120692000 # number of demand (read+write) miss cycles
281system.cpu.l2cache.demand_miss_latency::cpu.data 30018982000 # number of demand (read+write) miss cycles
282system.cpu.l2cache.demand_miss_latency::total 30139674000 # number of demand (read+write) miss cycles
283system.cpu.l2cache.overall_miss_latency::cpu.inst 120692000 # number of overall miss cycles
284system.cpu.l2cache.overall_miss_latency::cpu.data 30018982000 # number of overall miss cycles
285system.cpu.l2cache.overall_miss_latency::total 30139674000 # number of overall miss cycles

238system.cpu.l2cache.replacements 403150 # number of replacements
239system.cpu.l2cache.tagsinuse 29113.171325 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
243system.cpu.l2cache.warmup_cycle 772998682000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 21035.686564 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 79.698096 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 7997.786666 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.641958 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.244073 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.888463 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
253system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits
254system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits
255system.cpu.l2cache.Writeback_hits::total 2297113 # number of Writeback hits
256system.cpu.l2cache.ReadExReq_hits::cpu.data 581106 # number of ReadExReq hits
257system.cpu.l2cache.ReadExReq_hits::total 581106 # number of ReadExReq hits
258system.cpu.l2cache.demand_hits::cpu.inst 883 # number of demand (read+write) hits
259system.cpu.l2cache.demand_hits::cpu.data 2090960 # number of demand (read+write) hits
260system.cpu.l2cache.demand_hits::total 2091843 # number of demand (read+write) hits
261system.cpu.l2cache.overall_hits::cpu.inst 883 # number of overall hits
262system.cpu.l2cache.overall_hits::cpu.data 2090960 # number of overall hits
263system.cpu.l2cache.overall_hits::total 2091843 # number of overall hits
264system.cpu.l2cache.ReadReq_misses::cpu.inst 1931 # number of ReadReq misses
265system.cpu.l2cache.ReadReq_misses::cpu.data 217560 # number of ReadReq misses
266system.cpu.l2cache.ReadReq_misses::total 219491 # number of ReadReq misses
267system.cpu.l2cache.ReadExReq_misses::cpu.data 209938 # number of ReadExReq misses
268system.cpu.l2cache.ReadExReq_misses::total 209938 # number of ReadExReq misses
269system.cpu.l2cache.demand_misses::cpu.inst 1931 # number of demand (read+write) misses
270system.cpu.l2cache.demand_misses::cpu.data 427498 # number of demand (read+write) misses
271system.cpu.l2cache.demand_misses::total 429429 # number of demand (read+write) misses
272system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses
273system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses
274system.cpu.l2cache.overall_misses::total 429429 # number of overall misses
275system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100412000 # number of ReadReq miss cycles
276system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313120000 # number of ReadReq miss cycles
277system.cpu.l2cache.ReadReq_miss_latency::total 11413532000 # number of ReadReq miss cycles
278system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916779000 # number of ReadExReq miss cycles
279system.cpu.l2cache.ReadExReq_miss_latency::total 10916779000 # number of ReadExReq miss cycles
280system.cpu.l2cache.demand_miss_latency::cpu.inst 100412000 # number of demand (read+write) miss cycles
281system.cpu.l2cache.demand_miss_latency::cpu.data 22229899000 # number of demand (read+write) miss cycles
282system.cpu.l2cache.demand_miss_latency::total 22330311000 # number of demand (read+write) miss cycles
283system.cpu.l2cache.overall_miss_latency::cpu.inst 100412000 # number of overall miss cycles
284system.cpu.l2cache.overall_miss_latency::cpu.data 22229899000 # number of overall miss cycles
285system.cpu.l2cache.overall_miss_latency::total 22330311000 # number of overall miss cycles

286system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
287system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
288system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)

289system.cpu.l2cache.Writeback_accesses::writebacks 2223170 # number of Writeback accesses(hits+misses)
290system.cpu.l2cache.Writeback_accesses::total 2223170 # number of Writeback accesses(hits+misses)

289system.cpu.l2cache.Writeback_accesses::writebacks 2297113 # number of Writeback accesses(hits+misses)
290system.cpu.l2cache.Writeback_accesses::total 2297113 # number of Writeback accesses(hits+misses)

291system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
292system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
293system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
294system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
295system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
296system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
297system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
298system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses

299system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses
300system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses
301system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses
302system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses
303system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses
304system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses
305system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses
306system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses
307system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses
308system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses
309system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses

299system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.686212 # miss rate for ReadReq accesses
300system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.125945 # miss rate for ReadReq accesses
301system.cpu.l2cache.ReadReq_miss_rate::total 0.126857 # miss rate for ReadReq accesses
302system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265394 # miss rate for ReadExReq accesses
303system.cpu.l2cache.ReadExReq_miss_rate::total 0.265394 # miss rate for ReadExReq accesses
304system.cpu.l2cache.demand_miss_rate::cpu.inst 0.686212 # miss rate for demand accesses
305system.cpu.l2cache.demand_miss_rate::cpu.data 0.169746 # miss rate for demand accesses
306system.cpu.l2cache.demand_miss_rate::total 0.170322 # miss rate for demand accesses
307system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses
308system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses
309system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses

310system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
311system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
312system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency

313system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency
314system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency

313system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.014290 # average ReadExReq miss latency
314system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.014290 # average ReadExReq miss latency

315system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency

316system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
317system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency

316system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
317system.cpu.l2cache.demand_avg_miss_latency::total 52000.006986 # average overall miss latency

318system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency

319system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
320system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency

319system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
320system.cpu.l2cache.overall_avg_miss_latency::total 52000.006986 # average overall miss latency

321system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
322system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
323system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
324system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
325system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
326system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
327system.cpu.l2cache.fast_writes 0 # number of fast writes performed
328system.cpu.l2cache.cache_copies 0 # number of cache copies performed

329system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks
330system.cpu.l2cache.writebacks::total 411709 # number of writebacks
331system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses
332system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses
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336system.cpu.l2cache.demand_mshr_misses::cpu.inst 2321 # number of demand (read+write) MSHR misses
337system.cpu.l2cache.demand_mshr_misses::cpu.data 577288 # number of demand (read+write) MSHR misses
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340system.cpu.l2cache.overall_mshr_misses::cpu.data 577288 # number of overall MSHR misses
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342system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92840000 # number of ReadReq MSHR miss cycles
343system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13170200000 # number of ReadReq MSHR miss cycles
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345system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9921320000 # number of ReadExReq MSHR miss cycles
346system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9921320000 # number of ReadExReq MSHR miss cycles
347system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles
348system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles
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350system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles
351system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles
352system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles
353system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses
354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses
355system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses
356system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses
357system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses
358system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses
359system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses
360system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses
361system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses
362system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses
363system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses

329system.cpu.l2cache.writebacks::writebacks 323570 # number of writebacks
330system.cpu.l2cache.writebacks::total 323570 # number of writebacks
331system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1931 # number of ReadReq MSHR misses
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333system.cpu.l2cache.ReadReq_mshr_misses::total 219491 # number of ReadReq MSHR misses
334system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209938 # number of ReadExReq MSHR misses
335system.cpu.l2cache.ReadExReq_mshr_misses::total 209938 # number of ReadExReq MSHR misses
336system.cpu.l2cache.demand_mshr_misses::cpu.inst 1931 # number of demand (read+write) MSHR misses
337system.cpu.l2cache.demand_mshr_misses::cpu.data 427498 # number of demand (read+write) MSHR misses
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339system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses
340system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses
341system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses
342system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77240000 # number of ReadReq MSHR miss cycles
343system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702400000 # number of ReadReq MSHR miss cycles
344system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779640000 # number of ReadReq MSHR miss cycles
345system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles
346system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles
347system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77240000 # number of demand (read+write) MSHR miss cycles
348system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17099920000 # number of demand (read+write) MSHR miss cycles
349system.cpu.l2cache.demand_mshr_miss_latency::total 17177160000 # number of demand (read+write) MSHR miss cycles
350system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77240000 # number of overall MSHR miss cycles
351system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17099920000 # number of overall MSHR miss cycles
352system.cpu.l2cache.overall_mshr_miss_latency::total 17177160000 # number of overall MSHR miss cycles
353system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses
354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses
355system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses
356system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265394 # mshr miss rate for ReadExReq accesses
357system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265394 # mshr miss rate for ReadExReq accesses
358system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for demand accesses
359system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for demand accesses
360system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 # mshr miss rate for demand accesses
361system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses
362system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses
363system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses