| stats.txt (9039:9a22621c741c) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.658730 # Number of seconds simulated 4sim_ticks 1658729604000 # Number of ticks simulated 5final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.658730 # Number of seconds simulated 4sim_ticks 1658729604000 # Number of ticks simulated 5final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 478704 # Simulator instruction rate (inst/s) 8host_op_rate 885178 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 960288988 # Simulator tick rate (ticks/s) 10host_mem_usage 252496 # Number of bytes of host memory used 11host_seconds 1727.32 # Real time elapsed on the host | 7host_inst_rate 615589 # Simulator instruction rate (inst/s) 8host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1234881669 # Simulator tick rate (ticks/s) 10host_mem_usage 229524 # Number of bytes of host memory used 11host_seconds 1343.23 # Real time elapsed on the host |
| 12sim_insts 826877145 # Number of instructions simulated 13sim_ops 1528988757 # Number of ops (including micro ops) simulated | 12sim_insts 826877145 # Number of instructions simulated 13sim_ops 1528988757 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 37094976 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 26349376 # Number of bytes written to this memory 17system.physmem.num_reads 579609 # Number of read requests responded to by this memory 18system.physmem.num_writes 411709 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory 16system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory 20system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s) |
| 24system.cpu.workload.num_syscalls 551 # Number of system calls 25system.cpu.numCycles 3317459208 # number of cpu cycles simulated 26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28system.cpu.committedInsts 826877145 # Number of instructions committed 29system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed 30system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses 31system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 73system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles 74system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) 75system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) 76system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses 77system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses 78system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses 79system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses 80system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses | 37system.cpu.workload.num_syscalls 551 # Number of system calls 38system.cpu.numCycles 3317459208 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 826877145 # Number of instructions committed 42system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 41 unchanged lines hidden (view full) --- 86system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles 87system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) 88system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) 89system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses 90system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses 91system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses 92system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses 93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses |
| 94system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses |
|
| 81system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses | 95system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses |
| 96system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses |
|
| 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses | 97system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses |
| 98system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses |
|
| 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency | 99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency |
| 100system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency |
|
| 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency | 101system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency |
| 102system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency |
|
| 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency | 103system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency |
| 104system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency |
|
| 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 90system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 99system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 100system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles 101system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles 102system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles 103system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles 104system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles 105system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles 106system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses | 105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111system.cpu.icache.fast_writes 0 # number of fast writes performed 112system.cpu.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 118system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles 120system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles 121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles 122system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles 123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles 124system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles 125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses |
| 126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses |
|
| 107system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses | 127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses |
| 128system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses |
|
| 108system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses | 129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses |
| 130system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses |
|
| 109system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency | 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency |
| 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency |
|
| 110system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency | 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency |
| 134system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency |
|
| 111system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency | 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency |
| 136system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency |
|
| 112system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 113system.cpu.dcache.replacements 2514362 # number of replacements 114system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use 115system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. 116system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. 117system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. 118system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. 119system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 147system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 150system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses 151system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses 152system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses 153system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses 154system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses | 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 2514362 # number of replacements 139system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use 140system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. 141system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. 143system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. 144system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 172system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) 173system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses 179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses |
| 180system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses |
|
| 155system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses | 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses |
| 182system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses |
|
| 156system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses | 183system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses |
| 184system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses |
|
| 157system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses | 185system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses |
| 186system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses |
|
| 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency | 187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency |
| 188system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency |
|
| 159system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency | 189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency |
| 190system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency |
|
| 160system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency | 191system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency |
| 192system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency |
|
| 161system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency | 193system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency |
| 194system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency |
|
| 162system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 167system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 168system.cpu.dcache.fast_writes 0 # number of fast writes performed 169system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 181system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles 182system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles 183system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles 184system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles 185system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles 187system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles 188system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses | 195system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 196system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 197system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 198system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 199system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 200system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 201system.cpu.dcache.fast_writes 0 # number of fast writes performed 202system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 214system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles 215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles 216system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles 217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles 218system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles 219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles 220system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles 221system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses |
| 222system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses |
|
| 189system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses | 223system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses |
| 224system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses |
|
| 190system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses | 225system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses |
| 226system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses |
|
| 191system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses | 227system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses |
| 228system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses |
|
| 192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency | 229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency |
| 230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency |
|
| 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency | 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency |
| 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency |
|
| 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency | 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency |
| 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency |
|
| 195system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency | 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency |
| 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency |
|
| 196system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 197system.cpu.l2cache.replacements 568906 # number of replacements 198system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use 199system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. 200system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. 201system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. 202system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. 203system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 252system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 253system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses 254system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses 255system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 256system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses 257system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses 258system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses 259system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses | 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 568906 # number of replacements 239system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use 240system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. 243system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. 244system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 293system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 294system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses 295system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses 296system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 297system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses 298system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses 299system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses 300system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses |
| 301system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses |
|
| 260system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses | 302system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses |
| 303system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses |
|
| 261system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses 262system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses | 304system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses 305system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses |
| 306system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses |
|
| 263system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses 264system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses | 307system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses 308system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses |
| 309system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses |
|
| 265system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 266system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency | 310system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 311system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency |
| 312system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency |
|
| 267system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency | 313system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency |
| 314system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency |
|
| 268system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 269system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency | 315system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 316system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency |
| 317system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency |
|
| 270system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 271system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency | 318system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 319system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency |
| 320system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency |
|
| 272system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 273system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 274system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 275system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 276system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 277system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 278system.cpu.l2cache.fast_writes 0 # number of fast writes performed 279system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 298system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles 299system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles 300system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles 301system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles 302system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles 303system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles 304system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses 305system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses | 321system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 322system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 323system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 324system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 325system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 326system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 327system.cpu.l2cache.fast_writes 0 # number of fast writes performed 328system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 347system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles 348system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles 349system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles 350system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles 351system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles 352system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles 353system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses 354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses |
| 355system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses |
|
| 306system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses | 356system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses |
| 357system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses |
|
| 307system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses 308system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses | 358system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses 359system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses |
| 360system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses |
|
| 309system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses 310system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses | 361system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses 362system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses |
| 363system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses |
|
| 311system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 312system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency | 364system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 365system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency |
| 366system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |
|
| 313system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency | 367system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency |
| 368system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency |
|
| 314system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 315system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency | 369system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 370system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
| 371system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
|
| 316system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 317system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency | 372system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 373system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
| 374system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
|
| 318system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 319 320---------- End Simulation Statistics ---------- | 375system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 376 377---------- End Simulation Statistics ---------- |