Cross Reference: /gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 1.650501 # Number of seconds simulated
4sim_ticks 1650501252500 # Number of ticks simulated
5final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 1.650924 # Number of seconds simulated
4sim_ticks 1650923912500 # Number of ticks simulated
5final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 516047 # Simulator instruction rate (inst/s)
8host_op_rate 954946 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1030101248 # Simulator tick rate (ticks/s)
10host_mem_usage 278616 # Number of bytes of host memory used
11host_seconds 1602.27 # Real time elapsed on the host

7host_inst_rate 598809 # Simulator instruction rate (inst/s)
8host_op_rate 1108098 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1195612149 # Simulator tick rate (ticks/s)
10host_mem_usage 285816 # Number of bytes of host memory used
11host_seconds 1380.82 # Real time elapsed on the host

12sim_insts 826847304 # Number of instructions simulated
13sim_ops 1530082521 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
19system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
23system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory
19system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory
23system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

41system.cpu_clk_domain.clock 500 # Clock period in ticks

42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks

44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

46system.cpu.workload.num_syscalls 551 # Number of system calls

47system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states
48system.cpu.numCycles 3301002505 # number of cpu cycles simulated

47system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states
48system.cpu.numCycles 3301847825 # number of cpu cycles simulated

49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
51system.cpu.committedInsts 826847304 # Number of instructions committed
52system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
53system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
55system.cpu.num_func_calls 35346287 # number of times a function call or return occured
56system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

61system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
62system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
63system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
64system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
65system.cpu.num_mem_refs 533241508 # number of memory refs
66system.cpu.num_load_insts 384083313 # Number of load instructions
67system.cpu.num_store_insts 149158195 # Number of store instructions
68system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

69system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles

69system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles

70system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
71system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
72system.cpu.Branches 149981740 # Number of branches fetched
73system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
74system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
75system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
76system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
77system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction

--- 22 unchanged lines hidden (view full) ---

100system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
101system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
102system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
103system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
104system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
105system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
106system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
107system.cpu.op_class::total 1530082521 # Class of executed instruction

108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

109system.cpu.dcache.tags.replacements 2517016 # number of replacements

110system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use

110system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use

111system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
112system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
113system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.

114system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
115system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor
116system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
117system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy

114system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit.
115system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor
116system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy
117system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy

118system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
119system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
120system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
121system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
122system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
123system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
124system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
125system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
126system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses

127system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

127system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

128system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
129system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
130system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
131system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits
132system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits
133system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits
134system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits
135system.cpu.dcache.overall_hits::total 530720441 # number of overall hits
136system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses
137system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses
138system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses
139system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses
140system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses
141system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
142system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses
143system.cpu.dcache.overall_misses::total 2521112 # number of overall misses

144system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles
145system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles
146system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles
147system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles
148system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles
149system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles
150system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles
151system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles

144system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles
145system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles
146system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles
147system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles
148system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles
149system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles
150system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles
151system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles

152system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses)
153system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
154system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
155system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
156system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses
157system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses
158system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses
159system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses
160system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses
161system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses
162system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses
163system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses
164system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses
165system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses
166system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses
167system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses

168system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency
169system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency
170system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency
171system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency
172system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
173system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency
174system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
175system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency

168system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency
169system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency
170system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency
171system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency
172system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency
173system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency
174system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency
175system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency

176system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
177system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
178system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
179system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
180system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
181system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

182system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
183system.cpu.dcache.writebacks::total 2325221 # number of writebacks

182system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks
183system.cpu.dcache.writebacks::total 2324919 # number of writebacks

184system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
185system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses
186system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses
187system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses
188system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses
189system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses
190system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses
191system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses

192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles
193system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles
194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles
195system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles
196system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles
197system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles
198system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles
199system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles

192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles
193system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles
194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles
195system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles
196system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles
197system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles
198system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles
199system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles

200system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses
201system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses
202system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses
203system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses
204system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses
205system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses
206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses
207system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses

208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency
209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency
210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency
211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency
212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
213system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
215system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency
209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency
210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency
211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency
212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency
213system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency
214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency
215system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency
216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

217system.cpu.icache.tags.replacements 1253 # number of replacements

218system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use

218system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use

219system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
220system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
221system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks.
222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

223system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor

223system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor

224system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
225system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
226system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
227system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
228system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
229system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
230system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
231system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
232system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
233system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
234system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses

235system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

235system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

236system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
237system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
238system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
239system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits
240system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits
241system.cpu.icache.overall_hits::total 1068307822 # number of overall hits
242system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
243system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
244system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
245system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
246system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
247system.cpu.icache.overall_misses::total 2814 # number of overall misses

248system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles
249system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles
250system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles
251system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles
252system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles
253system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles

248system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles
249system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles
250system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles
251system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles
252system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles
253system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles

254system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses)
255system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses)
256system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses
257system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses
258system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses
259system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses
260system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
261system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
262system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
263system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
264system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
265system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses

266system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency
267system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency
268system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
269system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency
270system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
271system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency

266system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency
267system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency
268system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency
269system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency
270system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency
271system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency

272system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
273system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
274system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
275system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
276system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
277system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
278system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
279system.cpu.icache.writebacks::total 1253 # number of writebacks
280system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
281system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
282system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
283system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
284system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
285system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses

286system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles
287system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles
288system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles
289system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles
290system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles
291system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles

286system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles
287system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles
288system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles
289system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles
290system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles
291system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles

292system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
293system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
294system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
295system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
296system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
297system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses

298system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency
299system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency
300system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
301system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
302system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
303system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
304system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
305system.cpu.l2cache.tags.replacements 348438 # number of replacements
306system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
307system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
308system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
309system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks.
310system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
311system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor
312system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor
313system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor
314system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy
315system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
316system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy
317system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy
318system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
319system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
321system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
322system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
323system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
324system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
325system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
326system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
327system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
328system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits

298system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency
299system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency
300system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency
301system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency
302system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency
303system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency
304system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
305system.cpu.l2cache.tags.replacements 349420 # number of replacements
306system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use
307system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks.
308system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks.
309system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks.
310system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit.
311system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor
312system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor
313system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor
314system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy
315system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy
316system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy
317system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy
318system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
319system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id
321system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id
322system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
323system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses
324system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses
325system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
326system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits
327system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits

329system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
330system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits

328system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
329system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits

331system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits
332system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits
333system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
334system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
335system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits
336system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits
337system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits
338system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits
339system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits
340system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits
341system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits
342system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits
343system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
344system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
345system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
346system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
347system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses
348system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses
349system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
350system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
351system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses
352system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
353system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
354system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
355system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles
356system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
357system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles
358system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles
359system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
360system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
361system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles
362system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles
363system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles
364system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles
365system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles
366system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles
367system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses)
368system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses)

330system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits
331system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits
332system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # number of ReadCleanReq hits
333system.cpu.l2cache.ReadCleanReq_hits::total 1002 # number of ReadCleanReq hits
334system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 # number of ReadSharedReq hits
335system.cpu.l2cache.ReadSharedReq_hits::total 1556392 # number of ReadSharedReq hits
336system.cpu.l2cache.demand_hits::cpu.inst 1002 # number of demand (read+write) hits
337system.cpu.l2cache.demand_hits::cpu.data 2141233 # number of demand (read+write) hits
338system.cpu.l2cache.demand_hits::total 2142235 # number of demand (read+write) hits
339system.cpu.l2cache.overall_hits::cpu.inst 1002 # number of overall hits
340system.cpu.l2cache.overall_hits::cpu.data 2141233 # number of overall hits
341system.cpu.l2cache.overall_hits::total 2142235 # number of overall hits
342system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses
343system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses
344system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses
345system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses
346system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses
347system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses
348system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses
349system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses
350system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses
351system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses
352system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses
353system.cpu.l2cache.overall_misses::total 381691 # number of overall misses
354system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles
355system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles
356system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles
357system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles
358system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles
359system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles
360system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles
361system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles
362system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles
363system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles
364system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles
365system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles
366system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses)
367system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses)

369system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
370system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
371system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses)
372system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses)
373system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
374system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
375system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses)
376system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses)
377system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
378system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses
379system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses
380system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
381system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses
382system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses

368system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
369system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
370system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses)
371system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses)
372system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
373system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
374system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses)
375system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses)
376system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
377system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses
378system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses
379system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
380system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses
381system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses

383system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses
384system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses
385system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
386system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
387system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses
388system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses
389system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
390system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses
391system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses
392system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
393system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses
394system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses
395system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
396system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
397system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency
398system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency
399system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
400system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
401system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
402system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
403system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency
404system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
405system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
406system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency

382system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses
383system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses
384system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses
385system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses
386system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses
387system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses
388system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses
389system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses
390system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses
391system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses
392system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses
393system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses
394system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency
395system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency
396system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency
397system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency
398system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency
399system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency
400system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency
401system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency
402system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency
403system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency
404system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency
405system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency

407system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
408system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
409system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
410system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
411system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
412system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

406system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
407system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
408system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
409system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
410system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
411system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

413system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
414system.cpu.l2cache.writebacks::total 293208 # number of writebacks

412system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks
413system.cpu.l2cache.writebacks::total 293952 # number of writebacks

415system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
416system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses

414system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
415system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses

417system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
418system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
419system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
420system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
421system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
422system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses
423system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
424system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
425system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses
426system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
427system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
428system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
429system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
430system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
431system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles
432system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles
433system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
434system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
435system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles
436system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles
437system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles
438system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles
439system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles
440system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles

416system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses
417system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses
418system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses
419system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses
420system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses
421system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses
422system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses
423system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses
424system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses
425system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses
426system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses
427system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses
428system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles
429system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles
430system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles
431system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles
432system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles
433system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles
434system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles
435system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles
436system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles
437system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles
438system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles
439system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles

441system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
442system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

440system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
441system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

443system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses
444system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses
445system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
446system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
447system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses
448system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses
449system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
450system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses
451system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses
452system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
453system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses
454system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses
455system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
456system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
457system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency
458system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency
459system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
460system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
461system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
462system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
463system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
464system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
465system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
466system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency

442system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses
443system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses
444system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses
445system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses
446system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses
447system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses
448system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses
449system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses
450system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses
451system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses
452system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses
453system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses
454system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency
455system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency
456system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency
457system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency
458system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency
459system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency
460system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency
461system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency
462system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency
463system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency
464system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency
465system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency

467system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
468system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
469system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

466system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
467system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
468system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

470system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
471system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

469system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter.
470system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

472system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

471system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

473system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states

472system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states

474system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution

473system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution

475system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution

474system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution

476system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution

475system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution

477system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution

476system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution

478system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
479system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
480system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
481system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution
482system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
483system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
484system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
485system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)

477system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
478system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
479system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
480system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution
481system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
482system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
483system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
484system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)

486system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes)
487system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes)
488system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
489system.cpu.toL2Bus.snoopTraffic 18765312 # Total snoop traffic (bytes)
490system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
492system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram

485system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes)
486system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes)
487system.cpu.toL2Bus.snoops 349420 # Total snoops (count)
488system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes)
489system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram
490system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram

493system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

492system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

494system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram
495system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram

493system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram
494system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram

496system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
497system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
498system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
499system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

495system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
496system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
497system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
498system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

500system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram
501system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks)

499system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram
500system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks)

502system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
503system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
504system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
505system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
506system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

501system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
502system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
503system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
504system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
505system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

507system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
508system.membus.trans_dist::ReadResp 174499 # Transaction distribution
509system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
510system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
511system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
512system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
513system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
514system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
515system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
516system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
517system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
518system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
519system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)

506system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter.
507system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data.
508system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
509system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
510system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
511system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
512system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
513system.membus.trans_dist::ReadResp 175162 # Transaction distribution
514system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution
515system.membus.trans_dist::CleanEvict 53608 # Transaction distribution
516system.membus.trans_dist::ReadExReq 206529 # Transaction distribution
517system.membus.trans_dist::ReadExResp 206529 # Transaction distribution
518system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution
519system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes)
520system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes)
521system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes)
522system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes)
523system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes)
524system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes)

520system.membus.snoops 0 # Total snoops (count)
521system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

525system.membus.snoops 0 # Total snoops (count)
526system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

522system.membus.snoop_fanout::samples 727569 # Request fanout histogram

527system.membus.snoop_fanout::samples 381691 # Request fanout histogram

523system.membus.snoop_fanout::mean 0 # Request fanout histogram
524system.membus.snoop_fanout::stdev 0 # Request fanout histogram
525system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

528system.membus.snoop_fanout::mean 0 # Request fanout histogram
529system.membus.snoop_fanout::stdev 0 # Request fanout histogram
530system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

526system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram

531system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram

527system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
528system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
529system.membus.snoop_fanout::min_value 0 # Request fanout histogram
530system.membus.snoop_fanout::max_value 0 # Request fanout histogram

532system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
533system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
534system.membus.snoop_fanout::min_value 0 # Request fanout histogram
535system.membus.snoop_fanout::max_value 0 # Request fanout histogram

531system.membus.snoop_fanout::total 727569 # Request fanout histogram
532system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks)

536system.membus.snoop_fanout::total 381691 # Request fanout histogram
537system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks)

533system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

538system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

534system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)

539system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks)