| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.650501 # Number of seconds simulated 4sim_ticks 1650501252500 # Number of ticks simulated 5final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.650501 # Number of seconds simulated 4sim_ticks 1650501252500 # Number of ticks simulated 5final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 482495 # Simulator instruction rate (inst/s) 8host_op_rate 892859 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 963127288 # Simulator tick rate (ticks/s) 10host_mem_usage 277668 # Number of bytes of host memory used 11host_seconds 1713.69 # Real time elapsed on the host | 7host_inst_rate 943240 # Simulator instruction rate (inst/s) 8host_op_rate 1745467 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1882837072 # Simulator tick rate (ticks/s) 10host_mem_usage 326104 # Number of bytes of host memory used 11host_seconds 876.60 # Real time elapsed on the host |
| 12sim_insts 826847304 # Number of instructions simulated 13sim_ops 1530082521 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826847304 # Number of instructions simulated 13sim_ops 1530082521 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 32system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) |
| 40system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 39system.cpu_clk_domain.clock 500 # Clock period in ticks | 41system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states 45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 41system.cpu.workload.num_syscalls 551 # Number of system calls | 46system.cpu.workload.num_syscalls 551 # Number of system calls |
| 47system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 42system.cpu.numCycles 3301002505 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 826847304 # Number of instructions committed 46system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 49system.cpu.num_func_calls 35346287 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 94system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction 97system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction 98system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 1530082521 # Class of executed instruction | 48system.cpu.numCycles 3301002505 # number of cpu cycles simulated 49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51system.cpu.committedInsts 826847304 # Number of instructions committed 52system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed 53system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses 54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 55system.cpu.num_func_calls 35346287 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 100system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction 101system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction 102system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction 103system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction 104system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction 105system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 106system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 107system.cpu.op_class::total 1530082521 # Class of executed instruction |
| 108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 102system.cpu.dcache.tags.replacements 2517016 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses | 109system.cpu.dcache.tags.replacements 2517016 # number of replacements 110system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use 111system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. 112system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. 113system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. 114system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. 115system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor 116system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy 117system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy 118system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 119system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 120system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 121system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 122system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 123system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 124system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 125system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses 126system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses |
| 127system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 120system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits 124system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits 127system.cpu.dcache.overall_hits::total 530720441 # number of overall hits --- 72 unchanged lines hidden (view full) --- 200system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency 202system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency 204system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency 206system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency | 128system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits 129system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits 130system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits 131system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits 132system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits 133system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits 134system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits 135system.cpu.dcache.overall_hits::total 530720441 # number of overall hits --- 72 unchanged lines hidden (view full) --- 208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency 212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 213system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency 214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 215system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency |
| 216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 208system.cpu.icache.tags.replacements 1253 # number of replacements 209system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use 210system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. 211system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 212system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. 213system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 214system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor 215system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy 216system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy 217system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 218system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 219system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses 225system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses | 217system.cpu.icache.tags.replacements 1253 # number of replacements 218system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use 219system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. 220system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 221system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. 222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 223system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor 224system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy 225system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy 226system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 227system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 229system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 232system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 233system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses 234system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses |
| 235system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 226system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits 227system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits 228system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits 230system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits 231system.cpu.icache.overall_hits::total 1068307822 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency | 236system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits 237system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits 238system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits 239system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits 240system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits 241system.cpu.icache.overall_hits::total 1068307822 # number of overall hits 242system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 243system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 296system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 297system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 298system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency 300system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency 302system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency |
| 304system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 294system.cpu.l2cache.tags.replacements 348438 # number of replacements 295system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use 296system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. 297system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. 298system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. 299system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. 300system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor 301system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor --- 5 unchanged lines hidden (view full) --- 307system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id 308system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id 312system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id 313system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses 314system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses | 305system.cpu.l2cache.tags.replacements 348438 # number of replacements 306system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use 307system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. 308system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. 309system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. 310system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. 311system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor 312system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor --- 5 unchanged lines hidden (view full) --- 318system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id 319system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id 322system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id 323system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id 324system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses 325system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses |
| 326system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 315system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits 316system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits 317system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits 318system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits 319system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits 320system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits 321system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits 322system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 453system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency 455system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 327system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits 328system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits 329system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits 330system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits 331system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits 332system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits 333system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits 334system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 465system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 466system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency 467system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. 468system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 469system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 470system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. 471system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 472system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 473system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 461system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 485system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram 487system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) 488system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 489system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 490system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 491system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) 492system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) | 474system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 498system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram 500system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) 501system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 502system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 503system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 504system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) 505system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 506system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states |
|
| 493system.membus.trans_dist::ReadResp 174499 # Transaction distribution 494system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution 495system.membus.trans_dist::CleanEvict 53507 # Transaction distribution 496system.membus.trans_dist::ReadExReq 206356 # Transaction distribution 497system.membus.trans_dist::ReadExResp 206356 # Transaction distribution 498system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution 499system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) 500system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden --- | 507system.membus.trans_dist::ReadResp 174499 # Transaction distribution 508system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution 509system.membus.trans_dist::CleanEvict 53507 # Transaction distribution 510system.membus.trans_dist::ReadExReq 206356 # Transaction distribution 511system.membus.trans_dist::ReadExResp 206356 # Transaction distribution 512system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution 513system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) 514system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden --- |