| stats.txt (11390:f40859930028) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.650501 # Number of seconds simulated 4sim_ticks 1650501252500 # Number of ticks simulated 5final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.650501 # Number of seconds simulated 4sim_ticks 1650501252500 # Number of ticks simulated 5final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 239314 # Simulator instruction rate (inst/s) 8host_op_rate 442851 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 477703969 # Simulator tick rate (ticks/s) 10host_mem_usage 314168 # Number of bytes of host memory used 11host_seconds 3455.07 # Real time elapsed on the host | 7host_inst_rate 691787 # Simulator instruction rate (inst/s) 8host_op_rate 1280153 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1380901785 # Simulator tick rate (ticks/s) 10host_mem_usage 282548 # Number of bytes of host memory used 11host_seconds 1195.23 # Real time elapsed on the host |
| 12sim_insts 826847304 # Number of instructions simulated 13sim_ops 1530082521 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory --- 146 unchanged lines hidden (view full) --- 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 826847304 # Number of instructions simulated 13sim_ops 1530082521 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory --- 146 unchanged lines hidden (view full) --- 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 174system.cpu.dcache.fast_writes 0 # number of fast writes performed 175system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 176system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks 177system.cpu.dcache.writebacks::total 2325221 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses 182system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses 183system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses --- 18 unchanged lines hidden (view full) --- 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency 203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency 205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 207system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 209system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency | 174system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks 175system.cpu.dcache.writebacks::total 2325221 # number of writebacks 176system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses 177system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses 178system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses 180system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses 181system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses --- 18 unchanged lines hidden (view full) --- 200system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency 202system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency 204system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency 206system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency |
| 210system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 211system.cpu.icache.tags.replacements 1253 # number of replacements 212system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use 213system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. 214system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 215system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. 216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 217system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor 218system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 263system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency 264system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency 265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 208system.cpu.icache.tags.replacements 1253 # number of replacements 209system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use 210system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. 211system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 212system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. 213system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 214system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor 215system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 271system.cpu.icache.fast_writes 0 # number of fast writes performed 272system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 273system.cpu.icache.writebacks::writebacks 1253 # number of writebacks 274system.cpu.icache.writebacks::total 1253 # number of writebacks 275system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 276system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 277system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 278system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 279system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 280system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 291system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 292system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 293system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency 294system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency 295system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 296system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency 297system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 298system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency | 268system.cpu.icache.writebacks::writebacks 1253 # number of writebacks 269system.cpu.icache.writebacks::total 1253 # number of writebacks 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency |
| 299system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 300system.cpu.l2cache.tags.replacements 348438 # number of replacements 301system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use 302system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. 303system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. 304system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. 305system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. 306system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor 307system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor --- 91 unchanged lines hidden (view full) --- 399system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency 400system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency 401system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 294system.cpu.l2cache.tags.replacements 348438 # number of replacements 295system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use 296system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. 297system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. 298system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. 299system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. 300system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor 301system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor --- 91 unchanged lines hidden (view full) --- 393system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency 394system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency 395system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 407system.cpu.l2cache.fast_writes 0 # number of fast writes performed 408system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 409system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks 410system.cpu.l2cache.writebacks::total 293208 # number of writebacks 411system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses 412system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses 413system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses 414system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses 415system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses 416system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 455system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency 456system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency 457system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency 458system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 459system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency 460system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency 461system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 462system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency | 401system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks 402system.cpu.l2cache.writebacks::total 293208 # number of writebacks 403system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses 404system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses 405system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses 406system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses 407system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses 408system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 447system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency 448system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency 449system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency 450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 451system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency 452system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency |
| 463system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 464system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. 465system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 466system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 467system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. 468system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 469system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 470system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution --- 59 unchanged lines hidden --- | 455system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 461system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution --- 59 unchanged lines hidden --- |