Cross Reference: /gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 1.650527 # Number of seconds simulated
4sim_ticks 1650526667500 # Number of ticks simulated
5final_tick 1650526667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 1.650601 # Number of seconds simulated
4sim_ticks 1650600522500 # Number of ticks simulated
5final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 726731 # Simulator instruction rate (inst/s)
8host_op_rate 1343807 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1450624585 # Simulator tick rate (ticks/s)
10host_mem_usage 327760 # Number of bytes of host memory used
11host_seconds 1137.80 # Real time elapsed on the host
12sim_insts 826877110 # Number of instructions simulated
13sim_ops 1528988702 # Number of ops (including micro ops) simulated

7host_inst_rate 236277 # Simulator instruction rate (inst/s)
8host_op_rate 436901 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 471636555 # Simulator tick rate (ticks/s)
10host_mem_usage 314152 # Number of bytes of host memory used
11host_seconds 3499.73 # Real time elapsed on the host
12sim_insts 826906380 # Number of instructions simulated
13sim_ops 1529035683 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory

17system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory

17system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory

19system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory

21system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
22system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory

21system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory
22system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory

23system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory

24system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 70145 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 14697699 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 14767844 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 70145 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 70145 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 11369249 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 11369249 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 11369249 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 70145 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 14697699 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 26137092 # Total bandwidth to/from this memory (bytes/s)

24system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s)

39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
41system.cpu.workload.num_syscalls 551 # Number of system calls

42system.cpu.numCycles 3301053335 # number of cpu cycles simulated

42system.cpu.numCycles 3301201045 # number of cpu cycles simulated

43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

45system.cpu.committedInsts 826877110 # Number of instructions committed
46system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
47system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses

45system.cpu.committedInsts 826906380 # Number of instructions committed
46system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
47system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses

48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
49system.cpu.num_func_calls 35346287 # number of times a function call or return occured

50system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
51system.cpu.num_int_insts 1526605510 # number of integer instructions

50system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
51system.cpu.num_int_insts 1526653037 # number of integer instructions

52system.cpu.num_fp_insts 0 # number of float instructions

53system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
54system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written

53system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
54system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written

55system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
56system.cpu.num_fp_register_writes 0 # number of times the floating registers were written

57system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
58system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
59system.cpu.num_mem_refs 533262343 # number of memory refs
60system.cpu.num_load_insts 384102157 # Number of load instructions
61system.cpu.num_store_insts 149160186 # Number of store instructions

57system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
58system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
59system.cpu.num_mem_refs 533282319 # number of memory refs
60system.cpu.num_load_insts 384117825 # Number of load instructions
61system.cpu.num_store_insts 149164494 # Number of store instructions

62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

63system.cpu.num_busy_cycles 3301053334.998000 # Number of busy cycles

63system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles

64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles

66system.cpu.Branches 149758583 # Number of branches fetched
67system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
68system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction

66system.cpu.Branches 149762544 # Number of branches fetched
67system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
68system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction

69system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction

70system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction

70system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction

71system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
72system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
73system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
74system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
75system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
76system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
77system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
78system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction

--- 10 unchanged lines hidden (view full) ---

89system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
90system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
91system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
92system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
93system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
94system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
96system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction

97system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction
98system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction

97system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
98system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction

99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

101system.cpu.op_class::total 1528988702 # Class of executed instruction
102system.cpu.dcache.tags.replacements 2514362 # number of replacements
103system.cpu.dcache.tags.tagsinuse 4086.386622 # Cycle average of tags in use
104system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
105system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
106system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.

101system.cpu.op_class::total 1529035683 # Class of executed instruction
102system.cpu.dcache.tags.replacements 2515885 # number of replacements
103system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use
104system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks.
105system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks.
106system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks.

107system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.

108system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386622 # Average occupied blocks per requestor

108system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor

109system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
110system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
112system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
113system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
114system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
115system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

118system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
119system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
120system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
121system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
122system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
123system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
124system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
125system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
126system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
127system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
128system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
129system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
130system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
131system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
132system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
133system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
134system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
135system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
136system.cpu.dcache.ReadReq_miss_latency::cpu.data 30918235500 # number of ReadReq miss cycles
137system.cpu.dcache.ReadReq_miss_latency::total 30918235500 # number of ReadReq miss cycles
138system.cpu.dcache.WriteReq_miss_latency::cpu.data 20395021500 # number of WriteReq miss cycles
139system.cpu.dcache.WriteReq_miss_latency::total 20395021500 # number of WriteReq miss cycles
140system.cpu.dcache.demand_miss_latency::cpu.data 51313257000 # number of demand (read+write) miss cycles
141system.cpu.dcache.demand_miss_latency::total 51313257000 # number of demand (read+write) miss cycles
142system.cpu.dcache.overall_miss_latency::cpu.data 51313257000 # number of overall miss cycles
143system.cpu.dcache.overall_miss_latency::total 51313257000 # number of overall miss cycles
144system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
145system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
146system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
147system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
148system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
149system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
150system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
151system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
153system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
155system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
156system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
157system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
158system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
159system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165 # average ReadReq miss latency
161system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165 # average ReadReq miss latency
162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966 # average WriteReq miss latency
163system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966 # average WriteReq miss latency
164system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency
165system.cpu.dcache.demand_avg_miss_latency::total 20374.871052 # average overall miss latency
166system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency
167system.cpu.dcache.overall_avg_miss_latency::total 20374.871052 # average overall miss latency

118system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses
119system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses
120system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits
121system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits
122system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits
123system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits
124system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits
125system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits
126system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits
127system.cpu.dcache.overall_hits::total 530762383 # number of overall hits
128system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses
129system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses
130system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses
131system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses
132system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses
133system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses
134system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses
135system.cpu.dcache.overall_misses::total 2519981 # number of overall misses
136system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles
137system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles
138system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles
139system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles
140system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles
141system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles
142system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles
143system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles
144system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses)
145system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses)
146system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses)
147system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses)
148system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses
149system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses
150system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses
151system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses
152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses
153system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses
154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses
155system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses
156system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses
157system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses
158system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses
159system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses
160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency
161system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency
162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency
163system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency
164system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
165system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency
166system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
167system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency

168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
174system.cpu.dcache.fast_writes 0 # number of fast writes performed
175system.cpu.dcache.cache_copies 0 # number of cache copies performed

176system.cpu.dcache.writebacks::writebacks 2323200 # number of writebacks
177system.cpu.dcache.writebacks::total 2323200 # number of writebacks
178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
179system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
181system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
182system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
183system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
184system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
185system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
186system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29190821500 # number of ReadReq MSHR miss cycles
187system.cpu.dcache.ReadReq_mshr_miss_latency::total 29190821500 # number of ReadReq MSHR miss cycles
188system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19603977500 # number of WriteReq MSHR miss cycles
189system.cpu.dcache.WriteReq_mshr_miss_latency::total 19603977500 # number of WriteReq MSHR miss cycles
190system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48794799000 # number of demand (read+write) MSHR miss cycles
191system.cpu.dcache.demand_mshr_miss_latency::total 48794799000 # number of demand (read+write) MSHR miss cycles
192system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48794799000 # number of overall MSHR miss cycles
193system.cpu.dcache.overall_mshr_miss_latency::total 48794799000 # number of overall MSHR miss cycles
194system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
195system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
196system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
197system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
198system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
199system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
200system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
201system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165 # average ReadReq mshr miss latency
203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165 # average ReadReq mshr miss latency
204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966 # average WriteReq mshr miss latency
205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966 # average WriteReq mshr miss latency
206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency
207system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency
208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency
209system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency

176system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks
177system.cpu.dcache.writebacks::total 2324237 # number of writebacks
178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses
179system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses
180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses
181system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses
182system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses
183system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses
184system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses
185system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses
186system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles
187system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles
188system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles
189system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles
190system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles
191system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles
192system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles
193system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles
194system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses
195system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses
196system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses
197system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses
198system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses
199system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses
200system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses
201system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses
202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency
203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency
204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency
205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency
206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
207system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
209system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency

210system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
211system.cpu.icache.tags.replacements 1253 # number of replacements

212system.cpu.icache.tags.tagsinuse 881.361122 # Cycle average of tags in use
213system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks.

212system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use
213system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks.

214system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.

215system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks.

215system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks.

216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

217system.cpu.icache.tags.occ_blocks::cpu.inst 881.361122 # Average occupied blocks per requestor
218system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
219system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy

217system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor
218system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy
219system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy

220system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
221system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
222system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
223system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
224system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
225system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
226system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id

227system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses
228system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses
229system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits
230system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits
231system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits
232system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits
233system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits
234system.cpu.icache.overall_hits::total 1068344251 # number of overall hits

227system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses
228system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses
229system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits
230system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits
231system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits
232system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits
233system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits
234system.cpu.icache.overall_hits::total 1068379901 # number of overall hits

235system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
236system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
237system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
238system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
239system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
240system.cpu.icache.overall_misses::total 2814 # number of overall misses

241system.cpu.icache.ReadReq_miss_latency::cpu.inst 125252000 # number of ReadReq miss cycles
242system.cpu.icache.ReadReq_miss_latency::total 125252000 # number of ReadReq miss cycles
243system.cpu.icache.demand_miss_latency::cpu.inst 125252000 # number of demand (read+write) miss cycles
244system.cpu.icache.demand_miss_latency::total 125252000 # number of demand (read+write) miss cycles
245system.cpu.icache.overall_miss_latency::cpu.inst 125252000 # number of overall miss cycles
246system.cpu.icache.overall_miss_latency::total 125252000 # number of overall miss cycles
247system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses)
248system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses)
249system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses
250system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses
251system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses
252system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses

241system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles
242system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles
243system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles
244system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles
245system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles
246system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles
247system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses)
248system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses)
249system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses
250system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses
251system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses
252system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses

253system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
254system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
255system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
256system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
257system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
258system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses

259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615 # average ReadReq miss latency
260system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615 # average ReadReq miss latency
261system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency
262system.cpu.icache.demand_avg_miss_latency::total 44510.305615 # average overall miss latency
263system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency
264system.cpu.icache.overall_avg_miss_latency::total 44510.305615 # average overall miss latency

259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency
260system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency
261system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
262system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency
263system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
264system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency

265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
271system.cpu.icache.fast_writes 0 # number of fast writes performed
272system.cpu.icache.cache_copies 0 # number of cache copies performed
273system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
274system.cpu.icache.writebacks::total 1253 # number of writebacks
275system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
276system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
277system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
278system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
279system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
280system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses

281system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122438000 # number of ReadReq MSHR miss cycles
282system.cpu.icache.ReadReq_mshr_miss_latency::total 122438000 # number of ReadReq MSHR miss cycles
283system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122438000 # number of demand (read+write) MSHR miss cycles
284system.cpu.icache.demand_mshr_miss_latency::total 122438000 # number of demand (read+write) MSHR miss cycles
285system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122438000 # number of overall MSHR miss cycles
286system.cpu.icache.overall_mshr_miss_latency::total 122438000 # number of overall MSHR miss cycles

281system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles
282system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles
283system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles
284system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles
285system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles
286system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles

287system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
288system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
289system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
290system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
291system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
292system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses

293system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43510.305615 # average ReadReq mshr miss latency
294system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43510.305615 # average ReadReq mshr miss latency
295system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency
296system.cpu.icache.demand_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency
297system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency
298system.cpu.icache.overall_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency

293system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.727079 # average ReadReq mshr miss latency
294system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.727079 # average ReadReq mshr miss latency
295system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
296system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency
297system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
298system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency

299system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

300system.cpu.l2cache.tags.replacements 348438 # number of replacements
301system.cpu.l2cache.tags.tagsinuse 29288.473875 # Cycle average of tags in use
302system.cpu.l2cache.tags.total_refs 3847001 # Total number of references to valid blocks.
303system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
304system.cpu.l2cache.tags.avg_refs 10.102472 # Average number of references to valid blocks.

300system.cpu.l2cache.tags.replacements 348437 # number of replacements
301system.cpu.l2cache.tags.tagsinuse 29288.556947 # Cycle average of tags in use
302system.cpu.l2cache.tags.total_refs 3849932 # Total number of references to valid blocks.
303system.cpu.l2cache.tags.sampled_refs 380797 # Sample count of references to valid blocks.
304system.cpu.l2cache.tags.avg_refs 10.110195 # Average number of references to valid blocks.

305system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.

306system.cpu.l2cache.tags.occ_blocks::writebacks 20940.344841 # Average occupied blocks per requestor
307system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.252047 # Average occupied blocks per requestor
308system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.876987 # Average occupied blocks per requestor
309system.cpu.l2cache.tags.occ_percent::writebacks 0.639049 # Average percentage of cache occupancy
310system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004005 # Average percentage of cache occupancy
311system.cpu.l2cache.tags.occ_percent::cpu.data 0.250759 # Average percentage of cache occupancy
312system.cpu.l2cache.tags.occ_percent::total 0.893813 # Average percentage of cache occupancy

306system.cpu.l2cache.tags.occ_blocks::writebacks 20940.547795 # Average occupied blocks per requestor
307system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.260188 # Average occupied blocks per requestor
308system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.748964 # Average occupied blocks per requestor
309system.cpu.l2cache.tags.occ_percent::writebacks 0.639055 # Average percentage of cache occupancy
310system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
311system.cpu.l2cache.tags.occ_percent::cpu.data 0.250755 # Average percentage of cache occupancy
312system.cpu.l2cache.tags.occ_percent::total 0.893816 # Average percentage of cache occupancy

313system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
314system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
315system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id

316system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
317system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id

316system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8218 # Occupied blocks per task id
317system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24062 # Occupied blocks per task id

318system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id

319system.cpu.l2cache.tags.tag_accesses 41466938 # Number of tag accesses
320system.cpu.l2cache.tags.data_accesses 41466938 # Number of data accesses
321system.cpu.l2cache.WritebackDirty_hits::writebacks 2323200 # number of WritebackDirty hits
322system.cpu.l2cache.WritebackDirty_hits::total 2323200 # number of WritebackDirty hits

319system.cpu.l2cache.tags.tag_accesses 41491408 # Number of tag accesses
320system.cpu.l2cache.tags.data_accesses 41491408 # Number of data accesses
321system.cpu.l2cache.WritebackDirty_hits::writebacks 2324237 # number of WritebackDirty hits
322system.cpu.l2cache.WritebackDirty_hits::total 2324237 # number of WritebackDirty hits

323system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
324system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits

325system.cpu.l2cache.ReadExReq_hits::cpu.data 584688 # number of ReadExReq hits
326system.cpu.l2cache.ReadExReq_hits::total 584688 # number of ReadExReq hits

325system.cpu.l2cache.ReadExReq_hits::cpu.data 584791 # number of ReadExReq hits
326system.cpu.l2cache.ReadExReq_hits::total 584791 # number of ReadExReq hits

327system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
328system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits

329system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554724 # number of ReadSharedReq hits
330system.cpu.l2cache.ReadSharedReq_hits::total 1554724 # number of ReadSharedReq hits

329system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556145 # number of ReadSharedReq hits
330system.cpu.l2cache.ReadSharedReq_hits::total 1556145 # number of ReadSharedReq hits

331system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits

332system.cpu.l2cache.demand_hits::cpu.data 2139412 # number of demand (read+write) hits
333system.cpu.l2cache.demand_hits::total 2140417 # number of demand (read+write) hits

332system.cpu.l2cache.demand_hits::cpu.data 2140936 # number of demand (read+write) hits
333system.cpu.l2cache.demand_hits::total 2141941 # number of demand (read+write) hits

334system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits

335system.cpu.l2cache.overall_hits::cpu.data 2139412 # number of overall hits
336system.cpu.l2cache.overall_hits::total 2140417 # number of overall hits

335system.cpu.l2cache.overall_hits::cpu.data 2140936 # number of overall hits
336system.cpu.l2cache.overall_hits::total 2141941 # number of overall hits

337system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
338system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
339system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
340system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses

341system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses
342system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses

341system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172689 # number of ReadSharedReq misses
342system.cpu.l2cache.ReadSharedReq_misses::total 172689 # number of ReadSharedReq misses

343system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses

344system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
345system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses

344system.cpu.l2cache.demand_misses::cpu.data 379045 # number of demand (read+write) misses
345system.cpu.l2cache.demand_misses::total 380854 # number of demand (read+write) misses

346system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses

347system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
348system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
349system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278187500 # number of ReadExReq miss cycles
350system.cpu.l2cache.ReadExReq_miss_latency::total 12278187500 # number of ReadExReq miss cycles
351system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107652500 # number of ReadCleanReq miss cycles
352system.cpu.l2cache.ReadCleanReq_miss_latency::total 107652500 # number of ReadCleanReq miss cycles
353system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
354system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
355system.cpu.l2cache.demand_miss_latency::cpu.inst 107652500 # number of demand (read+write) miss cycles
356system.cpu.l2cache.demand_miss_latency::cpu.data 22553283000 # number of demand (read+write) miss cycles
357system.cpu.l2cache.demand_miss_latency::total 22660935500 # number of demand (read+write) miss cycles
358system.cpu.l2cache.overall_miss_latency::cpu.inst 107652500 # number of overall miss cycles
359system.cpu.l2cache.overall_miss_latency::cpu.data 22553283000 # number of overall miss cycles
360system.cpu.l2cache.overall_miss_latency::total 22660935500 # number of overall miss cycles
361system.cpu.l2cache.WritebackDirty_accesses::writebacks 2323200 # number of WritebackDirty accesses(hits+misses)
362system.cpu.l2cache.WritebackDirty_accesses::total 2323200 # number of WritebackDirty accesses(hits+misses)

347system.cpu.l2cache.overall_misses::cpu.data 379045 # number of overall misses
348system.cpu.l2cache.overall_misses::total 380854 # number of overall misses
349system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles
350system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
351system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107657000 # number of ReadCleanReq miss cycles
352system.cpu.l2cache.ReadCleanReq_miss_latency::total 107657000 # number of ReadCleanReq miss cycles
353system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275036000 # number of ReadSharedReq miss cycles
354system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275036000 # number of ReadSharedReq miss cycles
355system.cpu.l2cache.demand_miss_latency::cpu.inst 107657000 # number of demand (read+write) miss cycles
356system.cpu.l2cache.demand_miss_latency::cpu.data 22553221500 # number of demand (read+write) miss cycles
357system.cpu.l2cache.demand_miss_latency::total 22660878500 # number of demand (read+write) miss cycles
358system.cpu.l2cache.overall_miss_latency::cpu.inst 107657000 # number of overall miss cycles
359system.cpu.l2cache.overall_miss_latency::cpu.data 22553221500 # number of overall miss cycles
360system.cpu.l2cache.overall_miss_latency::total 22660878500 # number of overall miss cycles
361system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324237 # number of WritebackDirty accesses(hits+misses)
362system.cpu.l2cache.WritebackDirty_accesses::total 2324237 # number of WritebackDirty accesses(hits+misses)

363system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
364system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)

365system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
366system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)

365system.cpu.l2cache.ReadExReq_accesses::cpu.data 791147 # number of ReadExReq accesses(hits+misses)
366system.cpu.l2cache.ReadExReq_accesses::total 791147 # number of ReadExReq accesses(hits+misses)

367system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
368system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)

369system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1727414 # number of ReadSharedReq accesses(hits+misses)
370system.cpu.l2cache.ReadSharedReq_accesses::total 1727414 # number of ReadSharedReq accesses(hits+misses)

369system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1728834 # number of ReadSharedReq accesses(hits+misses)
370system.cpu.l2cache.ReadSharedReq_accesses::total 1728834 # number of ReadSharedReq accesses(hits+misses)

371system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses

372system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
373system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses

372system.cpu.l2cache.demand_accesses::cpu.data 2519981 # number of demand (read+write) accesses
373system.cpu.l2cache.demand_accesses::total 2522795 # number of demand (read+write) accesses

374system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses

375system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
376system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
377system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260865 # miss rate for ReadExReq accesses
378system.cpu.l2cache.ReadExReq_miss_rate::total 0.260865 # miss rate for ReadExReq accesses

375system.cpu.l2cache.overall_accesses::cpu.data 2519981 # number of overall (read+write) accesses
376system.cpu.l2cache.overall_accesses::total 2522795 # number of overall (read+write) accesses
377system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260831 # miss rate for ReadExReq accesses
378system.cpu.l2cache.ReadExReq_miss_rate::total 0.260831 # miss rate for ReadExReq accesses

379system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
380system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses

381system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099970 # miss rate for ReadSharedReq accesses
382system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099970 # miss rate for ReadSharedReq accesses

381system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099888 # miss rate for ReadSharedReq accesses
382system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099888 # miss rate for ReadSharedReq accesses

383system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses

384system.cpu.l2cache.demand_miss_rate::cpu.data 0.150507 # miss rate for demand accesses
385system.cpu.l2cache.demand_miss_rate::total 0.151057 # miss rate for demand accesses

384system.cpu.l2cache.demand_miss_rate::cpu.data 0.150416 # miss rate for demand accesses
385system.cpu.l2cache.demand_miss_rate::total 0.150965 # miss rate for demand accesses

386system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses

387system.cpu.l2cache.overall_miss_rate::cpu.data 0.150507 # miss rate for overall accesses
388system.cpu.l2cache.overall_miss_rate::total 0.151057 # miss rate for overall accesses
389system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.026653 # average ReadExReq miss latency
390system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.026653 # average ReadExReq miss latency
391system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59509.397457 # average ReadCleanReq miss latency
392system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59509.397457 # average ReadCleanReq miss latency
393system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
394system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
395system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59509.397457 # average overall miss latency
396system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.121357 # average overall miss latency
397system.cpu.l2cache.demand_avg_miss_latency::total 59500.165417 # average overall miss latency
398system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59509.397457 # average overall miss latency
399system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.121357 # average overall miss latency
400system.cpu.l2cache.overall_avg_miss_latency::total 59500.165417 # average overall miss latency

387system.cpu.l2cache.overall_miss_rate::cpu.data 0.150416 # miss rate for overall accesses
388system.cpu.l2cache.overall_miss_rate::total 0.150965 # miss rate for overall accesses
389system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
390system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
391system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.885019 # average ReadCleanReq miss latency
392system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.885019 # average ReadCleanReq miss latency
393system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234526 # average ReadSharedReq miss latency
394system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234526 # average ReadSharedReq miss latency
395system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency
396system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
397system.cpu.l2cache.demand_avg_miss_latency::total 59500.171982 # average overall miss latency
398system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency
399system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
400system.cpu.l2cache.overall_avg_miss_latency::total 59500.171982 # average overall miss latency

401system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
402system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
403system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
404system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
405system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
406system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
407system.cpu.l2cache.fast_writes 0 # number of fast writes performed
408system.cpu.l2cache.cache_copies 0 # number of cache copies performed

409system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
410system.cpu.l2cache.writebacks::total 293208 # number of writebacks

409system.cpu.l2cache.writebacks::writebacks 293207 # number of writebacks
410system.cpu.l2cache.writebacks::total 293207 # number of writebacks

411system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
412system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
413system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
414system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
415system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
416system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses

417system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
418system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses

417system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172689 # number of ReadSharedReq MSHR misses
418system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172689 # number of ReadSharedReq MSHR misses

419system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses

420system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
421system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses

420system.cpu.l2cache.demand_mshr_misses::cpu.data 379045 # number of demand (read+write) MSHR misses
421system.cpu.l2cache.demand_mshr_misses::total 380854 # number of demand (read+write) MSHR misses

422system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses

423system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
424system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
425system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214627500 # number of ReadExReq MSHR miss cycles
426system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214627500 # number of ReadExReq MSHR miss cycles
427system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89562500 # number of ReadCleanReq MSHR miss cycles
428system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89562500 # number of ReadCleanReq MSHR miss cycles
429system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
430system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
431system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89562500 # number of demand (read+write) MSHR miss cycles
432system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762823000 # number of demand (read+write) MSHR miss cycles
433system.cpu.l2cache.demand_mshr_miss_latency::total 18852385500 # number of demand (read+write) MSHR miss cycles
434system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89562500 # number of overall MSHR miss cycles
435system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762823000 # number of overall MSHR miss cycles
436system.cpu.l2cache.overall_mshr_miss_latency::total 18852385500 # number of overall MSHR miss cycles

423system.cpu.l2cache.overall_mshr_misses::cpu.data 379045 # number of overall MSHR misses
424system.cpu.l2cache.overall_mshr_misses::total 380854 # number of overall MSHR misses
425system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
426system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
427system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89567000 # number of ReadCleanReq MSHR miss cycles
428system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89567000 # number of ReadCleanReq MSHR miss cycles
429system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548146000 # number of ReadSharedReq MSHR miss cycles
430system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548146000 # number of ReadSharedReq MSHR miss cycles
431system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89567000 # number of demand (read+write) MSHR miss cycles
432system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762771500 # number of demand (read+write) MSHR miss cycles
433system.cpu.l2cache.demand_mshr_miss_latency::total 18852338500 # number of demand (read+write) MSHR miss cycles
434system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89567000 # number of overall MSHR miss cycles
435system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762771500 # number of overall MSHR miss cycles
436system.cpu.l2cache.overall_mshr_miss_latency::total 18852338500 # number of overall MSHR miss cycles

437system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
438system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

439system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260865 # mshr miss rate for ReadExReq accesses
440system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260865 # mshr miss rate for ReadExReq accesses

439system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260831 # mshr miss rate for ReadExReq accesses
440system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260831 # mshr miss rate for ReadExReq accesses

441system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
442system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses

443system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099970 # mshr miss rate for ReadSharedReq accesses
444system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099970 # mshr miss rate for ReadSharedReq accesses

443system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses
444system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses

445system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses

446system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for demand accesses
447system.cpu.l2cache.demand_mshr_miss_rate::total 0.151057 # mshr miss rate for demand accesses

446system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses
447system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses

448system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses

449system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for overall accesses
450system.cpu.l2cache.overall_mshr_miss_rate::total 0.151057 # mshr miss rate for overall accesses
451system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653 # average ReadExReq mshr miss latency
452system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653 # average ReadExReq mshr miss latency
453system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457 # average ReadCleanReq mshr miss latency
454system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457 # average ReadCleanReq mshr miss latency
455system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
456system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
457system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency
458system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency
459system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency
460system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency
461system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency
462system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency

449system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for overall accesses
450system.cpu.l2cache.overall_mshr_miss_rate::total 0.150965 # mshr miss rate for overall accesses
451system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
452system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
453system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.885019 # average ReadCleanReq mshr miss latency
454system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency
455system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency
456system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency
457system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
458system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
459system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency
460system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
461system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
462system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency

463system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

464system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter.
465system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data.

464system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter.
465system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data.

466system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
467system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
468system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
469system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

470system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::WritebackDirty 2616408 # Transaction distribution

470system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution

472system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution

473system.cpu.toL2Bus.trans_dist::CleanEvict 246392 # Transaction distribution
474system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
475system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution

473system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution
474system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution
475system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution

476system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution

477system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution

477system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution

478system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)

479system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes)
480system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes)

479system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes)
480system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes)

481system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)

482system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309866112 # Cumulative packet size per connected master and slave (bytes)
483system.cpu.toL2Bus.pkt_size::total 310126400 # Cumulative packet size per connected master and slave (bytes)
484system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
485system.cpu.toL2Bus.snoop_fanout::samples 2869710 # Request fanout histogram

482system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes)
483system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes)
484system.cpu.toL2Bus.snoops 348437 # Total snoops (count)
485system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram

486system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram

487system.cpu.toL2Bus.snoop_fanout::stdev 0.024538 # Request fanout histogram

487system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram

488system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

489system.cpu.toL2Bus.snoop_fanout::0 2867981 99.94% 99.94% # Request fanout histogram

489system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram

490system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
492system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
493system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
494system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

495system.cpu.toL2Bus.snoop_fanout::total 2869710 # Request fanout histogram
496system.cpu.toL2Bus.reqLayer0.occupancy 4842896500 # Layer occupancy (ticks)

495system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram
496system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks)

497system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
498system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
499system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

500system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)

500system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks)

501system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

502system.membus.trans_dist::ReadResp 174499 # Transaction distribution
503system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution

502system.membus.trans_dist::ReadResp 174498 # Transaction distribution
503system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution

504system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
505system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
506system.membus.trans_dist::ReadExResp 206356 # Transaction distribution

507system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
508system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
509system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
510system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
511system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
512system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
513system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)

507system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution
508system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes)
509system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes)
510system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes)
511system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes)
512system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes)
513system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes)

514system.membus.snoops 0 # Total snoops (count)

515system.membus.snoop_fanout::samples 727569 # Request fanout histogram

515system.membus.snoop_fanout::samples 727567 # Request fanout histogram

516system.membus.snoop_fanout::mean 0 # Request fanout histogram
517system.membus.snoop_fanout::stdev 0 # Request fanout histogram
518system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

519system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram

519system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram

520system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
521system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
522system.membus.snoop_fanout::min_value 0 # Request fanout histogram
523system.membus.snoop_fanout::max_value 0 # Request fanout histogram

524system.membus.snoop_fanout::total 727569 # Request fanout histogram
525system.membus.reqLayer0.occupancy 1900428500 # Layer occupancy (ticks)

524system.membus.snoop_fanout::total 727567 # Request fanout histogram
525system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks)

526system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

527system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)

527system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks)