| stats.txt (10488:7c27480a5031) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated |
| 4sim_ticks 1647872849000 # Number of ticks simulated 5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1647872738500 # Number of ticks simulated 5final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 845545 # Simulator instruction rate (inst/s) 8host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1685075999 # Simulator tick rate (ticks/s) 10host_mem_usage 318276 # Number of bytes of host memory used 11host_seconds 977.92 # Real time elapsed on the host | 7host_inst_rate 730118 # Simulator instruction rate (inst/s) 8host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1455043701 # Simulator tick rate (ticks/s) 10host_mem_usage 323120 # Number of bytes of host memory used 11host_seconds 1132.52 # Real time elapsed on the host |
| 12sim_insts 826877110 # Number of instructions simulated 13sim_ops 1528988702 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) | 12sim_insts 826877110 # Number of instructions simulated 13sim_ops 1528988702 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) |
| 29system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) | 29system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s) |
| 31system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) | 31system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) | 33system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s) |
| 36system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) | 36system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) |
| 37system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) 39system.membus.trans_dist::ReadReq 174452 # Transaction distribution 40system.membus.trans_dist::ReadResp 174452 # Transaction distribution 41system.membus.trans_dist::Writeback 292286 # Transaction distribution 42system.membus.trans_dist::ReadExReq 206691 # Transaction distribution 43system.membus.trans_dist::ReadExResp 206691 # Transaction distribution 44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) 47system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) 48system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) 49system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) 50system.membus.snoops 0 # Total snoops (count) 51system.membus.snoop_fanout::samples 673429 # Request fanout histogram 52system.membus.snoop_fanout::mean 0 # Request fanout histogram 53system.membus.snoop_fanout::stdev 0 # Request fanout histogram 54system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 55system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram 56system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 57system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 58system.membus.snoop_fanout::min_value 0 # Request fanout histogram 59system.membus.snoop_fanout::max_value 0 # Request fanout histogram 60system.membus.snoop_fanout::total 673429 # Request fanout histogram 61system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) 62system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 63system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) 64system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 37system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s) |
| 65system.cpu_clk_domain.clock 500 # Clock period in ticks 66system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 67system.cpu.workload.num_syscalls 551 # Number of system calls | 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 551 # Number of system calls |
| 68system.cpu.numCycles 3295745698 # number of cpu cycles simulated | 42system.cpu.numCycles 3295745477 # number of cpu cycles simulated |
| 69system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 70system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 71system.cpu.committedInsts 826877110 # Number of instructions committed 72system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed 73system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses 74system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 75system.cpu.num_func_calls 35346287 # number of times a function call or return occured 76system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 81system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written 85system.cpu.num_mem_refs 533262343 # number of memory refs 86system.cpu.num_load_insts 384102157 # Number of load instructions 87system.cpu.num_store_insts 149160186 # Number of store instructions 88system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 826877110 # Number of instructions committed 46system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 49system.cpu.num_func_calls 35346287 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 55system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written 59system.cpu.num_mem_refs 533262343 # number of memory refs 60system.cpu.num_load_insts 384102157 # Number of load instructions 61system.cpu.num_store_insts 149160186 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 89system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles | 63system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles |
| 90system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 92system.cpu.Branches 149758583 # Number of branches fetched 93system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction 94system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction 95system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction 96system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction 97system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 120system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction 121system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction 123system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction 124system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 1528988702 # Class of executed instruction | 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 149758583 # Number of branches fetched 67system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction 68system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction 69system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction 70system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction 71system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 94system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction 97system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction 98system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 1528988702 # Class of executed instruction |
| 102system.cpu.dcache.tags.replacements 2514362 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses 120system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits 124system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits 127system.cpu.dcache.overall_hits::total 530743930 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 132system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 133system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 134system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 135system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 136system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles 137system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles 140system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles 141system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles 142system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles 143system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles 144system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses 149system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses 150system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses 151system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses 152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 153system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses 154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 155system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 157system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses 158system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 159system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses 160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency 161system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency 164system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency 165system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.cpu.dcache.fast_writes 0 # number of fast writes performed 175system.cpu.dcache.cache_copies 0 # number of cache copies performed 176system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks 177system.cpu.dcache.writebacks::total 2323523 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses 182system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses 183system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses 184system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses 185system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses 186system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles 193system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles 194system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses 198system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses 199system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses 200system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses 201system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency 203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency 205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency 207system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency 209system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency 210system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 128system.cpu.icache.tags.replacements 1253 # number of replacements | 211system.cpu.icache.tags.replacements 1253 # number of replacements |
| 129system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use | 212system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use |
| 130system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. 131system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 132system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 213system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. 214system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 215system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. 216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 134system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor | 217system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor |
| 135system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 136system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy 137system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 138system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 139system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 140system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 141system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 142system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 150system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits 151system.cpu.icache.overall_hits::total 1068344251 # number of overall hits 152system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 153system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 154system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 155system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 156system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 157system.cpu.icache.overall_misses::total 2814 # number of overall misses | 218system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy 220system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 223system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 224system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 225system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 233system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits 234system.cpu.icache.overall_hits::total 1068344251 # number of overall hits 235system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 236system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 237system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 238system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 239system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 240system.cpu.icache.overall_misses::total 2814 # number of overall misses |
| 158system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles 159system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles 160system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles 161system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles 162system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles 163system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles | 241system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles 242system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles 243system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles 244system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles 245system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles 246system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles |
| 164system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) 165system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) 166system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses 167system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses 168system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses 169system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses 170system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 171system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 172system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 173system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 174system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 175system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses | 247system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) 248system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) 249system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses 250system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses 251system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses 252system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses 253system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 254system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 255system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 256system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 257system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 258system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses |
| 176system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency 177system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency 178system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency 179system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency 180system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency 181system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency | 259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency 260system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency 261system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency 262system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency 263system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency 264system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency |
| 182system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 183system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 184system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 185system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 186system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 187system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 188system.cpu.icache.fast_writes 0 # number of fast writes performed 189system.cpu.icache.cache_copies 0 # number of cache copies performed 190system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 191system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 192system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 193system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 194system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 195system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses | 265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 271system.cpu.icache.fast_writes 0 # number of fast writes performed 272system.cpu.icache.cache_copies 0 # number of cache copies performed 273system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 274system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 275system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 276system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 277system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 278system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses |
| 196system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles 197system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles 198system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles 199system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles 200system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles 201system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles | 279system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles 280system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles 281system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles 282system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles 283system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles 284system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles |
| 202system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 203system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 204system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 205system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 206system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 207system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses | 285system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 286system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 287system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 288system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 289system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 290system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses |
| 208system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency 209system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency 210system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 211system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 212system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 213system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency | 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency 294system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency 296system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency |
| 214system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 215system.cpu.l2cache.tags.replacements 348459 # number of replacements | 297system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 298system.cpu.l2cache.tags.replacements 348459 # number of replacements |
| 216system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use | 299system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use |
| 217system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. 218system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. 219system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. | 300system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. 301system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. 302system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. |
| 220system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. 221system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor 222system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor 223system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor | 303system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit. 304system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor 306system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor |
| 224system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy 225system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy 226system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy 227system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy 228system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id 229system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 230system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 231system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id --- 20 unchanged lines hidden (view full) --- 252system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses 253system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses 254system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses 255system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses 256system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses 257system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses 258system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses 259system.cpu.l2cache.overall_misses::total 381143 # number of overall misses | 307system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy 309system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy 310system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy 311system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id --- 20 unchanged lines hidden (view full) --- 335system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses 336system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses 337system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses 338system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses 339system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses 340system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses 341system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses 342system.cpu.l2cache.overall_misses::total 381143 # number of overall misses |
| 260system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles 261system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles 262system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles 263system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles 264system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles 265system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles 266system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles 267system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles 268system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles 269system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles 270system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles | 343system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles 344system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles 345system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles 346system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles 347system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles 348system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles 349system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles 350system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles 351system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles 352system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles 353system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles |
| 271system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) 272system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) 273system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) 274system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses) 275system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses) 276system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) 277system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) 278system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 287system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses 288system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses 289system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses 290system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses 291system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses 292system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses 293system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses 294system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses | 354system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) 355system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) 356system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) 357system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses) 358system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses) 359system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) 360system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) 361system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 370system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses 371system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses 372system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses 373system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses 374system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses 375system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses 376system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses 377system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses |
| 295system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency 296system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency 297system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency 298system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency 299system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency 300system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency 301system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency 302system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency 303system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency 304system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency 305system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency | 378system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency 379system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency 380system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency 381system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency 382system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency 383system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency 384system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency 385system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency 387system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency |
| 306system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 307system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 308system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 309system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 310system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 311system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 312system.cpu.l2cache.fast_writes 0 # number of fast writes performed 313system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 319system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses 320system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses 321system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses 322system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses 323system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses 324system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses 325system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses 326system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses | 389system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.l2cache.fast_writes 0 # number of fast writes performed 396system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 402system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses 403system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses 404system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses 405system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses 406system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses 407system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses 408system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses 409system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses |
| 327system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles 328system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles 329system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles 330system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles 331system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles 332system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles 333system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles 334system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles 335system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles 336system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles 337system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles | 410system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles 411system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles 412system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles 413system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles 414system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles 417system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles 419system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles 420system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles |
| 338system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses 339system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses 340system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses 341system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses 342system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses 343system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses 344system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses 345system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses 346system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses 347system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses 348system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses | 421system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses 422system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses 423system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses 424system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses 425system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses 426system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses 427system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses 428system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses 429system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses 430system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses 431system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses |
| 349system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency 350system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency 351system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency 352system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency 353system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency 354system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency 355system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency 356system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency 357system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency 358system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency 359system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency | 432system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency 433system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency 434system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency 435system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency 436system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency 438system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency |
| 360system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 443system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 361system.cpu.dcache.tags.replacements 2514362 # number of replacements 362system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use 363system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. 364system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. 365system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. 366system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. 367system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor 368system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy 369system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy 370system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 371system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 372system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 373system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 374system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 375system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 376system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 377system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses 378system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses 379system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits 380system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits 381system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits 382system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits 383system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits 384system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits 385system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits 386system.cpu.dcache.overall_hits::total 530743930 # number of overall hits 387system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 388system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 389system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 390system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 391system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 392system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 393system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 394system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 395system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles 396system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles 397system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles 398system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles 399system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles 400system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles 401system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles 402system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles 403system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) 404system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) 405system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 406system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 407system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses 408system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses 409system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses 410system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses 411system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 412system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses 413system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 414system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses 415system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 416system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses 417system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 418system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses 419system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency 420system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency 421system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency 422system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency 423system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency 424system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency 425system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency 426system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency 427system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 428system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 429system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 431system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 432system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 433system.cpu.dcache.fast_writes 0 # number of fast writes performed 434system.cpu.dcache.cache_copies 0 # number of cache copies performed 435system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks 436system.cpu.dcache.writebacks::total 2323523 # number of writebacks 437system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses 438system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses 439system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses 440system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses 441system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses 442system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses 443system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses 444system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses 445system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles 446system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles 447system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles 448system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles 449system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles 450system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles 451system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles 452system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles 453system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses 454system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses 455system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses 457system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses 458system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses 459system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses 460system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses 461system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency 462system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency 463system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency 464system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency 465system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 466system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 467system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 468system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 469system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 470system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution 475system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes) 476system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 493system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram 495system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) 496system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 497system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 498system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 499system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) 500system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) | 444system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution 447system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution 448system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution 449system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes) 450system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 467system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram 469system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) 470system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 471system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 472system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 473system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) 474system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 475system.membus.trans_dist::ReadReq 174452 # Transaction distribution 476system.membus.trans_dist::ReadResp 174452 # Transaction distribution 477system.membus.trans_dist::Writeback 292286 # Transaction distribution 478system.membus.trans_dist::ReadExReq 206691 # Transaction distribution 479system.membus.trans_dist::ReadExResp 206691 # Transaction distribution 480system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) 481system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) 482system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) 483system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) 484system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) 485system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) 486system.membus.snoops 0 # Total snoops (count) 487system.membus.snoop_fanout::samples 673429 # Request fanout histogram 488system.membus.snoop_fanout::mean 0 # Request fanout histogram 489system.membus.snoop_fanout::stdev 0 # Request fanout histogram 490system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 491system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram 492system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 493system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 494system.membus.snoop_fanout::min_value 0 # Request fanout histogram 495system.membus.snoop_fanout::max_value 0 # Request fanout histogram 496system.membus.snoop_fanout::total 673429 # Request fanout histogram 497system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks) 498system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 499system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks) 500system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
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| 501 502---------- End Simulation Statistics ---------- | 501 502---------- End Simulation Statistics ---------- |