| stats.txt (10409:8c80b91944c5) | stats.txt (10488:7c27480a5031) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated 4sim_ticks 1647872849000 # Number of ticks simulated 5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 845545 # Simulator instruction rate (inst/s) 8host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) --- 71 unchanged lines hidden (view full) --- 80system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written 81system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written 85system.cpu.num_mem_refs 533262343 # number of memory refs 86system.cpu.num_load_insts 384102157 # Number of load instructions 87system.cpu.num_store_insts 149160186 # Number of store instructions | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated 4sim_ticks 1647872849000 # Number of ticks simulated 5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 845545 # Simulator instruction rate (inst/s) 8host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) --- 71 unchanged lines hidden (view full) --- 80system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written 81system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written 85system.cpu.num_mem_refs 533262343 # number of memory refs 86system.cpu.num_load_insts 384102157 # Number of load instructions 87system.cpu.num_store_insts 149160186 # Number of store instructions |
| 88system.cpu.num_idle_cycles 0 # Number of idle cycles 89system.cpu.num_busy_cycles 3295745698 # Number of busy cycles 90system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0 # Percentage of idle cycles | 88system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 89system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles 90system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0.000000 # Percentage of idle cycles |
| 92system.cpu.Branches 149758583 # Number of branches fetched 93system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction 94system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction 95system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction 96system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction 97system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction 98system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction 99system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction 123system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction 124system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 1528988702 # Class of executed instruction 128system.cpu.icache.tags.replacements 1253 # number of replacements 129system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use | 92system.cpu.Branches 149758583 # Number of branches fetched 93system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction 94system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction 95system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction 96system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction 97system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction 98system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction 99system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction 123system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction 124system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 1528988702 # Class of executed instruction 128system.cpu.icache.tags.replacements 1253 # number of replacements 129system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use |
| 130system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks. | 130system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. |
| 131system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. | 131system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. |
| 132system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks. | 132system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. |
| 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor 135system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 136system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy 137system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 138system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 139system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 140system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 141system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 142system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 143system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id | 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor 135system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 136system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy 137system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 138system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 139system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 140system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 141system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 142system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 143system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id |
| 144system.cpu.icache.tags.tag_accesses 2136696946 # Number of tag accesses 145system.cpu.icache.tags.data_accesses 2136696946 # Number of data accesses 146system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits 147system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits 148system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits 149system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits 150system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits 151system.cpu.icache.overall_hits::total 1068344252 # number of overall hits | 144system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses 145system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses 146system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits 147system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits 148system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits 149system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits 150system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits 151system.cpu.icache.overall_hits::total 1068344251 # number of overall hits |
| 152system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 153system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 154system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 155system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 156system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 157system.cpu.icache.overall_misses::total 2814 # number of overall misses 158system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles 159system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles 160system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles 161system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles 162system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles 163system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles | 152system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 153system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 154system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 155system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 156system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 157system.cpu.icache.overall_misses::total 2814 # number of overall misses 158system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles 159system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles 160system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles 161system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles 162system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles 163system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles |
| 164system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) 165system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) 166system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses 167system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses 168system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses 169system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses | 164system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) 165system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) 166system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses 167system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses 168system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses 169system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses |
| 170system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 171system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 172system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 173system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 174system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 175system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 176system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency 177system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency --- 325 unchanged lines hidden --- | 170system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 171system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 172system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 173system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 174system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 175system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 176system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency 177system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency --- 325 unchanged lines hidden --- |