4,5c4,5
< sim_ticks 1652606875000 # Number of ticks simulated
< final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 1652606827000 # Number of ticks simulated
> final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 673883 # Simulator instruction rate (inst/s)
< host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1346830511 # Simulator tick rate (ticks/s)
< host_mem_usage 232676 # Number of bytes of host memory used
< host_seconds 1227.03 # Real time elapsed on the host
< sim_insts 826877145 # Number of instructions simulated
< sim_ops 1528988757 # Number of ops (including micro ops) simulated
---
> host_inst_rate 715148 # Simulator instruction rate (inst/s)
> host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1429304042 # Simulator tick rate (ticks/s)
> host_mem_usage 236556 # Number of bytes of host memory used
> host_seconds 1156.23 # Real time elapsed on the host
> sim_insts 826877110 # Number of instructions simulated
> sim_ops 1528988700 # Number of ops (including micro ops) simulated
27,28c27,28
< system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s)
31,33c31,33
< system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s)
35c35
< system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s)
38c38
< system.cpu.numCycles 3305213750 # number of cpu cycles simulated
---
> system.cpu.numCycles 3305213654 # number of cpu cycles simulated
41,43c41,43
< system.cpu.committedInsts 826877145 # Number of instructions committed
< system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
---
> system.cpu.committedInsts 826877110 # Number of instructions committed
> system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
46,47c46,47
< system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
< system.cpu.num_int_insts 1528317615 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
> system.cpu.num_int_insts 1528317558 # number of integer instructions
49,50c49,50
< system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
< system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read
> system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written
53,54c53,54
< system.cpu.num_mem_refs 533262345 # number of memory refs
< system.cpu.num_load_insts 384102160 # Number of load instructions
---
> system.cpu.num_mem_refs 533262341 # number of memory refs
> system.cpu.num_load_insts 384102156 # Number of load instructions
57c57
< system.cpu.num_busy_cycles 3305213750 # Number of busy cycles
---
> system.cpu.num_busy_cycles 3305213654 # Number of busy cycles
61,62c61,62
< system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use
< system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use
> system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
64c64
< system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
66c66
< system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor
69,74c69,74
< system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits
< system.cpu.icache.overall_hits::total 1068344296 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
> system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
87,92c87,92
< system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
139,140c139,140
< system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use
< system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use
> system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
142,144c142,144
< system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor
---
> system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor
147,148c147,148
< system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
151,154c151,154
< system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits
< system.cpu.dcache.overall_hits::total 530743932 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
> system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
171,172c171,172
< system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
175,178c175,178
< system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
239c239
< system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use
243,246c243,246
< system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor
---
> system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor
< sim_ticks 1652606875000 # Number of ticks simulated
< final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 1652606827000 # Number of ticks simulated
> final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 673883 # Simulator instruction rate (inst/s)
< host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1346830511 # Simulator tick rate (ticks/s)
< host_mem_usage 232676 # Number of bytes of host memory used
< host_seconds 1227.03 # Real time elapsed on the host
< sim_insts 826877145 # Number of instructions simulated
< sim_ops 1528988757 # Number of ops (including micro ops) simulated
---
> host_inst_rate 715148 # Simulator instruction rate (inst/s)
> host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1429304042 # Simulator tick rate (ticks/s)
> host_mem_usage 236556 # Number of bytes of host memory used
> host_seconds 1156.23 # Real time elapsed on the host
> sim_insts 826877110 # Number of instructions simulated
> sim_ops 1528988700 # Number of ops (including micro ops) simulated
27,28c27,28
< system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s)
31,33c31,33
< system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s)
35c35
< system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s)
38c38
< system.cpu.numCycles 3305213750 # number of cpu cycles simulated
---
> system.cpu.numCycles 3305213654 # number of cpu cycles simulated
41,43c41,43
< system.cpu.committedInsts 826877145 # Number of instructions committed
< system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
---
> system.cpu.committedInsts 826877110 # Number of instructions committed
> system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
46,47c46,47
< system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
< system.cpu.num_int_insts 1528317615 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
> system.cpu.num_int_insts 1528317558 # number of integer instructions
49,50c49,50
< system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
< system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read
> system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written
53,54c53,54
< system.cpu.num_mem_refs 533262345 # number of memory refs
< system.cpu.num_load_insts 384102160 # Number of load instructions
---
> system.cpu.num_mem_refs 533262341 # number of memory refs
> system.cpu.num_load_insts 384102156 # Number of load instructions
57c57
< system.cpu.num_busy_cycles 3305213750 # Number of busy cycles
---
> system.cpu.num_busy_cycles 3305213654 # Number of busy cycles
61,62c61,62
< system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use
< system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use
> system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
64c64
< system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
66c66
< system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor
69,74c69,74
< system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits
< system.cpu.icache.overall_hits::total 1068344296 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
> system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
87,92c87,92
< system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
139,140c139,140
< system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use
< system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use
> system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
142,144c142,144
< system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor
---
> system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor
147,148c147,148
< system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
151,154c151,154
< system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits
< system.cpu.dcache.overall_hits::total 530743932 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
> system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
171,172c171,172
< system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
175,178c175,178
< system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
239c239
< system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use
243,246c243,246
< system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor
---
> system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor