Cross Reference: /gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

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stats.txt (11687:b3d5f0e9e258)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.650924 # Number of seconds simulated 4sim_ticks 1650923912500 # Number of ticks simulated 5final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1073233 # Simulator instruction rate (inst/s) 8host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2142868820 # Simulator tick rate (ticks/s) 10host_mem_usage 285448 # Number of bytes of host memory used 11host_seconds 770.43 # Real time elapsed on the host 12sim_insts 826847304 # Number of instructions simulated 13sim_ops 1530082521 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.650924 # Number of seconds simulated 4sim_ticks 1650923912500 # Number of ticks simulated 5final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1073233 # Simulator instruction rate (inst/s) 8host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2142868820 # Simulator tick rate (ticks/s) 10host_mem_usage 285448 # Number of bytes of host memory used 11host_seconds 770.43 # Real time elapsed on the host 12sim_insts 826847304 # Number of instructions simulated 13sim_ops 1530082521 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
46system.cpu.workload.num_syscalls 551 # Number of system calls	46system.cpu.workload.numSyscalls 551 # Number of system calls
47system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states 48system.cpu.numCycles 3301847825 # number of cpu cycles simulated 49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51system.cpu.committedInsts 826847304 # Number of instructions committed 52system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed 53system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses 54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 55system.cpu.num_func_calls 35346287 # number of times a function call or return occured 56system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls 57system.cpu.num_int_insts 1527470226 # number of integer instructions 58system.cpu.num_fp_insts 0 # number of float instructions 59system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read 60system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written 61system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 62system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 63system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read 64system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written 65system.cpu.num_mem_refs 533241508 # number of memory refs 66system.cpu.num_load_insts 384083313 # Number of load instructions 67system.cpu.num_store_insts 149158195 # Number of store instructions 68system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 69system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles 70system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 71system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 72system.cpu.Branches 149981740 # Number of branches fetched 73system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction 74system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction 75system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction 76system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction 77system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction 78system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction 79system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction 80system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction 81system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction 82system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction 83system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction 84system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction 85system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction 86system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction 87system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction 88system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction 89system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction 90system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction 91system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction 92system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction 93system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction 94system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction 95system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction 96system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction 97system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction 98system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction 99system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction 100system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction 101system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction 102system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction 103system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction 104system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction 105system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction 106system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction 107system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 108system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 109system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 110system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::total 1530082521 # Class of executed instruction 112system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 113system.cpu.dcache.tags.replacements 2517016 # number of replacements 114system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use 115system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. 116system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. 117system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. 118system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. 119system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor 120system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy 121system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy 122system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 123system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 124system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 126system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 127system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 128system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 129system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses 130system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses 131system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 132system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits 133system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits 134system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits 135system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits 136system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits 137system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits 138system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits 139system.cpu.dcache.overall_hits::total 530720441 # number of overall hits 140system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses 141system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses 142system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses 143system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses 144system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses 145system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses 146system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses 147system.cpu.dcache.overall_misses::total 2521112 # number of overall misses 148system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles 149system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles 150system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles 151system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles 152system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles 153system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles 154system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles 155system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles 156system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) 157system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) 158system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) 159system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) 160system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses 161system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses 162system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses 163system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses 164system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses 165system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses 166system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses 167system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses 168system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses 169system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses 170system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses 171system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses 172system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency 173system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency 174system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency 175system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency 176system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency 177system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency 179system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency 180system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 186system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks 187system.cpu.dcache.writebacks::total 2324919 # number of writebacks 188system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses 189system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses 191system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses 192system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses 193system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses 194system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses 195system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses 196system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles 204system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses 205system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses 209system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses 210system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses 211system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses 212system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency 214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency 220system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 221system.cpu.icache.tags.replacements 1253 # number of replacements 222system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use 223system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 227system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor 228system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy 230system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 236system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 237system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses 238system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses 239system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 240system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits 241system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits 242system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits 243system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits 244system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits 245system.cpu.icache.overall_hits::total 1068307822 # number of overall hits 246system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 247system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 248system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 249system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 250system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 251system.cpu.icache.overall_misses::total 2814 # number of overall misses 252system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles 253system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles 254system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles 255system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles 256system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles 257system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles 258system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses 262system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses 263system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses 264system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 265system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 266system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 267system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 268system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 269system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 270system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency 271system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency 272system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency 273system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency 274system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency 275system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency 276system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 277system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 280system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 281system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 282system.cpu.icache.writebacks::writebacks 1253 # number of writebacks 283system.cpu.icache.writebacks::total 1253 # number of writebacks 284system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 285system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 286system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 287system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 288system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 289system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 290system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles 291system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles 292system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles 293system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles 294system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles 295system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles 296system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 297system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 298system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 299system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 300system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 301system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 302system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency 303system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency 304system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency 305system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency 306system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency 307system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency 308system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 309system.cpu.l2cache.tags.replacements 349420 # number of replacements 310system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use 311system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. 312system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. 313system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. 314system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. 315system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor 316system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor 317system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor 318system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy 320system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy 322system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 323system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id 325system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id 326system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 327system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses 328system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses 329system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 330system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits 331system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits 332system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits 333system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits 334system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits 335system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits 336system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # number of ReadCleanReq hits 337system.cpu.l2cache.ReadCleanReq_hits::total 1002 # number of ReadCleanReq hits 338system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 # number of ReadSharedReq hits 339system.cpu.l2cache.ReadSharedReq_hits::total 1556392 # number of ReadSharedReq hits 340system.cpu.l2cache.demand_hits::cpu.inst 1002 # number of demand (read+write) hits 341system.cpu.l2cache.demand_hits::cpu.data 2141233 # number of demand (read+write) hits 342system.cpu.l2cache.demand_hits::total 2142235 # number of demand (read+write) hits 343system.cpu.l2cache.overall_hits::cpu.inst 1002 # number of overall hits 344system.cpu.l2cache.overall_hits::cpu.data 2141233 # number of overall hits 345system.cpu.l2cache.overall_hits::total 2142235 # number of overall hits 346system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses 347system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses 348system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses 349system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses 350system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses 351system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses 352system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses 353system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses 354system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses 355system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses 356system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses 357system.cpu.l2cache.overall_misses::total 381691 # number of overall misses 358system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles 359system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles 360system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles 361system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles 362system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles 363system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles 364system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles 365system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles 366system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles 367system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles 368system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles 369system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles 370system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) 371system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) 372system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) 373system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) 374system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) 375system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) 376system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) 377system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) 378system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) 379system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) 380system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 381system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses 382system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses 383system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 384system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses 385system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses 386system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses 387system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses 388system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses 389system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses 390system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses 391system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses 392system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses 393system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses 394system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses 395system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses 396system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses 397system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses 398system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency 399system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency 400system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency 401system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency 402system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency 403system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency 404system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency 405system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency 406system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency 407system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency 408system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency 409system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency 410system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 411system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 412system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 413system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 414system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 415system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 416system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks 417system.cpu.l2cache.writebacks::total 293952 # number of writebacks 418system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses 419system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses 420system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses 421system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses 422system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses 423system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses 424system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses 425system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses 426system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses 427system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses 428system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses 429system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses 430system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses 431system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses 432system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles 433system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles 434system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles 435system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles 436system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles 437system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles 438system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles 439system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles 440system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles 441system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles 442system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles 443system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles 444system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 445system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 446system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses 447system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses 448system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses 449system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses 450system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses 451system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses 452system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses 453system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses 454system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses 455system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses 456system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses 457system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses 458system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency 459system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency 460system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency 461system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency 462system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency 463system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency 464system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency 465system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency 466system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency 467system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency 468system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency 469system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency 470system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. 471system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 472system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 473system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. 474system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 475system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 476system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 477system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution 482system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution 484system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution 485system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) 486system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) 487system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) 488system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) 489system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) 490system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) 491system.cpu.toL2Bus.snoops 349420 # Total snoops (count) 492system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) 493system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 500system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 501system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 502system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 503system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram 504system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) 505system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 506system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 507system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 508system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) 509system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 510system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter. 511system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 512system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 513system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 514system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 515system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 516system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 517system.membus.trans_dist::ReadResp 175162 # Transaction distribution 518system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution 519system.membus.trans_dist::CleanEvict 53608 # Transaction distribution 520system.membus.trans_dist::ReadExReq 206529 # Transaction distribution 521system.membus.trans_dist::ReadExResp 206529 # Transaction distribution 522system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution 523system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes) 524system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes) 525system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes) 526system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes) 527system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes) 528system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes) 529system.membus.snoops 0 # Total snoops (count) 530system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 531system.membus.snoop_fanout::samples 381691 # Request fanout histogram 532system.membus.snoop_fanout::mean 0 # Request fanout histogram 533system.membus.snoop_fanout::stdev 0 # Request fanout histogram 534system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 535system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram 536system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 537system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 538system.membus.snoop_fanout::min_value 0 # Request fanout histogram 539system.membus.snoop_fanout::max_value 0 # Request fanout histogram 540system.membus.snoop_fanout::total 381691 # Request fanout histogram 541system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks) 542system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 543system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks) 544system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 545 546---------- End Simulation Statistics ----------	47system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states 48system.cpu.numCycles 3301847825 # number of cpu cycles simulated 49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51system.cpu.committedInsts 826847304 # Number of instructions committed 52system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed 53system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses 54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 55system.cpu.num_func_calls 35346287 # number of times a function call or return occured 56system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls 57system.cpu.num_int_insts 1527470226 # number of integer instructions 58system.cpu.num_fp_insts 0 # number of float instructions 59system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read 60system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written 61system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 62system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 63system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read 64system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written 65system.cpu.num_mem_refs 533241508 # number of memory refs 66system.cpu.num_load_insts 384083313 # Number of load instructions 67system.cpu.num_store_insts 149158195 # Number of store instructions 68system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 69system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles 70system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 71system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 72system.cpu.Branches 149981740 # Number of branches fetched 73system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction 74system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction 75system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction 76system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction 77system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction 78system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction 79system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction 80system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction 81system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction 82system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction 83system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction 84system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction 85system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction 86system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction 87system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction 88system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction 89system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction 90system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction 91system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction 92system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction 93system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction 94system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction 95system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction 96system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction 97system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction 98system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction 99system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction 100system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction 101system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction 102system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction 103system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction 104system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction 105system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction 106system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction 107system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 108system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 109system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 110system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::total 1530082521 # Class of executed instruction 112system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 113system.cpu.dcache.tags.replacements 2517016 # number of replacements 114system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use 115system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. 116system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. 117system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. 118system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. 119system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor 120system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy 121system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy 122system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 123system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 124system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 126system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 127system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 128system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 129system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses 130system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses 131system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 132system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits 133system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits 134system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits 135system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits 136system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits 137system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits 138system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits 139system.cpu.dcache.overall_hits::total 530720441 # number of overall hits 140system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses 141system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses 142system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses 143system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses 144system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses 145system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses 146system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses 147system.cpu.dcache.overall_misses::total 2521112 # number of overall misses 148system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles 149system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles 150system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles 151system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles 152system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles 153system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles 154system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles 155system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles 156system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) 157system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) 158system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) 159system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) 160system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses 161system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses 162system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses 163system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses 164system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses 165system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses 166system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses 167system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses 168system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses 169system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses 170system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses 171system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses 172system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency 173system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency 174system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency 175system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency 176system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency 177system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency 179system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency 180system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 186system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks 187system.cpu.dcache.writebacks::total 2324919 # number of writebacks 188system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses 189system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses 191system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses 192system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses 193system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses 194system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses 195system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses 196system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles 204system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses 205system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses 209system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses 210system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses 211system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses 212system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency 214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency 220system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 221system.cpu.icache.tags.replacements 1253 # number of replacements 222system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use 223system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 227system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor 228system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy 230system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 233system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 234system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 236system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 237system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses 238system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses 239system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 240system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits 241system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits 242system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits 243system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits 244system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits 245system.cpu.icache.overall_hits::total 1068307822 # number of overall hits 246system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 247system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 248system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 249system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 250system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 251system.cpu.icache.overall_misses::total 2814 # number of overall misses 252system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles 253system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles 254system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles 255system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles 256system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles 257system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles 258system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses 262system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses 263system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses 264system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 265system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 266system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 267system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 268system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 269system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 270system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency 271system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency 272system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency 273system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency 274system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency 275system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency 276system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 277system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 280system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 281system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 282system.cpu.icache.writebacks::writebacks 1253 # number of writebacks 283system.cpu.icache.writebacks::total 1253 # number of writebacks 284system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 285system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 286system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 287system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 288system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 289system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 290system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles 291system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles 292system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles 293system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles 294system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles 295system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles 296system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 297system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 298system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 299system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 300system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 301system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 302system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency 303system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency 304system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency 305system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency 306system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency 307system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency 308system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 309system.cpu.l2cache.tags.replacements 349420 # number of replacements 310system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use 311system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. 312system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. 313system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. 314system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. 315system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor 316system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor 317system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor 318system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy 320system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy 322system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 323system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id 325system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id 326system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 327system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses 328system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses 329system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 330system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits 331system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits 332system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits 333system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits 334system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits 335system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits 336system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # number of ReadCleanReq hits 337system.cpu.l2cache.ReadCleanReq_hits::total 1002 # number of ReadCleanReq hits 338system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 # number of ReadSharedReq hits 339system.cpu.l2cache.ReadSharedReq_hits::total 1556392 # number of ReadSharedReq hits 340system.cpu.l2cache.demand_hits::cpu.inst 1002 # number of demand (read+write) hits 341system.cpu.l2cache.demand_hits::cpu.data 2141233 # number of demand (read+write) hits 342system.cpu.l2cache.demand_hits::total 2142235 # number of demand (read+write) hits 343system.cpu.l2cache.overall_hits::cpu.inst 1002 # number of overall hits 344system.cpu.l2cache.overall_hits::cpu.data 2141233 # number of overall hits 345system.cpu.l2cache.overall_hits::total 2142235 # number of overall hits 346system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses 347system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses 348system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses 349system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses 350system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses 351system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses 352system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses 353system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses 354system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses 355system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses 356system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses 357system.cpu.l2cache.overall_misses::total 381691 # number of overall misses 358system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles 359system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles 360system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles 361system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles 362system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles 363system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles 364system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles 365system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles 366system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles 367system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles 368system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles 369system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles 370system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) 371system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) 372system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) 373system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) 374system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) 375system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) 376system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) 377system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) 378system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) 379system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) 380system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 381system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses 382system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses 383system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 384system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses 385system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses 386system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses 387system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses 388system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses 389system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses 390system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses 391system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses 392system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses 393system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses 394system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses 395system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses 396system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses 397system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses 398system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency 399system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency 400system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency 401system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency 402system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency 403system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency 404system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency 405system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency 406system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency 407system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency 408system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency 409system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency 410system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 411system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 412system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 413system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 414system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 415system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 416system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks 417system.cpu.l2cache.writebacks::total 293952 # number of writebacks 418system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses 419system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses 420system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses 421system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses 422system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses 423system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses 424system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses 425system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses 426system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses 427system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses 428system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses 429system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses 430system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses 431system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses 432system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles 433system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles 434system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles 435system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles 436system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles 437system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles 438system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles 439system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles 440system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles 441system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles 442system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles 443system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles 444system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 445system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 446system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses 447system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses 448system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses 449system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses 450system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses 451system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses 452system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses 453system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses 454system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses 455system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses 456system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses 457system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses 458system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency 459system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency 460system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency 461system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency 462system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency 463system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency 464system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency 465system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency 466system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency 467system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency 468system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency 469system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency 470system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. 471system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 472system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 473system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. 474system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 475system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 476system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 477system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution 482system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution 484system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution 485system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) 486system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) 487system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) 488system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) 489system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) 490system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) 491system.cpu.toL2Bus.snoops 349420 # Total snoops (count) 492system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) 493system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 500system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 501system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 502system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 503system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram 504system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) 505system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 506system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 507system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 508system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) 509system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 510system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter. 511system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 512system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 513system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 514system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 515system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 516system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states 517system.membus.trans_dist::ReadResp 175162 # Transaction distribution 518system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution 519system.membus.trans_dist::CleanEvict 53608 # Transaction distribution 520system.membus.trans_dist::ReadExReq 206529 # Transaction distribution 521system.membus.trans_dist::ReadExResp 206529 # Transaction distribution 522system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution 523system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes) 524system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes) 525system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes) 526system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes) 527system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes) 528system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes) 529system.membus.snoops 0 # Total snoops (count) 530system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 531system.membus.snoop_fanout::samples 381691 # Request fanout histogram 532system.membus.snoop_fanout::mean 0 # Request fanout histogram 533system.membus.snoop_fanout::stdev 0 # Request fanout histogram 534system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 535system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram 536system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 537system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 538system.membus.snoop_fanout::min_value 0 # Request fanout histogram 539system.membus.snoop_fanout::max_value 0 # Request fanout histogram 540system.membus.snoop_fanout::total 381691 # Request fanout histogram 541system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks) 542system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 543system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks) 544system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 545 546---------- End Simulation Statistics ----------