1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.647873 # Number of seconds simulated
4sim_ticks 1647872849000 # Number of ticks simulated
5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 782951 # Simulator instruction rate (inst/s)
8host_op_rate 1447764 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1560332529 # Simulator tick rate (ticks/s)
10host_mem_usage 260992 # Number of bytes of host memory used
11host_seconds 1056.10 # Real time elapsed on the host
12sim_insts 826877110 # Number of instructions simulated
13sim_ops 1528988702 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory
22system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
39system.membus.throughput 26154600 # Throughput (bytes/s)
40system.membus.trans_dist::ReadReq 174452 # Transaction distribution
41system.membus.trans_dist::ReadResp 174452 # Transaction distribution
42system.membus.trans_dist::Writeback 292286 # Transaction distribution
43system.membus.trans_dist::ReadExReq 206691 # Transaction distribution
44system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
47system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
49system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
50system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
51system.membus.data_through_bus 43099456 # Total data (bytes)
52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
53system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
54system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
55system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
56system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
57system.cpu_clk_domain.clock 500 # Clock period in ticks
58system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
59system.cpu.workload.num_syscalls 551 # Number of system calls
60system.cpu.numCycles 3295745698 # number of cpu cycles simulated
61system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
62system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
63system.cpu.committedInsts 826877110 # Number of instructions committed
64system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
65system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
66system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
67system.cpu.num_func_calls 35346287 # number of times a function call or return occured
68system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
69system.cpu.num_int_insts 1526605510 # number of integer instructions
70system.cpu.num_fp_insts 0 # number of float instructions
71system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
72system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
73system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
74system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
75system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
76system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
77system.cpu.num_mem_refs 533262343 # number of memory refs
78system.cpu.num_load_insts 384102157 # Number of load instructions
79system.cpu.num_store_insts 149160186 # Number of store instructions
80system.cpu.num_idle_cycles 0 # Number of idle cycles
81system.cpu.num_busy_cycles 3295745698 # Number of busy cycles
82system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
83system.cpu.idle_fraction 0 # Percentage of idle cycles
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.647873 # Number of seconds simulated
4sim_ticks 1647872849000 # Number of ticks simulated
5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 782951 # Simulator instruction rate (inst/s)
8host_op_rate 1447764 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1560332529 # Simulator tick rate (ticks/s)
10host_mem_usage 260992 # Number of bytes of host memory used
11host_seconds 1056.10 # Real time elapsed on the host
12sim_insts 826877110 # Number of instructions simulated
13sim_ops 1528988702 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory
18system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory
22system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
39system.membus.throughput 26154600 # Throughput (bytes/s)
40system.membus.trans_dist::ReadReq 174452 # Transaction distribution
41system.membus.trans_dist::ReadResp 174452 # Transaction distribution
42system.membus.trans_dist::Writeback 292286 # Transaction distribution
43system.membus.trans_dist::ReadExReq 206691 # Transaction distribution
44system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
47system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
49system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
50system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
51system.membus.data_through_bus 43099456 # Total data (bytes)
52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
53system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
54system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
55system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
56system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
57system.cpu_clk_domain.clock 500 # Clock period in ticks
58system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
59system.cpu.workload.num_syscalls 551 # Number of system calls
60system.cpu.numCycles 3295745698 # number of cpu cycles simulated
61system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
62system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
63system.cpu.committedInsts 826877110 # Number of instructions committed
64system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
65system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
66system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
67system.cpu.num_func_calls 35346287 # number of times a function call or return occured
68system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
69system.cpu.num_int_insts 1526605510 # number of integer instructions
70system.cpu.num_fp_insts 0 # number of float instructions
71system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
72system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
73system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
74system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
75system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
76system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
77system.cpu.num_mem_refs 533262343 # number of memory refs
78system.cpu.num_load_insts 384102157 # Number of load instructions
79system.cpu.num_store_insts 149160186 # Number of store instructions
80system.cpu.num_idle_cycles 0 # Number of idle cycles
81system.cpu.num_busy_cycles 3295745698 # Number of busy cycles
82system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
83system.cpu.idle_fraction 0 # Percentage of idle cycles
|
| 84system.cpu.Branches 149758583 # Number of branches fetched
|
84system.cpu.icache.tags.replacements 1253 # number of replacements
85system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
86system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
87system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
88system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks.
89system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
90system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
91system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
92system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy
93system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
94system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
95system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
96system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
97system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
98system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
99system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
100system.cpu.icache.tags.tag_accesses 2136696946 # Number of tag accesses
101system.cpu.icache.tags.data_accesses 2136696946 # Number of data accesses
102system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
103system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
104system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
105system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
106system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
107system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
108system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
109system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
110system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
111system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
112system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
113system.cpu.icache.overall_misses::total 2814 # number of overall misses
114system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles
115system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles
116system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles
117system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles
118system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles
119system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles
120system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
121system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
122system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
123system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
124system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
125system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
126system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
127system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
128system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
129system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
130system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
131system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
132system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency
133system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency
134system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
135system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency
136system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
137system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency
138system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
139system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
140system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
141system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
142system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
143system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
144system.cpu.icache.fast_writes 0 # number of fast writes performed
145system.cpu.icache.cache_copies 0 # number of cache copies performed
146system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
147system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
148system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
149system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
150system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
151system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
152system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles
153system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles
154system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles
155system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles
156system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles
157system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles
158system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
159system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
160system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
161system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
162system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
163system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
164system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency
165system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency
166system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
167system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
168system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
169system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
170system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
171system.cpu.l2cache.tags.replacements 348459 # number of replacements
172system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use
173system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks.
174system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks.
175system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks.
176system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
177system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
178system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
179system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
180system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
181system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
182system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
183system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy
184system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id
185system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
186system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
187system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
188system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id
189system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id
190system.cpu.l2cache.tags.tag_accesses 39930218 # Number of tag accesses
191system.cpu.l2cache.tags.data_accesses 39930218 # Number of data accesses
192system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits
193system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits
194system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits
195system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits
196system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits
197system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits
198system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits
199system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits
200system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits
201system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits
202system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits
203system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits
204system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits
205system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses
206system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses
207system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses
208system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses
209system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses
210system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses
211system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses
212system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses
213system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses
214system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses
215system.cpu.l2cache.overall_misses::total 381143 # number of overall misses
216system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles
217system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles
218system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles
219system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles
220system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles
221system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles
222system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles
223system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles
224system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles
225system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles
226system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles
227system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
228system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
229system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
230system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses)
231system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses)
232system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
233system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
234system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
235system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
236system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
237system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
238system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
239system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
240system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses
241system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses
242system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses
243system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses
244system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses
245system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses
246system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses
247system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses
248system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses
249system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses
250system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses
251system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency
252system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency
253system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency
254system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency
255system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency
256system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
257system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
258system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency
259system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
260system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
261system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency
262system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
263system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
264system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
265system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
266system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
267system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
268system.cpu.l2cache.fast_writes 0 # number of fast writes performed
269system.cpu.l2cache.cache_copies 0 # number of cache copies performed
270system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks
271system.cpu.l2cache.writebacks::total 292286 # number of writebacks
272system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses
273system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses
274system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses
275system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses
276system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses
277system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses
278system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses
279system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses
280system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses
281system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses
282system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses
283system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles
284system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles
285system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles
286system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles
287system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles
288system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles
289system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles
290system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles
291system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles
292system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles
293system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles
294system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses
295system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses
296system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses
297system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses
298system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses
299system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses
300system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses
301system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses
302system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses
303system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses
304system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses
305system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency
306system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency
307system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency
308system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency
309system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency
310system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
311system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
312system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
313system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
314system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
315system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
316system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
317system.cpu.dcache.tags.replacements 2514362 # number of replacements
318system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use
319system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
320system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
321system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
322system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
323system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
324system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
325system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
326system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
327system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
328system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
329system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
330system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
331system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
332system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
333system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
334system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
335system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
336system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
337system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
338system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
339system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
340system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
341system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
342system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
343system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
344system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
345system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
346system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
347system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
348system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
349system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
350system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
351system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
352system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
353system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
354system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
355system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
356system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
357system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
358system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
359system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
360system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
361system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
362system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
363system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
364system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
365system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
366system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
367system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
368system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
369system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
370system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
371system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
372system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
373system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
374system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
375system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency
376system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency
377system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency
378system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency
379system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
380system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency
381system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
382system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency
383system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
384system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
386system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
387system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
388system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389system.cpu.dcache.fast_writes 0 # number of fast writes performed
390system.cpu.dcache.cache_copies 0 # number of cache copies performed
391system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks
392system.cpu.dcache.writebacks::total 2323523 # number of writebacks
393system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
394system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
395system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
396system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
397system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
398system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
399system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
400system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
401system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles
402system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles
403system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles
404system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles
405system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles
406system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles
407system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles
408system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles
409system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
410system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
411system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
412system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
413system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
414system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
415system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
416system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
417system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency
418system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency
419system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency
420system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency
421system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
422system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
423system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
424system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
425system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
426system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s)
427system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
428system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
429system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
430system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
431system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
432system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes)
433system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes)
434system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes)
435system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
436system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
437system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
438system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
439system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
440system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
441system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
442system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
443system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
444system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
445system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
446
447---------- End Simulation Statistics ----------
| 85system.cpu.icache.tags.replacements 1253 # number of replacements
86system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
87system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
88system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
89system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks.
90system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
91system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
92system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
93system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy
94system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
95system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
96system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
97system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
98system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
99system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
100system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
101system.cpu.icache.tags.tag_accesses 2136696946 # Number of tag accesses
102system.cpu.icache.tags.data_accesses 2136696946 # Number of data accesses
103system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
104system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
105system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
106system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
107system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
108system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
109system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
110system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
111system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
112system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
113system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
114system.cpu.icache.overall_misses::total 2814 # number of overall misses
115system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles
116system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles
117system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles
118system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles
119system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles
120system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles
121system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
122system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
123system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
124system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
125system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
126system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
127system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
128system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
129system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
130system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
131system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
132system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
133system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency
134system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency
135system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
136system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency
137system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
138system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency
139system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
140system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
141system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
142system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
143system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
144system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
145system.cpu.icache.fast_writes 0 # number of fast writes performed
146system.cpu.icache.cache_copies 0 # number of cache copies performed
147system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
148system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
149system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
150system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
151system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
152system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
153system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles
154system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles
155system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles
156system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles
157system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles
158system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles
159system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
160system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
161system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
162system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
163system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
164system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
165system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency
166system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency
167system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
168system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
169system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
170system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
171system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
172system.cpu.l2cache.tags.replacements 348459 # number of replacements
173system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use
174system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks.
175system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks.
176system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks.
177system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
178system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
179system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
180system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
181system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
182system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
183system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
184system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy
185system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id
186system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
187system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
188system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
189system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id
190system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id
191system.cpu.l2cache.tags.tag_accesses 39930218 # Number of tag accesses
192system.cpu.l2cache.tags.data_accesses 39930218 # Number of data accesses
193system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits
194system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits
195system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits
196system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits
197system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits
198system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits
199system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits
200system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits
201system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits
202system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits
203system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits
204system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits
205system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits
206system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses
207system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses
208system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses
209system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses
210system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses
211system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses
212system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses
213system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses
214system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses
215system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses
216system.cpu.l2cache.overall_misses::total 381143 # number of overall misses
217system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles
218system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles
219system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles
220system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles
221system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles
222system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles
223system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles
224system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles
225system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles
226system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles
227system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles
228system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
229system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
230system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
231system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses)
232system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses)
233system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
234system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
235system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
236system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
237system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
238system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
239system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
240system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
241system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses
242system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses
243system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses
244system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses
245system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses
246system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses
247system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses
248system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses
249system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses
250system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses
251system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses
252system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency
253system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency
254system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency
255system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency
256system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency
257system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
258system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
259system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency
260system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
261system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
262system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency
263system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
264system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
265system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
266system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
267system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
268system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
269system.cpu.l2cache.fast_writes 0 # number of fast writes performed
270system.cpu.l2cache.cache_copies 0 # number of cache copies performed
271system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks
272system.cpu.l2cache.writebacks::total 292286 # number of writebacks
273system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses
274system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses
275system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses
276system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses
277system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses
278system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses
279system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses
280system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses
281system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses
282system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses
283system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses
284system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles
285system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles
286system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles
287system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles
288system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles
289system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles
290system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles
291system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles
292system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles
293system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles
294system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles
295system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses
296system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses
297system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses
298system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses
299system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses
300system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses
301system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses
302system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses
303system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses
304system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses
305system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses
306system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency
307system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency
308system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency
309system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency
310system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency
311system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
312system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
313system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
314system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
315system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
316system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
317system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
318system.cpu.dcache.tags.replacements 2514362 # number of replacements
319system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use
320system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
321system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
322system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
323system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
324system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
325system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
326system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
327system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
328system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
329system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
330system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
331system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
332system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
333system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
334system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
335system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
336system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
337system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
338system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
339system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
340system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
341system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
342system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
343system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
344system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
345system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
346system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
347system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
348system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
349system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
350system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
351system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
352system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
353system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
354system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
355system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
356system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
357system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
358system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
359system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
360system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
361system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
362system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
363system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
364system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
365system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
366system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
367system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
368system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
369system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
370system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
371system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
372system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
373system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
374system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
375system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
376system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency
377system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency
378system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency
379system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency
380system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
381system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency
382system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
383system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency
384system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
385system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
386system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
387system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
388system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
389system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
390system.cpu.dcache.fast_writes 0 # number of fast writes performed
391system.cpu.dcache.cache_copies 0 # number of cache copies performed
392system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks
393system.cpu.dcache.writebacks::total 2323523 # number of writebacks
394system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
395system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
396system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
397system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
398system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
399system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
400system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
401system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
402system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles
403system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles
404system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles
405system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles
406system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles
407system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles
408system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles
409system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles
410system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
411system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
412system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
413system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
414system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
415system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
416system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
417system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
418system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency
419system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency
420system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency
421system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency
422system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
423system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
424system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
425system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
426system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
427system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s)
428system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
429system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
430system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
431system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
432system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
433system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes)
434system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes)
435system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes)
436system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
437system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
438system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
439system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
440system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
441system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
442system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
443system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
444system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
445system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
446system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
447
448---------- End Simulation Statistics ----------
|