| stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.451833 # Number of seconds simulated 4sim_ticks 451832922000 # Number of ticks simulated 5final_tick 451832922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.458090 # Number of seconds simulated 4sim_ticks 458090415000 # Number of ticks simulated 5final_tick 458090415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 67045 # Simulator instruction rate (inst/s) 8host_op_rate 123974 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36635806 # Simulator tick rate (ticks/s) 10host_mem_usage 390776 # Number of bytes of host memory used 11host_seconds 12333.10 # Real time elapsed on the host | 7host_inst_rate 96465 # Simulator instruction rate (inst/s) 8host_op_rate 178374 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53441498 # Simulator tick rate (ticks/s) 10host_mem_usage 343040 # Number of bytes of host memory used 11host_seconds 8571.81 # Real time elapsed on the host |
| 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated | 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24482112 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24684928 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18794304 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18794304 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 382533 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385702 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293661 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293661 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 448874 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 54183993 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 54632867 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 448874 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 448874 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 41595694 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 41595694 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 41595694 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 448874 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 54183993 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 96228561 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385702 # Total number of read requests seen 38system.physmem.writeReqs 293661 # Total number of write requests seen 39system.physmem.cpureqs 815428 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 24684928 # Total number of bytes read from memory 41system.physmem.bytesWritten 18794304 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 24684928 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 18794304 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 136028 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 23108 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 24460 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 23977 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 22639 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 23451 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 24452 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 24479 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 24189 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 24310 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 25055 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 24328 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 24340 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 23420 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 24898 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 23991 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 17770 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 18792 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 18332 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 17557 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 18441 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 18303 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 18298 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 18726 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 19016 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 18442 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 18563 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 17871 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 18864 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 18115 # Track writes on a per bank basis | 14system.physmem.bytes_read::cpu.inst 202496 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24476544 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24679040 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 202496 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 202496 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18790272 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18790272 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3164 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 382446 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385610 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293598 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293598 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 442044 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 53431688 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 53873731 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 442044 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 442044 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 41018697 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 41018697 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 41018697 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 442044 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 53431688 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 94892429 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385610 # Total number of read requests seen 38system.physmem.writeReqs 293598 # Total number of write requests seen 39system.physmem.cpureqs 811581 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 24679040 # Total number of bytes read from memory 41system.physmem.bytesWritten 18790272 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 24679040 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 18790272 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 158 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 132366 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 26444 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 24671 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 24517 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 23227 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 23669 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 24418 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 24212 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 23609 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 23834 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 24778 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 24050 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 23243 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 22960 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 23768 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 23988 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 18530 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 18950 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 18922 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 18033 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 18412 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 18983 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 18945 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 18535 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 18118 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 17707 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 16952 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 17709 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 17824 # Track writes on a per bank basis |
| 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 79system.physmem.numWrRetry 37 # Number of times wr buffer was full causing retry 80system.physmem.totGap 451832896000 # Total gap between requests | 79system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry 80system.physmem.totGap 458090389000 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 385702 # Categorize read packet sizes | 87system.physmem.readPktSize::6 385610 # Categorize read packet sizes |
| 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes | 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 94system.physmem.writePktSize::6 293661 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 380831 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 4356 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 329 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see | 94system.physmem.writePktSize::6 293598 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 380772 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 4340 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 300 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 127system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 12719 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 12722 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 12723 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 12725 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 12728 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 12729 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 12768 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 12768 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 12768 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 12768 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 12768 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 12768 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 12768 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 12768 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 45 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 43 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 40 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 39 # What write queue length does an incoming req see 159system.physmem.totQLat 3445991500 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 12040169000 # Sum of mem lat for all requests 161system.physmem.totBusLat 1927820000 # Total cycles spent in databus access 162system.physmem.totBankLat 6666357500 # Total cycles spent in bank access 163system.physmem.avgQLat 8937.53 # Average queueing delay per request 164system.physmem.avgBankLat 17289.89 # Average bank access latency per request | 127system.physmem.wrQLenPdf::0 12721 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 12738 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 12746 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 12748 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 12751 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 12755 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 12756 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 12765 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 12765 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 12765 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 12765 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 12765 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 12765 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 12765 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 12765 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see 159system.physmem.bytesPerActivate::samples 126022 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::mean 344.851534 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::gmean 161.962358 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::stdev 666.348366 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::64-65 54057 42.89% 42.89% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::128-129 23501 18.65% 61.54% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::192-193 10538 8.36% 69.91% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::256-257 6321 5.02% 74.92% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::320-321 4049 3.21% 78.13% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::384-385 2993 2.37% 80.51% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::448-449 2158 1.71% 82.22% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::512-513 1750 1.39% 83.61% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::576-577 1435 1.14% 84.75% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::640-641 1167 0.93% 85.67% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::704-705 1218 0.97% 86.64% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::768-769 1087 0.86% 87.50% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::832-833 749 0.59% 88.10% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::896-897 671 0.53% 88.63% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::960-961 595 0.47% 89.10% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1024-1025 568 0.45% 89.55% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 568 0.45% 90.00% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 525 0.42% 90.42% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 573 0.45% 90.88% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1280-1281 736 0.58% 91.46% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1344-1345 592 0.47% 91.93% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1408-1409 743 0.59% 92.52% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1472-1473 6177 4.90% 97.42% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1536-1537 481 0.38% 97.80% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1600-1601 330 0.26% 98.06% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1664-1665 288 0.23% 98.29% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1728-1729 210 0.17% 98.46% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1792-1793 190 0.15% 98.61% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1856-1857 142 0.11% 98.72% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1920-1921 147 0.12% 98.84% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1984-1985 96 0.08% 98.92% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2048-2049 92 0.07% 98.99% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2112-2113 69 0.05% 99.04% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2176-2177 52 0.04% 99.08% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2240-2241 45 0.04% 99.12% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2304-2305 44 0.03% 99.15% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2368-2369 35 0.03% 99.18% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2432-2433 33 0.03% 99.21% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2496-2497 28 0.02% 99.23% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2560-2561 24 0.02% 99.25% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2624-2625 31 0.02% 99.27% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2688-2689 21 0.02% 99.29% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2752-2753 18 0.01% 99.31% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2816-2817 25 0.02% 99.33% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.34% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2944-2945 20 0.02% 99.36% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3008-3009 17 0.01% 99.37% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3072-3073 13 0.01% 99.38% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3136-3137 15 0.01% 99.39% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3200-3201 13 0.01% 99.40% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3264-3265 16 0.01% 99.42% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3392-3393 6 0.00% 99.44% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3456-3457 9 0.01% 99.44% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3520-3521 7 0.01% 99.45% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3584-3585 17 0.01% 99.46% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3648-3649 9 0.01% 99.47% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3776-3777 8 0.01% 99.48% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3840-3841 13 0.01% 99.49% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3904-3905 9 0.01% 99.50% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4096-4097 13 0.01% 99.52% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4160-4161 4 0.00% 99.52% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.53% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4288-4289 8 0.01% 99.54% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.55% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4480-4481 5 0.00% 99.55% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4608-4609 4 0.00% 99.56% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4672-4673 8 0.01% 99.56% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.56% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.57% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.57% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4928-4929 6 0.00% 99.57% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5184-5185 9 0.01% 99.59% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5248-5249 3 0.00% 99.59% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5312-5313 8 0.01% 99.60% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5376-5377 11 0.01% 99.61% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.61% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5504-5505 5 0.00% 99.62% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5568-5569 5 0.00% 99.62% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.62% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.63% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.63% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.63% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.64% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.65% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.65% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.66% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6656-6657 5 0.00% 99.66% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.67% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.68% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.68% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.68% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.68% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.69% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.69% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.69% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.69% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.70% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.70% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.70% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::8192-8193 373 0.30% 100.00% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::total 126022 # Bytes accessed per row activation 288system.physmem.totQLat 3040953000 # Total cycles spent in queuing delays 289system.physmem.totMemAccLat 11219526750 # Sum of mem lat for all requests 290system.physmem.totBusLat 1927260000 # Total cycles spent in databus access 291system.physmem.totBankLat 6251313750 # Total cycles spent in bank access 292system.physmem.avgQLat 7889.32 # Average queueing delay per request 293system.physmem.avgBankLat 16218.14 # Average bank access latency per request |
| 165system.physmem.avgBusLat 5000.00 # Average bus latency per request | 294system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 166system.physmem.avgMemAccLat 31227.42 # Average memory access latency 167system.physmem.avgRdBW 54.63 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 41.60 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 54.63 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 41.60 # Average consumed write bandwidth in MB/s | 295system.physmem.avgMemAccLat 29107.46 # Average memory access latency 296system.physmem.avgRdBW 53.87 # Average achieved read bandwidth in MB/s 297system.physmem.avgWrBW 41.02 # Average achieved write bandwidth in MB/s 298system.physmem.avgConsumedRdBW 53.87 # Average consumed read bandwidth in MB/s 299system.physmem.avgConsumedWrBW 41.02 # Average consumed write bandwidth in MB/s |
| 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 300system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 172system.physmem.busUtil 0.75 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.03 # Average read queue length over time 174system.physmem.avgWrQLen 8.94 # Average write queue length over time 175system.physmem.readRowHits 331871 # Number of row buffer hits during reads 176system.physmem.writeRowHits 191829 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes 179system.physmem.avgGap 665083.17 # Average gap between requests 180system.cpu.branchPred.lookups 205621718 # Number of BP lookups 181system.cpu.branchPred.condPredicted 205621718 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 9907083 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 117077740 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 114695478 # Number of BTB hits | 301system.physmem.busUtil 0.74 # Data bus utilization in percentage 302system.physmem.avgRdQLen 0.02 # Average read queue length over time 303system.physmem.avgWrQLen 10.25 # Average write queue length over time 304system.physmem.readRowHits 346179 # Number of row buffer hits during reads 305system.physmem.writeRowHits 206846 # Number of row buffer hits during writes 306system.physmem.readRowHitRate 89.81 # Row buffer hit rate for reads 307system.physmem.writeRowHitRate 70.45 # Row buffer hit rate for writes 308system.physmem.avgGap 674447.87 # Average gap between requests 309system.membus.throughput 94892429 # Throughput (bytes/s) 310system.membus.trans_dist::ReadReq 178764 # Transaction distribution 311system.membus.trans_dist::ReadResp 178764 # Transaction distribution 312system.membus.trans_dist::Writeback 293598 # Transaction distribution 313system.membus.trans_dist::UpgradeReq 132366 # Transaction distribution 314system.membus.trans_dist::UpgradeResp 132366 # Transaction distribution 315system.membus.trans_dist::ReadExReq 206846 # Transaction distribution 316system.membus.trans_dist::ReadExResp 206846 # Transaction distribution 317system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1329550 # Packet count per connected master and slave (bytes) 319system.membus.pkt_count::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) 320system.membus.pkt_count::total 1329550 # Packet count per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469312 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size::total 43469312 # Cumulative packet size per connected master and slave (bytes) 325system.membus.data_through_bus 43469312 # Total data (bytes) 326system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 327system.membus.reqLayer0.occupancy 3305392000 # Layer occupancy (ticks) 328system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 329system.membus.respLayer1.occupancy 3861844643 # Layer occupancy (ticks) 330system.membus.respLayer1.utilization 0.8 # Layer utilization (%) 331system.cpu.branchPred.lookups 205596082 # Number of BP lookups 332system.cpu.branchPred.condPredicted 205596082 # Number of conditional branches predicted 333system.cpu.branchPred.condIncorrect 9898225 # Number of conditional branches incorrect 334system.cpu.branchPred.BTBLookups 117113450 # Number of BTB lookups 335system.cpu.branchPred.BTBHits 114684719 # Number of BTB hits |
| 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 336system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 186system.cpu.branchPred.BTBHitPct 97.965231 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 25073647 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 1800250 # Number of incorrect RAS predictions. | 337system.cpu.branchPred.BTBHitPct 97.926172 # BTB Hit Percentage 338system.cpu.branchPred.usedRAS 25065236 # Number of times the RAS was used to get a target. 339system.cpu.branchPred.RASInCorrect 1793499 # Number of incorrect RAS predictions. |
| 189system.cpu.workload.num_syscalls 551 # Number of system calls | 340system.cpu.workload.num_syscalls 551 # Number of system calls |
| 190system.cpu.numCycles 903825131 # number of cpu cycles simulated | 341system.cpu.numCycles 916341755 # number of cpu cycles simulated |
| 191system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 192system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 342system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 343system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 193system.cpu.fetch.icacheStallCycles 167418043 # Number of cycles fetch is stalled on an Icache miss 194system.cpu.fetch.Insts 1132282338 # Number of instructions fetch has processed 195system.cpu.fetch.Branches 205621718 # Number of branches that fetch encountered 196system.cpu.fetch.predictedBranches 139769125 # Number of branches that fetch has predicted taken 197system.cpu.fetch.Cycles 352430400 # Number of cycles fetch has run and was not squashing or blocked 198system.cpu.fetch.SquashCycles 71153000 # Number of cycles fetch has spent squashing 199system.cpu.fetch.BlockedCycles 297148174 # Number of cycles fetch has spent blocked 200system.cpu.fetch.MiscStallCycles 48797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 201system.cpu.fetch.PendingTrapStallCycles 255592 # Number of stall cycles due to pending traps 202system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR 203system.cpu.fetch.CacheLines 162064992 # Number of cache lines fetched 204system.cpu.fetch.IcacheSquashes 2572532 # Number of outstanding Icache misses that were squashed 205system.cpu.fetch.rateDist::samples 878293133 # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::mean 2.398381 # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::stdev 3.331165 # Number of instructions fetched each cycle (Total) | 344system.cpu.fetch.icacheStallCycles 167380851 # Number of cycles fetch is stalled on an Icache miss 345system.cpu.fetch.Insts 1131684299 # Number of instructions fetch has processed 346system.cpu.fetch.Branches 205596082 # Number of branches that fetch encountered 347system.cpu.fetch.predictedBranches 139749955 # Number of branches that fetch has predicted taken 348system.cpu.fetch.Cycles 352238514 # Number of cycles fetch has run and was not squashing or blocked 349system.cpu.fetch.SquashCycles 71080243 # Number of cycles fetch has spent squashing 350system.cpu.fetch.BlockedCycles 303608780 # Number of cycles fetch has spent blocked 351system.cpu.fetch.MiscStallCycles 49221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 352system.cpu.fetch.PendingTrapStallCycles 257762 # Number of stall cycles due to pending traps 353system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR 354system.cpu.fetch.CacheLines 162013900 # Number of cache lines fetched 355system.cpu.fetch.IcacheSquashes 2533511 # Number of outstanding Icache misses that were squashed 356system.cpu.fetch.rateDist::samples 884463501 # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::mean 2.380571 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::stdev 3.325217 # Number of instructions fetched each cycle (Total) |
| 208system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 359system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 209system.cpu.fetch.rateDist::0 529920988 60.34% 60.34% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::1 23389932 2.66% 63.00% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::2 25306191 2.88% 65.88% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::3 27947555 3.18% 69.06% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::4 17765128 2.02% 71.08% # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::5 22905202 2.61% 73.69% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::6 29375609 3.34% 77.04% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::7 26663527 3.04% 80.07% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::8 175019001 19.93% 100.00% # Number of instructions fetched each cycle (Total) | 360system.cpu.fetch.rateDist::0 536297540 60.64% 60.64% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::1 23375974 2.64% 63.28% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::2 25249823 2.85% 66.13% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::3 27885460 3.15% 69.29% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::4 17746776 2.01% 71.29% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::5 22912915 2.59% 73.88% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::6 29432713 3.33% 77.21% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::7 26649868 3.01% 80.22% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::8 174912432 19.78% 100.00% # Number of instructions fetched each cycle (Total) |
| 218system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 369system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 221system.cpu.fetch.rateDist::total 878293133 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.branchRate 0.227502 # Number of branch fetches per cycle 223system.cpu.fetch.rate 1.252767 # Number of inst fetches per cycle 224system.cpu.decode.IdleCycles 222360951 # Number of cycles decode is idle 225system.cpu.decode.BlockedCycles 252528998 # Number of cycles decode is blocked 226system.cpu.decode.RunCycles 295744531 # Number of cycles decode is running 227system.cpu.decode.UnblockCycles 46666559 # Number of cycles decode is unblocking 228system.cpu.decode.SquashCycles 60992094 # Number of cycles decode is squashing 229system.cpu.decode.DecodedInsts 2071948592 # Number of instructions handled by decode 230system.cpu.rename.SquashCycles 60992094 # Number of cycles rename is squashing 231system.cpu.rename.IdleCycles 255743691 # Number of cycles rename is idle 232system.cpu.rename.BlockCycles 109858014 # Number of cycles rename is blocking 233system.cpu.rename.serializeStallCycles 17204 # count of cycles rename stalled for serializing inst 234system.cpu.rename.RunCycles 306968990 # Number of cycles rename is running 235system.cpu.rename.UnblockCycles 144713140 # Number of cycles rename is unblocking 236system.cpu.rename.RenamedInsts 2035757004 # Number of instructions processed by rename 237system.cpu.rename.ROBFullEvents 14813 # Number of times rename has blocked due to ROB full 238system.cpu.rename.IQFullEvents 25048489 # Number of times rename has blocked due to IQ full 239system.cpu.rename.LSQFullEvents 104458594 # Number of times rename has blocked due to LSQ full 240system.cpu.rename.FullRegisterEvents 180 # Number of times there has been no free registers 241system.cpu.rename.RenamedOperands 2138803025 # Number of destination operands rename has renamed 242system.cpu.rename.RenameLookups 5151932301 # Number of register rename lookups that rename has made 243system.cpu.rename.int_rename_lookups 5151817228 # Number of integer rename lookups 244system.cpu.rename.fp_rename_lookups 115073 # Number of floating rename lookups | 372system.cpu.fetch.rateDist::total 884463501 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.branchRate 0.224366 # Number of branch fetches per cycle 374system.cpu.fetch.rate 1.235002 # Number of inst fetches per cycle 375system.cpu.decode.IdleCycles 222590662 # Number of cycles decode is idle 376system.cpu.decode.BlockedCycles 258678079 # Number of cycles decode is blocked 377system.cpu.decode.RunCycles 295142458 # Number of cycles decode is running 378system.cpu.decode.UnblockCycles 47123970 # Number of cycles decode is unblocking 379system.cpu.decode.SquashCycles 60928332 # Number of cycles decode is squashing 380system.cpu.decode.DecodedInsts 2071292159 # Number of instructions handled by decode 381system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode 382system.cpu.rename.SquashCycles 60928332 # Number of cycles rename is squashing 383system.cpu.rename.IdleCycles 256060013 # Number of cycles rename is idle 384system.cpu.rename.BlockCycles 114129471 # Number of cycles rename is blocking 385system.cpu.rename.serializeStallCycles 17113 # count of cycles rename stalled for serializing inst 386system.cpu.rename.RunCycles 306672128 # Number of cycles rename is running 387system.cpu.rename.UnblockCycles 146656444 # Number of cycles rename is unblocking 388system.cpu.rename.RenamedInsts 2035150603 # Number of instructions processed by rename 389system.cpu.rename.ROBFullEvents 19208 # Number of times rename has blocked due to ROB full 390system.cpu.rename.IQFullEvents 24905685 # Number of times rename has blocked due to IQ full 391system.cpu.rename.LSQFullEvents 106527720 # Number of times rename has blocked due to LSQ full 392system.cpu.rename.FullRegisterEvents 191 # Number of times there has been no free registers 393system.cpu.rename.RenamedOperands 2137983634 # Number of destination operands rename has renamed 394system.cpu.rename.RenameLookups 5150411981 # Number of register rename lookups that rename has made 395system.cpu.rename.int_rename_lookups 5150294631 # Number of integer rename lookups 396system.cpu.rename.fp_rename_lookups 117350 # Number of floating rename lookups |
| 245system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed | 397system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed |
| 246system.cpu.rename.UndoneMaps 524762171 # Number of HB maps that are undone due to squashing 247system.cpu.rename.serializingInsts 1163 # count of serializing insts renamed 248system.cpu.rename.tempSerializingInsts 1096 # count of temporary serializing insts renamed 249system.cpu.rename.skidInsts 344343454 # count of insts added to the skid buffer 250system.cpu.memDep0.insertedLoads 496005535 # Number of loads inserted to the mem dependence unit. 251system.cpu.memDep0.insertedStores 194479256 # Number of stores inserted to the mem dependence unit. 252system.cpu.memDep0.conflictingLoads 195803959 # Number of conflicting loads. 253system.cpu.memDep0.conflictingStores 55147463 # Number of conflicting stores. 254system.cpu.iq.iqInstsAdded 1975947809 # Number of instructions added to the IQ (excludes non-spec) 255system.cpu.iq.iqNonSpecInstsAdded 16072 # Number of non-speculative instructions added to the IQ 256system.cpu.iq.iqInstsIssued 1772430246 # Number of instructions issued 257system.cpu.iq.iqSquashedInstsIssued 489293 # Number of squashed instructions issued 258system.cpu.iq.iqSquashedInstsExamined 442088890 # Number of squashed instructions iterated over during squash; mainly for profiling 259system.cpu.iq.iqSquashedOperandsExamined 735772933 # Number of squashed operands that are examined and possibly removed from graph 260system.cpu.iq.iqSquashedNonSpecRemoved 15520 # Number of squashed non-spec instructions that were removed 261system.cpu.iq.issued_per_cycle::samples 878293133 # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::mean 2.018040 # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::stdev 1.884895 # Number of insts issued each cycle | 398system.cpu.rename.UndoneMaps 523942780 # Number of HB maps that are undone due to squashing 399system.cpu.rename.serializingInsts 1169 # count of serializing insts renamed 400system.cpu.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed 401system.cpu.rename.skidInsts 347123881 # count of insts added to the skid buffer 402system.cpu.memDep0.insertedLoads 495862419 # Number of loads inserted to the mem dependence unit. 403system.cpu.memDep0.insertedStores 194434977 # Number of stores inserted to the mem dependence unit. 404system.cpu.memDep0.conflictingLoads 195681210 # Number of conflicting loads. 405system.cpu.memDep0.conflictingStores 55050050 # Number of conflicting stores. 406system.cpu.iq.iqInstsAdded 1975391803 # Number of instructions added to the IQ (excludes non-spec) 407system.cpu.iq.iqNonSpecInstsAdded 13688 # Number of non-speculative instructions added to the IQ 408system.cpu.iq.iqInstsIssued 1772107860 # Number of instructions issued 409system.cpu.iq.iqSquashedInstsIssued 473436 # Number of squashed instructions issued 410system.cpu.iq.iqSquashedInstsExamined 441529176 # Number of squashed instructions iterated over during squash; mainly for profiling 411system.cpu.iq.iqSquashedOperandsExamined 734849750 # Number of squashed operands that are examined and possibly removed from graph 412system.cpu.iq.iqSquashedNonSpecRemoved 13136 # Number of squashed non-spec instructions that were removed 413system.cpu.iq.issued_per_cycle::samples 884463501 # Number of insts issued each cycle 414system.cpu.iq.issued_per_cycle::mean 2.003596 # Number of insts issued each cycle 415system.cpu.iq.issued_per_cycle::stdev 1.883133 # Number of insts issued each cycle |
| 264system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 416system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 265system.cpu.iq.issued_per_cycle::0 263200988 29.97% 29.97% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::1 149900664 17.07% 47.03% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::2 137095286 15.61% 62.64% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::3 132054982 15.04% 77.68% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::4 91669420 10.44% 88.12% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::5 56193413 6.40% 94.51% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::6 34492530 3.93% 98.44% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::7 11912661 1.36% 99.80% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::8 1773189 0.20% 100.00% # Number of insts issued each cycle | 417system.cpu.iq.issued_per_cycle::0 267821241 30.28% 30.28% # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::1 151877147 17.17% 47.45% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::2 137227346 15.52% 62.97% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::3 131884953 14.91% 77.88% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::4 91607169 10.36% 88.24% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::5 55986805 6.33% 94.57% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::6 34422638 3.89% 98.46% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::7 11866983 1.34% 99.80% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::8 1769219 0.20% 100.00% # Number of insts issued each cycle |
| 274system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 426system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 277system.cpu.iq.issued_per_cycle::total 878293133 # Number of insts issued each cycle | 429system.cpu.iq.issued_per_cycle::total 884463501 # Number of insts issued each cycle |
| 278system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 430system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 279system.cpu.iq.fu_full::IntAlu 4998230 32.74% 32.74% # attempts to use FU when none available 280system.cpu.iq.fu_full::IntMult 0 0.00% 32.74% # attempts to use FU when none available 281system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available 282system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available 287system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available 308system.cpu.iq.fu_full::MemRead 7655755 50.14% 82.88% # attempts to use FU when none available 309system.cpu.iq.fu_full::MemWrite 2613853 17.12% 100.00% # attempts to use FU when none available | 431system.cpu.iq.fu_full::IntAlu 4968361 32.63% 32.63% # attempts to use FU when none available 432system.cpu.iq.fu_full::IntMult 0 0.00% 32.63% # attempts to use FU when none available 433system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available 434system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available 435system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available 460system.cpu.iq.fu_full::MemRead 7638299 50.16% 82.79% # attempts to use FU when none available 461system.cpu.iq.fu_full::MemWrite 2620527 17.21% 100.00% # attempts to use FU when none available |
| 310system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 311system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 462system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 463system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 312system.cpu.iq.FU_type_0::No_OpClass 2627910 0.15% 0.15% # Type of FU issued 313system.cpu.iq.FU_type_0::IntAlu 1165981895 65.78% 65.93% # Type of FU issued 314system.cpu.iq.FU_type_0::IntMult 352516 0.02% 65.95% # Type of FU issued 315system.cpu.iq.FU_type_0::IntDiv 3880818 0.22% 66.17% # Type of FU issued | 464system.cpu.iq.FU_type_0::No_OpClass 2623300 0.15% 0.15% # Type of FU issued 465system.cpu.iq.FU_type_0::IntAlu 1165765153 65.78% 65.93% # Type of FU issued 466system.cpu.iq.FU_type_0::IntMult 352884 0.02% 65.95% # Type of FU issued 467system.cpu.iq.FU_type_0::IntDiv 3880872 0.22% 66.17% # Type of FU issued |
| 316system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued 321system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 334system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued | 468system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued 469system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 486system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued |
| 342system.cpu.iq.FU_type_0::MemRead 429341212 24.22% 90.39% # Type of FU issued 343system.cpu.iq.FU_type_0::MemWrite 170245895 9.61% 100.00% # Type of FU issued | 494system.cpu.iq.FU_type_0::MemRead 429256529 24.22% 90.39% # Type of FU issued 495system.cpu.iq.FU_type_0::MemWrite 170229122 9.61% 100.00% # Type of FU issued |
| 344system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 345system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 496system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 497system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 346system.cpu.iq.FU_type_0::total 1772430246 # Type of FU issued 347system.cpu.iq.rate 1.961032 # Inst issue rate 348system.cpu.iq.fu_busy_cnt 15267838 # FU busy when requested 349system.cpu.iq.fu_busy_rate 0.008614 # FU busy rate (busy events/executed inst) 350system.cpu.iq.int_inst_queue_reads 4438895750 # Number of integer instruction queue reads 351system.cpu.iq.int_inst_queue_writes 2418277528 # Number of integer instruction queue writes 352system.cpu.iq.int_inst_queue_wakeup_accesses 1745063548 # Number of integer instruction queue wakeup accesses 353system.cpu.iq.fp_inst_queue_reads 15006 # Number of floating instruction queue reads 354system.cpu.iq.fp_inst_queue_writes 33162 # Number of floating instruction queue writes 355system.cpu.iq.fp_inst_queue_wakeup_accesses 3630 # Number of floating instruction queue wakeup accesses 356system.cpu.iq.int_alu_accesses 1785062995 # Number of integer alu accesses 357system.cpu.iq.fp_alu_accesses 7179 # Number of floating point alu accesses 358system.cpu.iew.lsq.thread0.forwLoads 172239839 # Number of loads that had data forwarded from stores | 498system.cpu.iq.FU_type_0::total 1772107860 # Type of FU issued 499system.cpu.iq.rate 1.933894 # Inst issue rate 500system.cpu.iq.fu_busy_cnt 15227187 # FU busy when requested 501system.cpu.iq.fu_busy_rate 0.008593 # FU busy rate (busy events/executed inst) 502system.cpu.iq.int_inst_queue_reads 4444363529 # Number of integer instruction queue reads 503system.cpu.iq.int_inst_queue_writes 2417156929 # Number of integer instruction queue writes 504system.cpu.iq.int_inst_queue_wakeup_accesses 1744871940 # Number of integer instruction queue wakeup accesses 505system.cpu.iq.fp_inst_queue_reads 16315 # Number of floating instruction queue reads 506system.cpu.iq.fp_inst_queue_writes 34548 # Number of floating instruction queue writes 507system.cpu.iq.fp_inst_queue_wakeup_accesses 3820 # Number of floating instruction queue wakeup accesses 508system.cpu.iq.int_alu_accesses 1784704039 # Number of integer alu accesses 509system.cpu.iq.fp_alu_accesses 7708 # Number of floating point alu accesses 510system.cpu.iew.lsq.thread0.forwLoads 172523009 # Number of loads that had data forwarded from stores |
| 359system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 511system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 360system.cpu.iew.lsq.thread0.squashedLoads 111903378 # Number of loads squashed 361system.cpu.iew.lsq.thread0.ignoredResponses 383433 # Number of memory responses ignored because the instruction is squashed 362system.cpu.iew.lsq.thread0.memOrderViolation 329474 # Number of memory ordering violations 363system.cpu.iew.lsq.thread0.squashedStores 45320259 # Number of stores squashed | 512system.cpu.iew.lsq.thread0.squashedLoads 111760262 # Number of loads squashed 513system.cpu.iew.lsq.thread0.ignoredResponses 384025 # Number of memory responses ignored because the instruction is squashed 514system.cpu.iew.lsq.thread0.memOrderViolation 328721 # Number of memory ordering violations 515system.cpu.iew.lsq.thread0.squashedStores 45275855 # Number of stores squashed |
| 364system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 365system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 516system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 517system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 366system.cpu.iew.lsq.thread0.rescheduledLoads 14682 # Number of loads that were rescheduled 367system.cpu.iew.lsq.thread0.cacheBlocked 568 # Number of times an access to memory failed due to the cache being blocked | 518system.cpu.iew.lsq.thread0.rescheduledLoads 15305 # Number of loads that were rescheduled 519system.cpu.iew.lsq.thread0.cacheBlocked 564 # Number of times an access to memory failed due to the cache being blocked |
| 368system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 520system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 369system.cpu.iew.iewSquashCycles 60992094 # Number of cycles IEW is squashing 370system.cpu.iew.iewBlockCycles 64075051 # Number of cycles IEW is blocking 371system.cpu.iew.iewUnblockCycles 7111223 # Number of cycles IEW is unblocking 372system.cpu.iew.iewDispatchedInsts 1975963881 # Number of instructions dispatched to IQ 373system.cpu.iew.iewDispSquashedInsts 801543 # Number of squashed instructions skipped by dispatch 374system.cpu.iew.iewDispLoadInsts 496005535 # Number of dispatched load instructions 375system.cpu.iew.iewDispStoreInsts 194480445 # Number of dispatched store instructions 376system.cpu.iew.iewDispNonSpecInsts 3509 # Number of dispatched non-speculative instructions 377system.cpu.iew.iewIQFullEvents 4460880 # Number of times the IQ has become full, causing a stall 378system.cpu.iew.iewLSQFullEvents 83569 # Number of times the LSQ has become full, causing a stall 379system.cpu.iew.memOrderViolationEvents 329474 # Number of memory order violations 380system.cpu.iew.predictedTakenIncorrect 5903386 # Number of branches that were predicted taken incorrectly 381system.cpu.iew.predictedNotTakenIncorrect 4417104 # Number of branches that were predicted not taken incorrectly 382system.cpu.iew.branchMispredicts 10320490 # Number of branch mispredicts detected at execute 383system.cpu.iew.iewExecutedInsts 1753197001 # Number of executed instructions 384system.cpu.iew.iewExecLoadInsts 424204757 # Number of load instructions executed 385system.cpu.iew.iewExecSquashedInsts 19233245 # Number of squashed instructions skipped in execute | 521system.cpu.iew.iewSquashCycles 60928332 # Number of cycles IEW is squashing 522system.cpu.iew.iewBlockCycles 66654454 # Number of cycles IEW is blocking 523system.cpu.iew.iewUnblockCycles 7158115 # Number of cycles IEW is unblocking 524system.cpu.iew.iewDispatchedInsts 1975405491 # Number of instructions dispatched to IQ 525system.cpu.iew.iewDispSquashedInsts 788328 # Number of squashed instructions skipped by dispatch 526system.cpu.iew.iewDispLoadInsts 495862419 # Number of dispatched load instructions 527system.cpu.iew.iewDispStoreInsts 194436041 # Number of dispatched store instructions 528system.cpu.iew.iewDispNonSpecInsts 3451 # Number of dispatched non-speculative instructions 529system.cpu.iew.iewIQFullEvents 4460839 # Number of times the IQ has become full, causing a stall 530system.cpu.iew.iewLSQFullEvents 82816 # Number of times the LSQ has become full, causing a stall 531system.cpu.iew.memOrderViolationEvents 328721 # Number of memory order violations 532system.cpu.iew.predictedTakenIncorrect 5900080 # Number of branches that were predicted taken incorrectly 533system.cpu.iew.predictedNotTakenIncorrect 4426535 # Number of branches that were predicted not taken incorrectly 534system.cpu.iew.branchMispredicts 10326615 # Number of branch mispredicts detected at execute 535system.cpu.iew.iewExecutedInsts 1752972690 # Number of executed instructions 536system.cpu.iew.iewExecLoadInsts 424121378 # Number of load instructions executed 537system.cpu.iew.iewExecSquashedInsts 19135170 # Number of squashed instructions skipped in execute |
| 386system.cpu.iew.exec_swp 0 # number of swp insts executed 387system.cpu.iew.exec_nop 0 # number of nop insts executed | 538system.cpu.iew.exec_swp 0 # number of swp insts executed 539system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 388system.cpu.iew.exec_refs 591004689 # number of memory reference insts executed 389system.cpu.iew.exec_branches 167488871 # Number of branches executed 390system.cpu.iew.exec_stores 166799932 # Number of stores executed 391system.cpu.iew.exec_rate 1.939752 # Inst execution rate 392system.cpu.iew.wb_sent 1749947599 # cumulative count of insts sent to commit 393system.cpu.iew.wb_count 1745067178 # cumulative count of insts written-back 394system.cpu.iew.wb_producers 1326505641 # num instructions producing a value 395system.cpu.iew.wb_consumers 1948512890 # num instructions consuming a value | 540system.cpu.iew.exec_refs 590916604 # number of memory reference insts executed 541system.cpu.iew.exec_branches 167471832 # Number of branches executed 542system.cpu.iew.exec_stores 166795226 # Number of stores executed 543system.cpu.iew.exec_rate 1.913012 # Inst execution rate 544system.cpu.iew.wb_sent 1749734148 # cumulative count of insts sent to commit 545system.cpu.iew.wb_count 1744875760 # cumulative count of insts written-back 546system.cpu.iew.wb_producers 1325266031 # num instructions producing a value 547system.cpu.iew.wb_consumers 1946145137 # num instructions consuming a value |
| 396system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 548system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 397system.cpu.iew.wb_rate 1.930758 # insts written-back per cycle 398system.cpu.iew.wb_fanout 0.680778 # average fanout of values written-back | 549system.cpu.iew.wb_rate 1.904176 # insts written-back per cycle 550system.cpu.iew.wb_fanout 0.680970 # average fanout of values written-back |
| 399system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 551system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 400system.cpu.commit.commitSquashedInsts 447002783 # The number of squashed insts skipped by commit | 552system.cpu.commit.commitSquashedInsts 446445392 # The number of squashed insts skipped by commit |
| 401system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 553system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 402system.cpu.commit.branchMispredicts 9936450 # The number of times a branch was mispredicted 403system.cpu.commit.committed_per_cycle::samples 817301039 # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::mean 1.870778 # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::stdev 2.444599 # Number of insts commited each cycle | 554system.cpu.commit.branchMispredicts 9927956 # The number of times a branch was mispredicted 555system.cpu.commit.committed_per_cycle::samples 823535169 # Number of insts commited each cycle 556system.cpu.commit.committed_per_cycle::mean 1.856616 # Number of insts commited each cycle 557system.cpu.commit.committed_per_cycle::stdev 2.436023 # Number of insts commited each cycle |
| 406system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 558system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 407system.cpu.commit.committed_per_cycle::0 326881530 40.00% 40.00% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::1 191845418 23.47% 63.47% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::2 62847977 7.69% 71.16% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::3 92272413 11.29% 82.45% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::4 25036529 3.06% 85.51% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::5 27653799 3.38% 88.89% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::6 9274477 1.13% 90.03% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::7 11343051 1.39% 91.42% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::8 70145845 8.58% 100.00% # Number of insts commited each cycle | 559system.cpu.commit.committed_per_cycle::0 331309797 40.23% 40.23% # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::1 193436575 23.49% 63.72% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::2 63121599 7.66% 71.38% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::3 92647186 11.25% 82.63% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::4 25073312 3.04% 85.68% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::5 27553603 3.35% 89.02% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::6 9217324 1.12% 90.14% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::7 11404021 1.38% 91.53% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::8 69771752 8.47% 100.00% # Number of insts commited each cycle |
| 416system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 568system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 419system.cpu.commit.committed_per_cycle::total 817301039 # Number of insts commited each cycle | 571system.cpu.commit.committed_per_cycle::total 823535169 # Number of insts commited each cycle |
| 420system.cpu.commit.committedInsts 826877109 # Number of instructions committed 421system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 422system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 423system.cpu.commit.refs 533262343 # Number of memory references committed 424system.cpu.commit.loads 384102157 # Number of loads committed 425system.cpu.commit.membars 0 # Number of memory barriers committed 426system.cpu.commit.branches 149758583 # Number of branches committed 427system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 428system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. 429system.cpu.commit.function_calls 17673145 # Number of function calls committed. | 572system.cpu.commit.committedInsts 826877109 # Number of instructions committed 573system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 574system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 575system.cpu.commit.refs 533262343 # Number of memory references committed 576system.cpu.commit.loads 384102157 # Number of loads committed 577system.cpu.commit.membars 0 # Number of memory barriers committed 578system.cpu.commit.branches 149758583 # Number of branches committed 579system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 580system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. 581system.cpu.commit.function_calls 17673145 # Number of function calls committed. |
| 430system.cpu.commit.bw_lim_events 70145845 # number cycles where commit BW limit reached | 582system.cpu.commit.bw_lim_events 69771752 # number cycles where commit BW limit reached |
| 431system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 583system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 432system.cpu.rob.rob_reads 2723146678 # The number of ROB reads 433system.cpu.rob.rob_writes 4013137574 # The number of ROB writes 434system.cpu.timesIdled 3358951 # Number of times that the entire CPU went into an idle state and unscheduled itself 435system.cpu.idleCycles 25531998 # Total number of cycles that the CPU has spent unscheduled due to idling | 584system.cpu.rob.rob_reads 2729197510 # The number of ROB reads 585system.cpu.rob.rob_writes 4011957603 # The number of ROB writes 586system.cpu.timesIdled 3360338 # Number of times that the entire CPU went into an idle state and unscheduled itself 587system.cpu.idleCycles 31878254 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 436system.cpu.committedInsts 826877109 # Number of Instructions Simulated 437system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 438system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated | 588system.cpu.committedInsts 826877109 # Number of Instructions Simulated 589system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 590system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated |
| 439system.cpu.cpi 1.093059 # CPI: Cycles Per Instruction 440system.cpu.cpi_total 1.093059 # CPI: Total CPI of All Threads 441system.cpu.ipc 0.914864 # IPC: Instructions Per Cycle 442system.cpu.ipc_total 0.914864 # IPC: Total IPC of All Threads 443system.cpu.int_regfile_reads 3313860690 # number of integer regfile reads 444system.cpu.int_regfile_writes 1826087017 # number of integer regfile writes 445system.cpu.fp_regfile_reads 3611 # number of floating regfile reads 446system.cpu.fp_regfile_writes 20 # number of floating regfile writes 447system.cpu.misc_regfile_reads 964797382 # number of misc regfile reads | 591system.cpu.cpi 1.108196 # CPI: Cycles Per Instruction 592system.cpu.cpi_total 1.108196 # CPI: Total CPI of All Threads 593system.cpu.ipc 0.902368 # IPC: Instructions Per Cycle 594system.cpu.ipc_total 0.902368 # IPC: Total IPC of All Threads 595system.cpu.int_regfile_reads 3313525285 # number of integer regfile reads 596system.cpu.int_regfile_writes 1825886137 # number of integer regfile writes 597system.cpu.fp_regfile_reads 3803 # number of floating regfile reads 598system.cpu.fp_regfile_writes 18 # number of floating regfile writes 599system.cpu.misc_regfile_reads 964657168 # number of misc regfile reads |
| 448system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 600system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 449system.cpu.icache.replacements 5491 # number of replacements 450system.cpu.icache.tagsinuse 1036.603099 # Cycle average of tags in use 451system.cpu.icache.total_refs 161916606 # Total number of references to valid blocks. 452system.cpu.icache.sampled_refs 7071 # Sample count of references to valid blocks. 453system.cpu.icache.avg_refs 22898.685617 # Average number of references to valid blocks. | 601system.cpu.toL2Bus.throughput 699341277 # Throughput (bytes/s) 602system.cpu.toL2Bus.trans_dist::ReadReq 1903111 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::ReadResp 1903110 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::Writeback 2330801 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::UpgradeReq 133805 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::UpgradeResp 133805 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadExReq 771738 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadExResp 771738 # Transaction distribution 609system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 147545 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7666657 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_count 7814202 # Packet count per connected master and slave (bytes) 612system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 436416 # Cumulative packet size per connected master and slave (bytes) 613system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311355136 # Cumulative packet size per connected master and slave (bytes) 614system.cpu.toL2Bus.tot_pkt_size 311791552 # Cumulative packet size per connected master and slave (bytes) 615system.cpu.toL2Bus.data_through_bus 311791552 # Total data (bytes) 616system.cpu.toL2Bus.snoop_data_through_bus 8569984 # Total snoop data (bytes) 617system.cpu.toL2Bus.reqLayer0.occupancy 4904454883 # Layer occupancy (ticks) 618system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 619system.cpu.toL2Bus.respLayer0.occupancy 211090494 # Layer occupancy (ticks) 620system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 621system.cpu.toL2Bus.respLayer1.occupancy 3868088996 # Layer occupancy (ticks) 622system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 623system.cpu.icache.replacements 5303 # number of replacements 624system.cpu.icache.tagsinuse 1039.981291 # Cycle average of tags in use 625system.cpu.icache.total_refs 161869191 # Total number of references to valid blocks. 626system.cpu.icache.sampled_refs 6885 # Sample count of references to valid blocks. 627system.cpu.icache.avg_refs 23510.412636 # Average number of references to valid blocks. |
| 454system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 628system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 455system.cpu.icache.occ_blocks::cpu.inst 1036.603099 # Average occupied blocks per requestor 456system.cpu.icache.occ_percent::cpu.inst 0.506154 # Average percentage of cache occupancy 457system.cpu.icache.occ_percent::total 0.506154 # Average percentage of cache occupancy 458system.cpu.icache.ReadReq_hits::cpu.inst 161918575 # number of ReadReq hits 459system.cpu.icache.ReadReq_hits::total 161918575 # number of ReadReq hits 460system.cpu.icache.demand_hits::cpu.inst 161918575 # number of demand (read+write) hits 461system.cpu.icache.demand_hits::total 161918575 # number of demand (read+write) hits 462system.cpu.icache.overall_hits::cpu.inst 161918575 # number of overall hits 463system.cpu.icache.overall_hits::total 161918575 # number of overall hits 464system.cpu.icache.ReadReq_misses::cpu.inst 146417 # number of ReadReq misses 465system.cpu.icache.ReadReq_misses::total 146417 # number of ReadReq misses 466system.cpu.icache.demand_misses::cpu.inst 146417 # number of demand (read+write) misses 467system.cpu.icache.demand_misses::total 146417 # number of demand (read+write) misses 468system.cpu.icache.overall_misses::cpu.inst 146417 # number of overall misses 469system.cpu.icache.overall_misses::total 146417 # number of overall misses 470system.cpu.icache.ReadReq_miss_latency::cpu.inst 875142000 # number of ReadReq miss cycles 471system.cpu.icache.ReadReq_miss_latency::total 875142000 # number of ReadReq miss cycles 472system.cpu.icache.demand_miss_latency::cpu.inst 875142000 # number of demand (read+write) miss cycles 473system.cpu.icache.demand_miss_latency::total 875142000 # number of demand (read+write) miss cycles 474system.cpu.icache.overall_miss_latency::cpu.inst 875142000 # number of overall miss cycles 475system.cpu.icache.overall_miss_latency::total 875142000 # number of overall miss cycles 476system.cpu.icache.ReadReq_accesses::cpu.inst 162064992 # number of ReadReq accesses(hits+misses) 477system.cpu.icache.ReadReq_accesses::total 162064992 # number of ReadReq accesses(hits+misses) 478system.cpu.icache.demand_accesses::cpu.inst 162064992 # number of demand (read+write) accesses 479system.cpu.icache.demand_accesses::total 162064992 # number of demand (read+write) accesses 480system.cpu.icache.overall_accesses::cpu.inst 162064992 # number of overall (read+write) accesses 481system.cpu.icache.overall_accesses::total 162064992 # number of overall (read+write) accesses 482system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses 483system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses 484system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses 485system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses 486system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses 487system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses 488system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5977.051845 # average ReadReq miss latency 489system.cpu.icache.ReadReq_avg_miss_latency::total 5977.051845 # average ReadReq miss latency 490system.cpu.icache.demand_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency 491system.cpu.icache.demand_avg_miss_latency::total 5977.051845 # average overall miss latency 492system.cpu.icache.overall_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency 493system.cpu.icache.overall_avg_miss_latency::total 5977.051845 # average overall miss latency 494system.cpu.icache.blocked_cycles::no_mshrs 1375 # number of cycles access was blocked 495system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 629system.cpu.icache.occ_blocks::cpu.inst 1039.981291 # Average occupied blocks per requestor 630system.cpu.icache.occ_percent::cpu.inst 0.507803 # Average percentage of cache occupancy 631system.cpu.icache.occ_percent::total 0.507803 # Average percentage of cache occupancy 632system.cpu.icache.ReadReq_hits::cpu.inst 161871216 # number of ReadReq hits 633system.cpu.icache.ReadReq_hits::total 161871216 # number of ReadReq hits 634system.cpu.icache.demand_hits::cpu.inst 161871216 # number of demand (read+write) hits 635system.cpu.icache.demand_hits::total 161871216 # number of demand (read+write) hits 636system.cpu.icache.overall_hits::cpu.inst 161871216 # number of overall hits 637system.cpu.icache.overall_hits::total 161871216 # number of overall hits 638system.cpu.icache.ReadReq_misses::cpu.inst 142683 # number of ReadReq misses 639system.cpu.icache.ReadReq_misses::total 142683 # number of ReadReq misses 640system.cpu.icache.demand_misses::cpu.inst 142683 # number of demand (read+write) misses 641system.cpu.icache.demand_misses::total 142683 # number of demand (read+write) misses 642system.cpu.icache.overall_misses::cpu.inst 142683 # number of overall misses 643system.cpu.icache.overall_misses::total 142683 # number of overall misses 644system.cpu.icache.ReadReq_miss_latency::cpu.inst 931781000 # number of ReadReq miss cycles 645system.cpu.icache.ReadReq_miss_latency::total 931781000 # number of ReadReq miss cycles 646system.cpu.icache.demand_miss_latency::cpu.inst 931781000 # number of demand (read+write) miss cycles 647system.cpu.icache.demand_miss_latency::total 931781000 # number of demand (read+write) miss cycles 648system.cpu.icache.overall_miss_latency::cpu.inst 931781000 # number of overall miss cycles 649system.cpu.icache.overall_miss_latency::total 931781000 # number of overall miss cycles 650system.cpu.icache.ReadReq_accesses::cpu.inst 162013899 # number of ReadReq accesses(hits+misses) 651system.cpu.icache.ReadReq_accesses::total 162013899 # number of ReadReq accesses(hits+misses) 652system.cpu.icache.demand_accesses::cpu.inst 162013899 # number of demand (read+write) accesses 653system.cpu.icache.demand_accesses::total 162013899 # number of demand (read+write) accesses 654system.cpu.icache.overall_accesses::cpu.inst 162013899 # number of overall (read+write) accesses 655system.cpu.icache.overall_accesses::total 162013899 # number of overall (read+write) accesses 656system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000881 # miss rate for ReadReq accesses 657system.cpu.icache.ReadReq_miss_rate::total 0.000881 # miss rate for ReadReq accesses 658system.cpu.icache.demand_miss_rate::cpu.inst 0.000881 # miss rate for demand accesses 659system.cpu.icache.demand_miss_rate::total 0.000881 # miss rate for demand accesses 660system.cpu.icache.overall_miss_rate::cpu.inst 0.000881 # miss rate for overall accesses 661system.cpu.icache.overall_miss_rate::total 0.000881 # miss rate for overall accesses 662system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6530.427591 # average ReadReq miss latency 663system.cpu.icache.ReadReq_avg_miss_latency::total 6530.427591 # average ReadReq miss latency 664system.cpu.icache.demand_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency 665system.cpu.icache.demand_avg_miss_latency::total 6530.427591 # average overall miss latency 666system.cpu.icache.overall_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency 667system.cpu.icache.overall_avg_miss_latency::total 6530.427591 # average overall miss latency 668system.cpu.icache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked 669system.cpu.icache.blocked_cycles::no_targets 250 # number of cycles access was blocked |
| 496system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked | 670system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked |
| 497system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 498system.cpu.icache.avg_blocked_cycles::no_mshrs 229.166667 # average number of cycles each access was blocked 499system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 671system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 672system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked 673system.cpu.icache.avg_blocked_cycles::no_targets 250 # average number of cycles each access was blocked |
| 500system.cpu.icache.fast_writes 0 # number of fast writes performed 501system.cpu.icache.cache_copies 0 # number of cache copies performed | 674system.cpu.icache.fast_writes 0 # number of fast writes performed 675system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 502system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits 503system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits 504system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits 505system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits 506system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits 507system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits 508system.cpu.icache.ReadReq_mshr_misses::cpu.inst 144572 # number of ReadReq MSHR misses 509system.cpu.icache.ReadReq_mshr_misses::total 144572 # number of ReadReq MSHR misses 510system.cpu.icache.demand_mshr_misses::cpu.inst 144572 # number of demand (read+write) MSHR misses 511system.cpu.icache.demand_mshr_misses::total 144572 # number of demand (read+write) MSHR misses 512system.cpu.icache.overall_mshr_misses::cpu.inst 144572 # number of overall MSHR misses 513system.cpu.icache.overall_mshr_misses::total 144572 # number of overall MSHR misses 514system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 521583500 # number of ReadReq MSHR miss cycles 515system.cpu.icache.ReadReq_mshr_miss_latency::total 521583500 # number of ReadReq MSHR miss cycles 516system.cpu.icache.demand_mshr_miss_latency::cpu.inst 521583500 # number of demand (read+write) MSHR miss cycles 517system.cpu.icache.demand_mshr_miss_latency::total 521583500 # number of demand (read+write) MSHR miss cycles 518system.cpu.icache.overall_mshr_miss_latency::cpu.inst 521583500 # number of overall MSHR miss cycles 519system.cpu.icache.overall_mshr_miss_latency::total 521583500 # number of overall MSHR miss cycles 520system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for ReadReq accesses 521system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000892 # mshr miss rate for ReadReq accesses 522system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for demand accesses 523system.cpu.icache.demand_mshr_miss_rate::total 0.000892 # mshr miss rate for demand accesses 524system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for overall accesses 525system.cpu.icache.overall_mshr_miss_rate::total 0.000892 # mshr miss rate for overall accesses 526system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3607.776748 # average ReadReq mshr miss latency 527system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3607.776748 # average ReadReq mshr miss latency 528system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency 529system.cpu.icache.demand_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency 530system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency 531system.cpu.icache.overall_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency | 676system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1957 # number of ReadReq MSHR hits 677system.cpu.icache.ReadReq_mshr_hits::total 1957 # number of ReadReq MSHR hits 678system.cpu.icache.demand_mshr_hits::cpu.inst 1957 # number of demand (read+write) MSHR hits 679system.cpu.icache.demand_mshr_hits::total 1957 # number of demand (read+write) MSHR hits 680system.cpu.icache.overall_mshr_hits::cpu.inst 1957 # number of overall MSHR hits 681system.cpu.icache.overall_mshr_hits::total 1957 # number of overall MSHR hits 682system.cpu.icache.ReadReq_mshr_misses::cpu.inst 140726 # number of ReadReq MSHR misses 683system.cpu.icache.ReadReq_mshr_misses::total 140726 # number of ReadReq MSHR misses 684system.cpu.icache.demand_mshr_misses::cpu.inst 140726 # number of demand (read+write) MSHR misses 685system.cpu.icache.demand_mshr_misses::total 140726 # number of demand (read+write) MSHR misses 686system.cpu.icache.overall_mshr_misses::cpu.inst 140726 # number of overall MSHR misses 687system.cpu.icache.overall_mshr_misses::total 140726 # number of overall MSHR misses 688system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 559745506 # number of ReadReq MSHR miss cycles 689system.cpu.icache.ReadReq_mshr_miss_latency::total 559745506 # number of ReadReq MSHR miss cycles 690system.cpu.icache.demand_mshr_miss_latency::cpu.inst 559745506 # number of demand (read+write) MSHR miss cycles 691system.cpu.icache.demand_mshr_miss_latency::total 559745506 # number of demand (read+write) MSHR miss cycles 692system.cpu.icache.overall_mshr_miss_latency::cpu.inst 559745506 # number of overall MSHR miss cycles 693system.cpu.icache.overall_mshr_miss_latency::total 559745506 # number of overall MSHR miss cycles 694system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for ReadReq accesses 695system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000869 # mshr miss rate for ReadReq accesses 696system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for demand accesses 697system.cpu.icache.demand_mshr_miss_rate::total 0.000869 # mshr miss rate for demand accesses 698system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for overall accesses 699system.cpu.icache.overall_mshr_miss_rate::total 0.000869 # mshr miss rate for overall accesses 700system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3977.555718 # average ReadReq mshr miss latency 701system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3977.555718 # average ReadReq mshr miss latency 702system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency 703system.cpu.icache.demand_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency 704system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency 705system.cpu.icache.overall_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency |
| 532system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 706system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 533system.cpu.l2cache.replacements 353019 # number of replacements 534system.cpu.l2cache.tagsinuse 29665.542211 # Cycle average of tags in use 535system.cpu.l2cache.total_refs 3698954 # Total number of references to valid blocks. 536system.cpu.l2cache.sampled_refs 385379 # Sample count of references to valid blocks. 537system.cpu.l2cache.avg_refs 9.598224 # Average number of references to valid blocks. 538system.cpu.l2cache.warmup_cycle 196543776500 # Cycle when the warmup percentage was hit. 539system.cpu.l2cache.occ_blocks::writebacks 21121.895278 # Average occupied blocks per requestor 540system.cpu.l2cache.occ_blocks::cpu.inst 226.041869 # Average occupied blocks per requestor 541system.cpu.l2cache.occ_blocks::cpu.data 8317.605064 # Average occupied blocks per requestor 542system.cpu.l2cache.occ_percent::writebacks 0.644589 # Average percentage of cache occupancy 543system.cpu.l2cache.occ_percent::cpu.inst 0.006898 # Average percentage of cache occupancy 544system.cpu.l2cache.occ_percent::cpu.data 0.253833 # Average percentage of cache occupancy 545system.cpu.l2cache.occ_percent::total 0.905321 # Average percentage of cache occupancy 546system.cpu.l2cache.ReadReq_hits::cpu.inst 3851 # number of ReadReq hits 547system.cpu.l2cache.ReadReq_hits::cpu.data 1587691 # number of ReadReq hits 548system.cpu.l2cache.ReadReq_hits::total 1591542 # number of ReadReq hits 549system.cpu.l2cache.Writeback_hits::writebacks 2331818 # number of Writeback hits 550system.cpu.l2cache.Writeback_hits::total 2331818 # number of Writeback hits 551system.cpu.l2cache.UpgradeReq_hits::cpu.data 1456 # number of UpgradeReq hits 552system.cpu.l2cache.UpgradeReq_hits::total 1456 # number of UpgradeReq hits 553system.cpu.l2cache.ReadExReq_hits::cpu.data 565593 # number of ReadExReq hits 554system.cpu.l2cache.ReadExReq_hits::total 565593 # number of ReadExReq hits 555system.cpu.l2cache.demand_hits::cpu.inst 3851 # number of demand (read+write) hits 556system.cpu.l2cache.demand_hits::cpu.data 2153284 # number of demand (read+write) hits 557system.cpu.l2cache.demand_hits::total 2157135 # number of demand (read+write) hits 558system.cpu.l2cache.overall_hits::cpu.inst 3851 # number of overall hits 559system.cpu.l2cache.overall_hits::cpu.data 2153284 # number of overall hits 560system.cpu.l2cache.overall_hits::total 2157135 # number of overall hits 561system.cpu.l2cache.ReadReq_misses::cpu.inst 3170 # number of ReadReq misses 562system.cpu.l2cache.ReadReq_misses::cpu.data 175625 # number of ReadReq misses 563system.cpu.l2cache.ReadReq_misses::total 178795 # number of ReadReq misses 564system.cpu.l2cache.UpgradeReq_misses::cpu.data 135999 # number of UpgradeReq misses 565system.cpu.l2cache.UpgradeReq_misses::total 135999 # number of UpgradeReq misses 566system.cpu.l2cache.ReadExReq_misses::cpu.data 206937 # number of ReadExReq misses 567system.cpu.l2cache.ReadExReq_misses::total 206937 # number of ReadExReq misses 568system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses 569system.cpu.l2cache.demand_misses::cpu.data 382562 # number of demand (read+write) misses 570system.cpu.l2cache.demand_misses::total 385732 # number of demand (read+write) misses 571system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses 572system.cpu.l2cache.overall_misses::cpu.data 382562 # number of overall misses 573system.cpu.l2cache.overall_misses::total 385732 # number of overall misses 574system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197656000 # number of ReadReq miss cycles 575system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10096367454 # number of ReadReq miss cycles 576system.cpu.l2cache.ReadReq_miss_latency::total 10294023454 # number of ReadReq miss cycles 577system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6513500 # number of UpgradeReq miss cycles 578system.cpu.l2cache.UpgradeReq_miss_latency::total 6513500 # number of UpgradeReq miss cycles 579system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10430438500 # number of ReadExReq miss cycles 580system.cpu.l2cache.ReadExReq_miss_latency::total 10430438500 # number of ReadExReq miss cycles 581system.cpu.l2cache.demand_miss_latency::cpu.inst 197656000 # number of demand (read+write) miss cycles 582system.cpu.l2cache.demand_miss_latency::cpu.data 20526805954 # number of demand (read+write) miss cycles 583system.cpu.l2cache.demand_miss_latency::total 20724461954 # number of demand (read+write) miss cycles 584system.cpu.l2cache.overall_miss_latency::cpu.inst 197656000 # number of overall miss cycles 585system.cpu.l2cache.overall_miss_latency::cpu.data 20526805954 # number of overall miss cycles 586system.cpu.l2cache.overall_miss_latency::total 20724461954 # number of overall miss cycles 587system.cpu.l2cache.ReadReq_accesses::cpu.inst 7021 # number of ReadReq accesses(hits+misses) 588system.cpu.l2cache.ReadReq_accesses::cpu.data 1763316 # number of ReadReq accesses(hits+misses) 589system.cpu.l2cache.ReadReq_accesses::total 1770337 # number of ReadReq accesses(hits+misses) 590system.cpu.l2cache.Writeback_accesses::writebacks 2331818 # number of Writeback accesses(hits+misses) 591system.cpu.l2cache.Writeback_accesses::total 2331818 # number of Writeback accesses(hits+misses) 592system.cpu.l2cache.UpgradeReq_accesses::cpu.data 137455 # number of UpgradeReq accesses(hits+misses) 593system.cpu.l2cache.UpgradeReq_accesses::total 137455 # number of UpgradeReq accesses(hits+misses) 594system.cpu.l2cache.ReadExReq_accesses::cpu.data 772530 # number of ReadExReq accesses(hits+misses) 595system.cpu.l2cache.ReadExReq_accesses::total 772530 # number of ReadExReq accesses(hits+misses) 596system.cpu.l2cache.demand_accesses::cpu.inst 7021 # number of demand (read+write) accesses 597system.cpu.l2cache.demand_accesses::cpu.data 2535846 # number of demand (read+write) accesses 598system.cpu.l2cache.demand_accesses::total 2542867 # number of demand (read+write) accesses 599system.cpu.l2cache.overall_accesses::cpu.inst 7021 # number of overall (read+write) accesses 600system.cpu.l2cache.overall_accesses::cpu.data 2535846 # number of overall (read+write) accesses 601system.cpu.l2cache.overall_accesses::total 2542867 # number of overall (read+write) accesses 602system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.451503 # miss rate for ReadReq accesses 603system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099599 # miss rate for ReadReq accesses 604system.cpu.l2cache.ReadReq_miss_rate::total 0.100995 # miss rate for ReadReq accesses 605system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989407 # miss rate for UpgradeReq accesses 606system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989407 # miss rate for UpgradeReq accesses 607system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.267869 # miss rate for ReadExReq accesses 608system.cpu.l2cache.ReadExReq_miss_rate::total 0.267869 # miss rate for ReadExReq accesses 609system.cpu.l2cache.demand_miss_rate::cpu.inst 0.451503 # miss rate for demand accesses 610system.cpu.l2cache.demand_miss_rate::cpu.data 0.150862 # miss rate for demand accesses 611system.cpu.l2cache.demand_miss_rate::total 0.151692 # miss rate for demand accesses 612system.cpu.l2cache.overall_miss_rate::cpu.inst 0.451503 # miss rate for overall accesses 613system.cpu.l2cache.overall_miss_rate::cpu.data 0.150862 # miss rate for overall accesses 614system.cpu.l2cache.overall_miss_rate::total 0.151692 # miss rate for overall accesses 615system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62352.050473 # average ReadReq miss latency 616system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57488.213261 # average ReadReq miss latency 617system.cpu.l2cache.ReadReq_avg_miss_latency::total 57574.448133 # average ReadReq miss latency 618system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.893735 # average UpgradeReq miss latency 619system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.893735 # average UpgradeReq miss latency 620system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50403.932115 # average ReadExReq miss latency 621system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50403.932115 # average ReadExReq miss latency 622system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62352.050473 # average overall miss latency 623system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53656.154961 # average overall miss latency 624system.cpu.l2cache.demand_avg_miss_latency::total 53727.619057 # average overall miss latency 625system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62352.050473 # average overall miss latency 626system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53656.154961 # average overall miss latency 627system.cpu.l2cache.overall_avg_miss_latency::total 53727.619057 # average overall miss latency | 707system.cpu.l2cache.replacements 352927 # number of replacements 708system.cpu.l2cache.tagsinuse 29672.787481 # Cycle average of tags in use 709system.cpu.l2cache.total_refs 3696932 # Total number of references to valid blocks. 710system.cpu.l2cache.sampled_refs 385290 # Sample count of references to valid blocks. 711system.cpu.l2cache.avg_refs 9.595193 # Average number of references to valid blocks. 712system.cpu.l2cache.warmup_cycle 199022750000 # Cycle when the warmup percentage was hit. 713system.cpu.l2cache.occ_blocks::writebacks 21119.606677 # Average occupied blocks per requestor 714system.cpu.l2cache.occ_blocks::cpu.inst 224.793859 # Average occupied blocks per requestor 715system.cpu.l2cache.occ_blocks::cpu.data 8328.386944 # Average occupied blocks per requestor 716system.cpu.l2cache.occ_percent::writebacks 0.644519 # Average percentage of cache occupancy 717system.cpu.l2cache.occ_percent::cpu.inst 0.006860 # Average percentage of cache occupancy 718system.cpu.l2cache.occ_percent::cpu.data 0.254162 # Average percentage of cache occupancy 719system.cpu.l2cache.occ_percent::total 0.905542 # Average percentage of cache occupancy 720system.cpu.l2cache.ReadReq_hits::cpu.inst 3655 # number of ReadReq hits 721system.cpu.l2cache.ReadReq_hits::cpu.data 1586785 # number of ReadReq hits 722system.cpu.l2cache.ReadReq_hits::total 1590440 # number of ReadReq hits 723system.cpu.l2cache.Writeback_hits::writebacks 2330801 # number of Writeback hits 724system.cpu.l2cache.Writeback_hits::total 2330801 # number of Writeback hits 725system.cpu.l2cache.UpgradeReq_hits::cpu.data 1461 # number of UpgradeReq hits 726system.cpu.l2cache.UpgradeReq_hits::total 1461 # number of UpgradeReq hits 727system.cpu.l2cache.ReadExReq_hits::cpu.data 564870 # number of ReadExReq hits 728system.cpu.l2cache.ReadExReq_hits::total 564870 # number of ReadExReq hits 729system.cpu.l2cache.demand_hits::cpu.inst 3655 # number of demand (read+write) hits 730system.cpu.l2cache.demand_hits::cpu.data 2151655 # number of demand (read+write) hits 731system.cpu.l2cache.demand_hits::total 2155310 # number of demand (read+write) hits 732system.cpu.l2cache.overall_hits::cpu.inst 3655 # number of overall hits 733system.cpu.l2cache.overall_hits::cpu.data 2151655 # number of overall hits 734system.cpu.l2cache.overall_hits::total 2155310 # number of overall hits 735system.cpu.l2cache.ReadReq_misses::cpu.inst 3165 # number of ReadReq misses 736system.cpu.l2cache.ReadReq_misses::cpu.data 175600 # number of ReadReq misses 737system.cpu.l2cache.ReadReq_misses::total 178765 # number of ReadReq misses 738system.cpu.l2cache.UpgradeReq_misses::cpu.data 132344 # number of UpgradeReq misses 739system.cpu.l2cache.UpgradeReq_misses::total 132344 # number of UpgradeReq misses 740system.cpu.l2cache.ReadExReq_misses::cpu.data 206868 # number of ReadExReq misses 741system.cpu.l2cache.ReadExReq_misses::total 206868 # number of ReadExReq misses 742system.cpu.l2cache.demand_misses::cpu.inst 3165 # number of demand (read+write) misses 743system.cpu.l2cache.demand_misses::cpu.data 382468 # number of demand (read+write) misses 744system.cpu.l2cache.demand_misses::total 385633 # number of demand (read+write) misses 745system.cpu.l2cache.overall_misses::cpu.inst 3165 # number of overall misses 746system.cpu.l2cache.overall_misses::cpu.data 382468 # number of overall misses 747system.cpu.l2cache.overall_misses::total 385633 # number of overall misses 748system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245367500 # number of ReadReq miss cycles 749system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13155433460 # number of ReadReq miss cycles 750system.cpu.l2cache.ReadReq_miss_latency::total 13400800960 # number of ReadReq miss cycles 751system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6275000 # number of UpgradeReq miss cycles 752system.cpu.l2cache.UpgradeReq_miss_latency::total 6275000 # number of UpgradeReq miss cycles 753system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14197844500 # number of ReadExReq miss cycles 754system.cpu.l2cache.ReadExReq_miss_latency::total 14197844500 # number of ReadExReq miss cycles 755system.cpu.l2cache.demand_miss_latency::cpu.inst 245367500 # number of demand (read+write) miss cycles 756system.cpu.l2cache.demand_miss_latency::cpu.data 27353277960 # number of demand (read+write) miss cycles 757system.cpu.l2cache.demand_miss_latency::total 27598645460 # number of demand (read+write) miss cycles 758system.cpu.l2cache.overall_miss_latency::cpu.inst 245367500 # number of overall miss cycles 759system.cpu.l2cache.overall_miss_latency::cpu.data 27353277960 # number of overall miss cycles 760system.cpu.l2cache.overall_miss_latency::total 27598645460 # number of overall miss cycles 761system.cpu.l2cache.ReadReq_accesses::cpu.inst 6820 # number of ReadReq accesses(hits+misses) 762system.cpu.l2cache.ReadReq_accesses::cpu.data 1762385 # number of ReadReq accesses(hits+misses) 763system.cpu.l2cache.ReadReq_accesses::total 1769205 # number of ReadReq accesses(hits+misses) 764system.cpu.l2cache.Writeback_accesses::writebacks 2330801 # number of Writeback accesses(hits+misses) 765system.cpu.l2cache.Writeback_accesses::total 2330801 # number of Writeback accesses(hits+misses) 766system.cpu.l2cache.UpgradeReq_accesses::cpu.data 133805 # number of UpgradeReq accesses(hits+misses) 767system.cpu.l2cache.UpgradeReq_accesses::total 133805 # number of UpgradeReq accesses(hits+misses) 768system.cpu.l2cache.ReadExReq_accesses::cpu.data 771738 # number of ReadExReq accesses(hits+misses) 769system.cpu.l2cache.ReadExReq_accesses::total 771738 # number of ReadExReq accesses(hits+misses) 770system.cpu.l2cache.demand_accesses::cpu.inst 6820 # number of demand (read+write) accesses 771system.cpu.l2cache.demand_accesses::cpu.data 2534123 # number of demand (read+write) accesses 772system.cpu.l2cache.demand_accesses::total 2540943 # number of demand (read+write) accesses 773system.cpu.l2cache.overall_accesses::cpu.inst 6820 # number of overall (read+write) accesses 774system.cpu.l2cache.overall_accesses::cpu.data 2534123 # number of overall (read+write) accesses 775system.cpu.l2cache.overall_accesses::total 2540943 # number of overall (read+write) accesses 776system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.464076 # miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099638 # miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_miss_rate::total 0.101043 # miss rate for ReadReq accesses 779system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989081 # miss rate for UpgradeReq accesses 780system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989081 # miss rate for UpgradeReq accesses 781system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268055 # miss rate for ReadExReq accesses 782system.cpu.l2cache.ReadExReq_miss_rate::total 0.268055 # miss rate for ReadExReq accesses 783system.cpu.l2cache.demand_miss_rate::cpu.inst 0.464076 # miss rate for demand accesses 784system.cpu.l2cache.demand_miss_rate::cpu.data 0.150927 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::total 0.151768 # miss rate for demand accesses 786system.cpu.l2cache.overall_miss_rate::cpu.inst 0.464076 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::cpu.data 0.150927 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::total 0.151768 # miss rate for overall accesses 789system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77525.276461 # average ReadReq miss latency 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74917.047039 # average ReadReq miss latency 791system.cpu.l2cache.ReadReq_avg_miss_latency::total 74963.225240 # average ReadReq miss latency 792system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.414314 # average UpgradeReq miss latency 793system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.414314 # average UpgradeReq miss latency 794system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68632.386353 # average ReadExReq miss latency 795system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68632.386353 # average ReadExReq miss latency 796system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77525.276461 # average overall miss latency 797system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71517.820994 # average overall miss latency 798system.cpu.l2cache.demand_avg_miss_latency::total 71567.125894 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77525.276461 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71517.820994 # average overall miss latency 801system.cpu.l2cache.overall_avg_miss_latency::total 71567.125894 # average overall miss latency |
| 628system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 629system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 630system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 632system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 633system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 634system.cpu.l2cache.fast_writes 0 # number of fast writes performed 635system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 802system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 805system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 806system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 807system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 808system.cpu.l2cache.fast_writes 0 # number of fast writes performed 809system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 636system.cpu.l2cache.writebacks::writebacks 293661 # number of writebacks 637system.cpu.l2cache.writebacks::total 293661 # number of writebacks 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3170 # number of ReadReq MSHR misses 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175625 # number of ReadReq MSHR misses 640system.cpu.l2cache.ReadReq_mshr_misses::total 178795 # number of ReadReq MSHR misses 641system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 135999 # number of UpgradeReq MSHR misses 642system.cpu.l2cache.UpgradeReq_mshr_misses::total 135999 # number of UpgradeReq MSHR misses 643system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206937 # number of ReadExReq MSHR misses 644system.cpu.l2cache.ReadExReq_mshr_misses::total 206937 # number of ReadExReq MSHR misses 645system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.demand_mshr_misses::cpu.data 382562 # number of demand (read+write) MSHR misses 647system.cpu.l2cache.demand_mshr_misses::total 385732 # number of demand (read+write) MSHR misses 648system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses 649system.cpu.l2cache.overall_mshr_misses::cpu.data 382562 # number of overall MSHR misses 650system.cpu.l2cache.overall_mshr_misses::total 385732 # number of overall MSHR misses 651system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158250747 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7922707780 # number of ReadReq MSHR miss cycles 653system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8080958527 # number of ReadReq MSHR miss cycles 654system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1364143324 # number of UpgradeReq MSHR miss cycles 655system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1364143324 # number of UpgradeReq MSHR miss cycles 656system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7842004636 # number of ReadExReq MSHR miss cycles 657system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7842004636 # number of ReadExReq MSHR miss cycles 658system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158250747 # number of demand (read+write) MSHR miss cycles 659system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15764712416 # number of demand (read+write) MSHR miss cycles 660system.cpu.l2cache.demand_mshr_miss_latency::total 15922963163 # number of demand (read+write) MSHR miss cycles 661system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158250747 # number of overall MSHR miss cycles 662system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15764712416 # number of overall MSHR miss cycles 663system.cpu.l2cache.overall_mshr_miss_latency::total 15922963163 # number of overall MSHR miss cycles 664system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for ReadReq accesses 665system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099599 # mshr miss rate for ReadReq accesses 666system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100995 # mshr miss rate for ReadReq accesses 667system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989407 # mshr miss rate for UpgradeReq accesses 668system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989407 # mshr miss rate for UpgradeReq accesses 669system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267869 # mshr miss rate for ReadExReq accesses 670system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267869 # mshr miss rate for ReadExReq accesses 671system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for demand accesses 672system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150862 # mshr miss rate for demand accesses 673system.cpu.l2cache.demand_mshr_miss_rate::total 0.151692 # mshr miss rate for demand accesses 674system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for overall accesses 675system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150862 # mshr miss rate for overall accesses 676system.cpu.l2cache.overall_mshr_miss_rate::total 0.151692 # mshr miss rate for overall accesses 677system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49921.371293 # average ReadReq mshr miss latency 678system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45111.503374 # average ReadReq mshr miss latency 679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45196.781381 # average ReadReq mshr miss latency 680system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.539372 # average UpgradeReq mshr miss latency 681system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.539372 # average UpgradeReq mshr miss latency 682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37895.613815 # average ReadExReq mshr miss latency 683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37895.613815 # average ReadExReq mshr miss latency 684system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency 685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency 687system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency | 810system.cpu.l2cache.writebacks::writebacks 293598 # number of writebacks 811system.cpu.l2cache.writebacks::total 293598 # number of writebacks 812system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3165 # number of ReadReq MSHR misses 813system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175600 # number of ReadReq MSHR misses 814system.cpu.l2cache.ReadReq_mshr_misses::total 178765 # number of ReadReq MSHR misses 815system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 132344 # number of UpgradeReq MSHR misses 816system.cpu.l2cache.UpgradeReq_mshr_misses::total 132344 # number of UpgradeReq MSHR misses 817system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206868 # number of ReadExReq MSHR misses 818system.cpu.l2cache.ReadExReq_mshr_misses::total 206868 # number of ReadExReq MSHR misses 819system.cpu.l2cache.demand_mshr_misses::cpu.inst 3165 # number of demand (read+write) MSHR misses 820system.cpu.l2cache.demand_mshr_misses::cpu.data 382468 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.demand_mshr_misses::total 385633 # number of demand (read+write) MSHR misses 822system.cpu.l2cache.overall_mshr_misses::cpu.inst 3165 # number of overall MSHR misses 823system.cpu.l2cache.overall_mshr_misses::cpu.data 382468 # number of overall MSHR misses 824system.cpu.l2cache.overall_mshr_misses::total 385633 # number of overall MSHR misses 825system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 206069250 # number of ReadReq MSHR miss cycles 826system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986131460 # number of ReadReq MSHR miss cycles 827system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11192200710 # number of ReadReq MSHR miss cycles 828system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1327484723 # number of UpgradeReq MSHR miss cycles 829system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1327484723 # number of UpgradeReq MSHR miss cycles 830system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11619637772 # number of ReadExReq MSHR miss cycles 831system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11619637772 # number of ReadExReq MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206069250 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22605769232 # number of demand (read+write) MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::total 22811838482 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206069250 # number of overall MSHR miss cycles 836system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22605769232 # number of overall MSHR miss cycles 837system.cpu.l2cache.overall_mshr_miss_latency::total 22811838482 # number of overall MSHR miss cycles 838system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for ReadReq accesses 839system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099638 # mshr miss rate for ReadReq accesses 840system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101043 # mshr miss rate for ReadReq accesses 841system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989081 # mshr miss rate for UpgradeReq accesses 842system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989081 # mshr miss rate for UpgradeReq accesses 843system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268055 # mshr miss rate for ReadExReq accesses 844system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268055 # mshr miss rate for ReadExReq accesses 845system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for demand accesses 846system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for demand accesses 847system.cpu.l2cache.demand_mshr_miss_rate::total 0.151768 # mshr miss rate for demand accesses 848system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for overall accesses 849system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for overall accesses 850system.cpu.l2cache.overall_mshr_miss_rate::total 0.151768 # mshr miss rate for overall accesses 851system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65108.767773 # average ReadReq mshr miss latency 852system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62563.391002 # average ReadReq mshr miss latency 853system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62608.456409 # average ReadReq mshr miss latency 854system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.562194 # average UpgradeReq mshr miss latency 855system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.562194 # average UpgradeReq mshr miss latency 856system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56169.333933 # average ReadExReq mshr miss latency 857system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56169.333933 # average ReadExReq mshr miss latency 858system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency 859system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency 861system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency 862system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency |
| 690system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 864system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 691system.cpu.dcache.replacements 2531750 # number of replacements 692system.cpu.dcache.tagsinuse 4088.641557 # Cycle average of tags in use 693system.cpu.dcache.total_refs 396440107 # Total number of references to valid blocks. 694system.cpu.dcache.sampled_refs 2535846 # Sample count of references to valid blocks. 695system.cpu.dcache.avg_refs 156.334457 # Average number of references to valid blocks. 696system.cpu.dcache.warmup_cycle 1679431000 # Cycle when the warmup percentage was hit. 697system.cpu.dcache.occ_blocks::cpu.data 4088.641557 # Average occupied blocks per requestor 698system.cpu.dcache.occ_percent::cpu.data 0.998204 # Average percentage of cache occupancy 699system.cpu.dcache.occ_percent::total 0.998204 # Average percentage of cache occupancy 700system.cpu.dcache.ReadReq_hits::cpu.data 247707841 # number of ReadReq hits 701system.cpu.dcache.ReadReq_hits::total 247707841 # number of ReadReq hits 702system.cpu.dcache.WriteReq_hits::cpu.data 148233543 # number of WriteReq hits 703system.cpu.dcache.WriteReq_hits::total 148233543 # number of WriteReq hits 704system.cpu.dcache.demand_hits::cpu.data 395941384 # number of demand (read+write) hits 705system.cpu.dcache.demand_hits::total 395941384 # number of demand (read+write) hits 706system.cpu.dcache.overall_hits::cpu.data 395941384 # number of overall hits 707system.cpu.dcache.overall_hits::total 395941384 # number of overall hits 708system.cpu.dcache.ReadReq_misses::cpu.data 2871315 # number of ReadReq misses 709system.cpu.dcache.ReadReq_misses::total 2871315 # number of ReadReq misses 710system.cpu.dcache.WriteReq_misses::cpu.data 926659 # number of WriteReq misses 711system.cpu.dcache.WriteReq_misses::total 926659 # number of WriteReq misses 712system.cpu.dcache.demand_misses::cpu.data 3797974 # number of demand (read+write) misses 713system.cpu.dcache.demand_misses::total 3797974 # number of demand (read+write) misses 714system.cpu.dcache.overall_misses::cpu.data 3797974 # number of overall misses 715system.cpu.dcache.overall_misses::total 3797974 # number of overall misses 716system.cpu.dcache.ReadReq_miss_latency::cpu.data 51373394500 # number of ReadReq miss cycles 717system.cpu.dcache.ReadReq_miss_latency::total 51373394500 # number of ReadReq miss cycles 718system.cpu.dcache.WriteReq_miss_latency::cpu.data 21994238500 # number of WriteReq miss cycles 719system.cpu.dcache.WriteReq_miss_latency::total 21994238500 # number of WriteReq miss cycles 720system.cpu.dcache.demand_miss_latency::cpu.data 73367633000 # number of demand (read+write) miss cycles 721system.cpu.dcache.demand_miss_latency::total 73367633000 # number of demand (read+write) miss cycles 722system.cpu.dcache.overall_miss_latency::cpu.data 73367633000 # number of overall miss cycles 723system.cpu.dcache.overall_miss_latency::total 73367633000 # number of overall miss cycles 724system.cpu.dcache.ReadReq_accesses::cpu.data 250579156 # number of ReadReq accesses(hits+misses) 725system.cpu.dcache.ReadReq_accesses::total 250579156 # number of ReadReq accesses(hits+misses) | 865system.cpu.dcache.replacements 2530027 # number of replacements 866system.cpu.dcache.tagsinuse 4088.382661 # Cycle average of tags in use 867system.cpu.dcache.total_refs 396086661 # Total number of references to valid blocks. 868system.cpu.dcache.sampled_refs 2534123 # Sample count of references to valid blocks. 869system.cpu.dcache.avg_refs 156.301277 # Average number of references to valid blocks. 870system.cpu.dcache.warmup_cycle 1759751000 # Cycle when the warmup percentage was hit. 871system.cpu.dcache.occ_blocks::cpu.data 4088.382661 # Average occupied blocks per requestor 872system.cpu.dcache.occ_percent::cpu.data 0.998140 # Average percentage of cache occupancy 873system.cpu.dcache.occ_percent::total 0.998140 # Average percentage of cache occupancy 874system.cpu.dcache.ReadReq_hits::cpu.data 247356702 # number of ReadReq hits 875system.cpu.dcache.ReadReq_hits::total 247356702 # number of ReadReq hits 876system.cpu.dcache.WriteReq_hits::cpu.data 148237858 # number of WriteReq hits 877system.cpu.dcache.WriteReq_hits::total 148237858 # number of WriteReq hits 878system.cpu.dcache.demand_hits::cpu.data 395594560 # number of demand (read+write) hits 879system.cpu.dcache.demand_hits::total 395594560 # number of demand (read+write) hits 880system.cpu.dcache.overall_hits::cpu.data 395594560 # number of overall hits 881system.cpu.dcache.overall_hits::total 395594560 # number of overall hits 882system.cpu.dcache.ReadReq_misses::cpu.data 2862804 # number of ReadReq misses 883system.cpu.dcache.ReadReq_misses::total 2862804 # number of ReadReq misses 884system.cpu.dcache.WriteReq_misses::cpu.data 922344 # number of WriteReq misses 885system.cpu.dcache.WriteReq_misses::total 922344 # number of WriteReq misses 886system.cpu.dcache.demand_misses::cpu.data 3785148 # number of demand (read+write) misses 887system.cpu.dcache.demand_misses::total 3785148 # number of demand (read+write) misses 888system.cpu.dcache.overall_misses::cpu.data 3785148 # number of overall misses 889system.cpu.dcache.overall_misses::total 3785148 # number of overall misses 890system.cpu.dcache.ReadReq_miss_latency::cpu.data 57011675000 # number of ReadReq miss cycles 891system.cpu.dcache.ReadReq_miss_latency::total 57011675000 # number of ReadReq miss cycles 892system.cpu.dcache.WriteReq_miss_latency::cpu.data 25670326998 # number of WriteReq miss cycles 893system.cpu.dcache.WriteReq_miss_latency::total 25670326998 # number of WriteReq miss cycles 894system.cpu.dcache.demand_miss_latency::cpu.data 82682001998 # number of demand (read+write) miss cycles 895system.cpu.dcache.demand_miss_latency::total 82682001998 # number of demand (read+write) miss cycles 896system.cpu.dcache.overall_miss_latency::cpu.data 82682001998 # number of overall miss cycles 897system.cpu.dcache.overall_miss_latency::total 82682001998 # number of overall miss cycles 898system.cpu.dcache.ReadReq_accesses::cpu.data 250219506 # number of ReadReq accesses(hits+misses) 899system.cpu.dcache.ReadReq_accesses::total 250219506 # number of ReadReq accesses(hits+misses) |
| 726system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 727system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) | 900system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 901system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) |
| 728system.cpu.dcache.demand_accesses::cpu.data 399739358 # number of demand (read+write) accesses 729system.cpu.dcache.demand_accesses::total 399739358 # number of demand (read+write) accesses 730system.cpu.dcache.overall_accesses::cpu.data 399739358 # number of overall (read+write) accesses 731system.cpu.dcache.overall_accesses::total 399739358 # number of overall (read+write) accesses 732system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011459 # miss rate for ReadReq accesses 733system.cpu.dcache.ReadReq_miss_rate::total 0.011459 # miss rate for ReadReq accesses 734system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006213 # miss rate for WriteReq accesses 735system.cpu.dcache.WriteReq_miss_rate::total 0.006213 # miss rate for WriteReq accesses 736system.cpu.dcache.demand_miss_rate::cpu.data 0.009501 # miss rate for demand accesses 737system.cpu.dcache.demand_miss_rate::total 0.009501 # miss rate for demand accesses 738system.cpu.dcache.overall_miss_rate::cpu.data 0.009501 # miss rate for overall accesses 739system.cpu.dcache.overall_miss_rate::total 0.009501 # miss rate for overall accesses 740system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.939582 # average ReadReq miss latency 741system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.939582 # average ReadReq miss latency 742system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23734.986117 # average WriteReq miss latency 743system.cpu.dcache.WriteReq_avg_miss_latency::total 23734.986117 # average WriteReq miss latency 744system.cpu.dcache.demand_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency 745system.cpu.dcache.demand_avg_miss_latency::total 19317.571158 # average overall miss latency 746system.cpu.dcache.overall_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency 747system.cpu.dcache.overall_avg_miss_latency::total 19317.571158 # average overall miss latency 748system.cpu.dcache.blocked_cycles::no_mshrs 6008 # number of cycles access was blocked | 902system.cpu.dcache.demand_accesses::cpu.data 399379708 # number of demand (read+write) accesses 903system.cpu.dcache.demand_accesses::total 399379708 # number of demand (read+write) accesses 904system.cpu.dcache.overall_accesses::cpu.data 399379708 # number of overall (read+write) accesses 905system.cpu.dcache.overall_accesses::total 399379708 # number of overall (read+write) accesses 906system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011441 # miss rate for ReadReq accesses 907system.cpu.dcache.ReadReq_miss_rate::total 0.011441 # miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006184 # miss rate for WriteReq accesses 909system.cpu.dcache.WriteReq_miss_rate::total 0.006184 # miss rate for WriteReq accesses 910system.cpu.dcache.demand_miss_rate::cpu.data 0.009478 # miss rate for demand accesses 911system.cpu.dcache.demand_miss_rate::total 0.009478 # miss rate for demand accesses 912system.cpu.dcache.overall_miss_rate::cpu.data 0.009478 # miss rate for overall accesses 913system.cpu.dcache.overall_miss_rate::total 0.009478 # miss rate for overall accesses 914system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19914.627407 # average ReadReq miss latency 915system.cpu.dcache.ReadReq_avg_miss_latency::total 19914.627407 # average ReadReq miss latency 916system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27831.619220 # average WriteReq miss latency 917system.cpu.dcache.WriteReq_avg_miss_latency::total 27831.619220 # average WriteReq miss latency 918system.cpu.dcache.demand_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency 919system.cpu.dcache.demand_avg_miss_latency::total 21843.796332 # average overall miss latency 920system.cpu.dcache.overall_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency 921system.cpu.dcache.overall_avg_miss_latency::total 21843.796332 # average overall miss latency 922system.cpu.dcache.blocked_cycles::no_mshrs 6595 # number of cycles access was blocked |
| 749system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 923system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 750system.cpu.dcache.blocked::no_mshrs 680 # number of cycles access was blocked | 924system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked |
| 751system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 925system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 752system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.835294 # average number of cycles each access was blocked | 926system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.828614 # average number of cycles each access was blocked |
| 753system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 754system.cpu.dcache.fast_writes 0 # number of fast writes performed 755system.cpu.dcache.cache_copies 0 # number of cache copies performed | 927system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 928system.cpu.dcache.fast_writes 0 # number of fast writes performed 929system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 756system.cpu.dcache.writebacks::writebacks 2331818 # number of writebacks 757system.cpu.dcache.writebacks::total 2331818 # number of writebacks 758system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1107712 # number of ReadReq MSHR hits 759system.cpu.dcache.ReadReq_mshr_hits::total 1107712 # number of ReadReq MSHR hits 760system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16962 # number of WriteReq MSHR hits 761system.cpu.dcache.WriteReq_mshr_hits::total 16962 # number of WriteReq MSHR hits 762system.cpu.dcache.demand_mshr_hits::cpu.data 1124674 # number of demand (read+write) MSHR hits 763system.cpu.dcache.demand_mshr_hits::total 1124674 # number of demand (read+write) MSHR hits 764system.cpu.dcache.overall_mshr_hits::cpu.data 1124674 # number of overall MSHR hits 765system.cpu.dcache.overall_mshr_hits::total 1124674 # number of overall MSHR hits 766system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763603 # number of ReadReq MSHR misses 767system.cpu.dcache.ReadReq_mshr_misses::total 1763603 # number of ReadReq MSHR misses 768system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909697 # number of WriteReq MSHR misses 769system.cpu.dcache.WriteReq_mshr_misses::total 909697 # number of WriteReq MSHR misses 770system.cpu.dcache.demand_mshr_misses::cpu.data 2673300 # number of demand (read+write) MSHR misses 771system.cpu.dcache.demand_mshr_misses::total 2673300 # number of demand (read+write) MSHR misses 772system.cpu.dcache.overall_mshr_misses::cpu.data 2673300 # number of overall MSHR misses 773system.cpu.dcache.overall_mshr_misses::total 2673300 # number of overall MSHR misses 774system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27774523500 # number of ReadReq MSHR miss cycles 775system.cpu.dcache.ReadReq_mshr_miss_latency::total 27774523500 # number of ReadReq MSHR miss cycles 776system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972622500 # number of WriteReq MSHR miss cycles 777system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972622500 # number of WriteReq MSHR miss cycles 778system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47747146000 # number of demand (read+write) MSHR miss cycles 779system.cpu.dcache.demand_mshr_miss_latency::total 47747146000 # number of demand (read+write) MSHR miss cycles 780system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47747146000 # number of overall MSHR miss cycles 781system.cpu.dcache.overall_mshr_miss_latency::total 47747146000 # number of overall MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007038 # mshr miss rate for ReadReq accesses 783system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007038 # mshr miss rate for ReadReq accesses 784system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses 785system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses 786system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for demand accesses 787system.cpu.dcache.demand_mshr_miss_rate::total 0.006688 # mshr miss rate for demand accesses 788system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for overall accesses 789system.cpu.dcache.overall_mshr_miss_rate::total 0.006688 # mshr miss rate for overall accesses 790system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15748.739087 # average ReadReq mshr miss latency 791system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15748.739087 # average ReadReq mshr miss latency 792system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21955.247187 # average WriteReq mshr miss latency 793system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21955.247187 # average WriteReq mshr miss latency 794system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency 795system.cpu.dcache.demand_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency 796system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency 797system.cpu.dcache.overall_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency | 930system.cpu.dcache.writebacks::writebacks 2330801 # number of writebacks 931system.cpu.dcache.writebacks::total 2330801 # number of writebacks 932system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100153 # number of ReadReq MSHR hits 933system.cpu.dcache.ReadReq_mshr_hits::total 1100153 # number of ReadReq MSHR hits 934system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17067 # number of WriteReq MSHR hits 935system.cpu.dcache.WriteReq_mshr_hits::total 17067 # number of WriteReq MSHR hits 936system.cpu.dcache.demand_mshr_hits::cpu.data 1117220 # number of demand (read+write) MSHR hits 937system.cpu.dcache.demand_mshr_hits::total 1117220 # number of demand (read+write) MSHR hits 938system.cpu.dcache.overall_mshr_hits::cpu.data 1117220 # number of overall MSHR hits 939system.cpu.dcache.overall_mshr_hits::total 1117220 # number of overall MSHR hits 940system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762651 # number of ReadReq MSHR misses 941system.cpu.dcache.ReadReq_mshr_misses::total 1762651 # number of ReadReq MSHR misses 942system.cpu.dcache.WriteReq_mshr_misses::cpu.data 905277 # number of WriteReq MSHR misses 943system.cpu.dcache.WriteReq_mshr_misses::total 905277 # number of WriteReq MSHR misses 944system.cpu.dcache.demand_mshr_misses::cpu.data 2667928 # number of demand (read+write) MSHR misses 945system.cpu.dcache.demand_mshr_misses::total 2667928 # number of demand (read+write) MSHR misses 946system.cpu.dcache.overall_mshr_misses::cpu.data 2667928 # number of overall MSHR misses 947system.cpu.dcache.overall_mshr_misses::total 2667928 # number of overall MSHR misses 948system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30822255503 # number of ReadReq MSHR miss cycles 949system.cpu.dcache.ReadReq_mshr_miss_latency::total 30822255503 # number of ReadReq MSHR miss cycles 950system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23648350501 # number of WriteReq MSHR miss cycles 951system.cpu.dcache.WriteReq_mshr_miss_latency::total 23648350501 # number of WriteReq MSHR miss cycles 952system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54470606004 # number of demand (read+write) MSHR miss cycles 953system.cpu.dcache.demand_mshr_miss_latency::total 54470606004 # number of demand (read+write) MSHR miss cycles 954system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54470606004 # number of overall MSHR miss cycles 955system.cpu.dcache.overall_mshr_miss_latency::total 54470606004 # number of overall MSHR miss cycles 956system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses 957system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses 958system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006069 # mshr miss rate for WriteReq accesses 959system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006069 # mshr miss rate for WriteReq accesses 960system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for demand accesses 961system.cpu.dcache.demand_mshr_miss_rate::total 0.006680 # mshr miss rate for demand accesses 962system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for overall accesses 963system.cpu.dcache.overall_mshr_miss_rate::total 0.006680 # mshr miss rate for overall accesses 964system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17486.306423 # average ReadReq mshr miss latency 965system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17486.306423 # average ReadReq mshr miss latency 966system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26122.778444 # average WriteReq mshr miss latency 967system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26122.778444 # average WriteReq mshr miss latency 968system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency 969system.cpu.dcache.demand_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency 970system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency 971system.cpu.dcache.overall_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency |
| 798system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 799 800---------- End Simulation Statistics ---------- | 972system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 973 974---------- End Simulation Statistics ---------- |