Cross Reference: /gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.434516 # Number of seconds simulated
4sim_ticks 434516346000 # Number of ticks simulated
5final_tick 434516346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.434544 # Number of seconds simulated
4sim_ticks 434543595000 # Number of ticks simulated
5final_tick 434543595000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 41156 # Simulator instruction rate (inst/s)
8host_op_rate 76102 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 21627180 # Simulator tick rate (ticks/s)
10host_mem_usage 403680 # Number of bytes of host memory used
11host_seconds 20091.22 # Real time elapsed on the host

7host_inst_rate 65471 # Simulator instruction rate (inst/s)
8host_op_rate 121063 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 34406418 # Simulator tick rate (ticks/s)
10host_mem_usage 403752 # Number of bytes of host memory used
11host_seconds 12629.72 # Real time elapsed on the host

12sim_insts 826877109 # Number of instructions simulated
13sim_ops 1528988701 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 207552 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 24467712 # Number of bytes read from this memory
16system.physmem.bytes_read::total 24675264 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 207552 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 207552 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 18791168 # Number of bytes written to this memory
20system.physmem.bytes_written::total 18791168 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3243 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 382308 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 385551 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 293612 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 293612 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 477662 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 56310222 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 56787884 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 477662 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 477662 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 43246171 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 43246171 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 43246171 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 477662 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 56310222 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 100034055 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 385553 # Total number of read requests seen
38system.physmem.writeReqs 293612 # Total number of write requests seen
39system.physmem.cpureqs 889187 # Reqs generatd by CPU via cache - shady
40system.physmem.bytesRead 24675264 # Total number of bytes read from memory
41system.physmem.bytesWritten 18791168 # Total number of bytes written to memory
42system.physmem.bytesConsumedRd 24675264 # bytesRead derated as per pkt->getSize()
43system.physmem.bytesConsumedWr 18791168 # bytesWritten derated as per pkt->getSize()
44system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 209992 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 23303 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 24507 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 23750 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::3 22586 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::4 23590 # Track reads on a per bank basis

14system.physmem.bytes_read::cpu.inst 207168 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 24469184 # Number of bytes read from this memory
16system.physmem.bytes_read::total 24676352 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 207168 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 207168 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 18791424 # Number of bytes written to this memory
20system.physmem.bytes_written::total 18791424 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3237 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 382331 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 385568 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 293616 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 293616 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 476748 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 56310079 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 56786827 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 476748 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 476748 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 43244048 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 43244048 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 43244048 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 476748 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 56310079 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 100030875 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 385570 # Total number of read requests seen
38system.physmem.writeReqs 293616 # Total number of write requests seen
39system.physmem.cpureqs 889416 # Reqs generatd by CPU via cache - shady
40system.physmem.bytesRead 24676352 # Total number of bytes read from memory
41system.physmem.bytesWritten 18791424 # Total number of bytes written to memory
42system.physmem.bytesConsumedRd 24676352 # bytesRead derated as per pkt->getSize()
43system.physmem.bytesConsumedWr 18791424 # bytesWritten derated as per pkt->getSize()
44system.physmem.servicedByWrQ 147 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 210200 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 23300 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 24510 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 23756 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::3 22591 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::4 23592 # Track reads on a per bank basis

51system.physmem.perBankRdReqs::5 24765 # Track reads on a per bank basis

52system.physmem.perBankRdReqs::6 24370 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::7 24220 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::8 24533 # Track reads on a per bank basis

52system.physmem.perBankRdReqs::6 24384 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::7 24225 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::8 24541 # Track reads on a per bank basis

55system.physmem.perBankRdReqs::9 24693 # Track reads on a per bank basis

56system.physmem.perBankRdReqs::10 24138 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 24300 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::12 24598 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::13 23473 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 24673 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 23908 # Track reads on a per bank basis
62system.physmem.perBankWrReqs::0 17801 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::1 18813 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::2 18266 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::3 17554 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::4 18027 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::5 18651 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::6 18325 # Track writes on a per bank basis

56system.physmem.perBankRdReqs::10 24144 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 24284 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::12 24592 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::13 23476 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 24665 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 23905 # Track reads on a per bank basis
62system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::1 18814 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::2 18269 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::3 17556 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::5 18647 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::6 18328 # Track writes on a per bank basis

69system.physmem.perBankWrReqs::7 18330 # Track writes on a per bank basis

70system.physmem.perBankWrReqs::8 18772 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::9 18767 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::10 18400 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::11 18544 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::12 18575 # Track writes on a per bank basis

70system.physmem.perBankWrReqs::8 18773 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::9 18765 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::10 18401 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::11 18543 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::12 18573 # Track writes on a per bank basis

75system.physmem.perBankWrReqs::13 17879 # Track writes on a per bank basis

76system.physmem.perBankWrReqs::14 18803 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::15 18105 # Track writes on a per bank basis

76system.physmem.perBankWrReqs::14 18800 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::15 18107 # Track writes on a per bank basis

78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry

80system.physmem.totGap 434516329000 # Total gap between requests

80system.physmem.totGap 434543578000 # Total gap between requests

81system.physmem.readPktSize::0 0 # Categorize read packet sizes
82system.physmem.readPktSize::1 0 # Categorize read packet sizes
83system.physmem.readPktSize::2 0 # Categorize read packet sizes
84system.physmem.readPktSize::3 0 # Categorize read packet sizes
85system.physmem.readPktSize::4 0 # Categorize read packet sizes
86system.physmem.readPktSize::5 0 # Categorize read packet sizes

87system.physmem.readPktSize::6 385553 # Categorize read packet sizes

87system.physmem.readPktSize::6 385570 # Categorize read packet sizes

88system.physmem.writePktSize::0 0 # Categorize write packet sizes
89system.physmem.writePktSize::1 0 # Categorize write packet sizes
90system.physmem.writePktSize::2 0 # Categorize write packet sizes
91system.physmem.writePktSize::3 0 # Categorize write packet sizes
92system.physmem.writePktSize::4 0 # Categorize write packet sizes
93system.physmem.writePktSize::5 0 # Categorize write packet sizes

94system.physmem.writePktSize::6 293612 # Categorize write packet sizes
95system.physmem.rdQLenPdf::0 380638 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::1 4317 # What read queue length does an incoming req see

94system.physmem.writePktSize::6 293616 # Categorize write packet sizes
95system.physmem.rdQLenPdf::0 380658 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::1 4312 # What read queue length does an incoming req see

97system.physmem.rdQLenPdf::2 385 # What read queue length does an incoming req see

98system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see

98system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see

101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see

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119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see

127system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see

127system.physmem.wrQLenPdf::0 12705 # What write queue length does an incoming req see

128system.physmem.wrQLenPdf::1 12716 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::2 12716 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::3 12716 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::4 12720 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::5 12725 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::6 12730 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::8 12735 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see

144system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see

144system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see

148system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see

150system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see

150system.physmem.wrQLenPdf::23 61 # What write queue length does an incoming req see

151system.physmem.wrQLenPdf::24 50 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::25 50 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::31 31 # What write queue length does an incoming req see

159system.physmem.totQLat 3419098500 # Total cycles spent in queuing delays
160system.physmem.totMemAccLat 12003058500 # Sum of mem lat for all requests
161system.physmem.totBusLat 1927035000 # Total cycles spent in databus access
162system.physmem.totBankLat 6656925000 # Total cycles spent in bank access
163system.physmem.avgQLat 8871.40 # Average queueing delay per request
164system.physmem.avgBankLat 17272.45 # Average bank access latency per request

159system.physmem.totQLat 3416691250 # Total cycles spent in queuing delays
160system.physmem.totMemAccLat 12001501250 # Sum of mem lat for all requests
161system.physmem.totBusLat 1927115000 # Total cycles spent in databus access
162system.physmem.totBankLat 6657695000 # Total cycles spent in bank access
163system.physmem.avgQLat 8864.78 # Average queueing delay per request
164system.physmem.avgBankLat 17273.74 # Average bank access latency per request

165system.physmem.avgBusLat 5000.00 # Average bus latency per request

166system.physmem.avgMemAccLat 31143.85 # Average memory access latency

166system.physmem.avgMemAccLat 31138.52 # Average memory access latency

167system.physmem.avgRdBW 56.79 # Average achieved read bandwidth in MB/s

168system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s

168system.physmem.avgWrBW 43.24 # Average achieved write bandwidth in MB/s

169system.physmem.avgConsumedRdBW 56.79 # Average consumed read bandwidth in MB/s

170system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s

170system.physmem.avgConsumedWrBW 43.24 # Average consumed write bandwidth in MB/s

171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
172system.physmem.busUtil 0.78 # Data bus utilization in percentage
173system.physmem.avgRdQLen 0.03 # Average read queue length over time

174system.physmem.avgWrQLen 9.12 # Average write queue length over time
175system.physmem.readRowHits 331790 # Number of row buffer hits during reads
176system.physmem.writeRowHits 191871 # Number of row buffer hits during writes

174system.physmem.avgWrQLen 9.11 # Average write queue length over time
175system.physmem.readRowHits 331804 # Number of row buffer hits during reads
176system.physmem.writeRowHits 191849 # Number of row buffer hits during writes

177system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads

178system.physmem.writeRowHitRate 65.35 # Row buffer hit rate for writes
179system.physmem.avgGap 639780.21 # Average gap between requests
180system.cpu.branchPred.lookups 214953506 # Number of BP lookups
181system.cpu.branchPred.condPredicted 214953506 # Number of conditional branches predicted
182system.cpu.branchPred.condIncorrect 13134677 # Number of conditional branches incorrect
183system.cpu.branchPred.BTBLookups 150549169 # Number of BTB lookups
184system.cpu.branchPred.BTBHits 147861057 # Number of BTB hits

178system.physmem.writeRowHitRate 65.34 # Row buffer hit rate for writes
179system.physmem.avgGap 639800.55 # Average gap between requests
180system.cpu.branchPred.lookups 214941297 # Number of BP lookups
181system.cpu.branchPred.condPredicted 214941297 # Number of conditional branches predicted
182system.cpu.branchPred.condIncorrect 13134170 # Number of conditional branches incorrect
183system.cpu.branchPred.BTBLookups 150507127 # Number of BTB lookups
184system.cpu.branchPred.BTBHits 147849168 # Number of BTB hits

185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

186system.cpu.branchPred.BTBHitPct 98.214462 # BTB Hit Percentage

186system.cpu.branchPred.BTBHitPct 98.233998 # BTB Hit Percentage

187system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
188system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
189system.cpu.workload.num_syscalls 551 # Number of system calls

190system.cpu.numCycles 869032693 # number of cpu cycles simulated

190system.cpu.numCycles 869087191 # number of cpu cycles simulated

191system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
192system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

193system.cpu.fetch.icacheStallCycles 180543347 # Number of cycles fetch is stalled on an Icache miss
194system.cpu.fetch.Insts 1193643366 # Number of instructions fetch has processed
195system.cpu.fetch.Branches 214953506 # Number of branches that fetch encountered
196system.cpu.fetch.predictedBranches 147861057 # Number of branches that fetch has predicted taken
197system.cpu.fetch.Cycles 371295648 # Number of cycles fetch has run and was not squashing or blocked
198system.cpu.fetch.SquashCycles 83421023 # Number of cycles fetch has spent squashing
199system.cpu.fetch.BlockedCycles 231519953 # Number of cycles fetch has spent blocked
200system.cpu.fetch.MiscStallCycles 32147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
201system.cpu.fetch.PendingTrapStallCycles 318682 # Number of stall cycles due to pending traps
202system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR
203system.cpu.fetch.CacheLines 173452328 # Number of cache lines fetched
204system.cpu.fetch.IcacheSquashes 3838970 # Number of outstanding Icache misses that were squashed
205system.cpu.fetch.rateDist::samples 853739491 # Number of instructions fetched each cycle (Total)
206system.cpu.fetch.rateDist::mean 2.595744 # Number of instructions fetched each cycle (Total)
207system.cpu.fetch.rateDist::stdev 3.389493 # Number of instructions fetched each cycle (Total)

193system.cpu.fetch.icacheStallCycles 180529479 # Number of cycles fetch is stalled on an Icache miss
194system.cpu.fetch.Insts 1193576474 # Number of instructions fetch has processed
195system.cpu.fetch.Branches 214941297 # Number of branches that fetch encountered
196system.cpu.fetch.predictedBranches 147849168 # Number of branches that fetch has predicted taken
197system.cpu.fetch.Cycles 371266839 # Number of cycles fetch has run and was not squashing or blocked
198system.cpu.fetch.SquashCycles 83403229 # Number of cycles fetch has spent squashing
199system.cpu.fetch.BlockedCycles 231605654 # Number of cycles fetch has spent blocked
200system.cpu.fetch.MiscStallCycles 31859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
201system.cpu.fetch.PendingTrapStallCycles 315081 # Number of stall cycles due to pending traps
202system.cpu.fetch.IcacheWaitRetryStallCycles 80 # Number of stall cycles due to full MSHR
203system.cpu.fetch.CacheLines 173437780 # Number of cache lines fetched
204system.cpu.fetch.IcacheSquashes 3837204 # Number of outstanding Icache misses that were squashed
205system.cpu.fetch.rateDist::samples 853761597 # Number of instructions fetched each cycle (Total)
206system.cpu.fetch.rateDist::mean 2.595537 # Number of instructions fetched each cycle (Total)
207system.cpu.fetch.rateDist::stdev 3.389460 # Number of instructions fetched each cycle (Total)

208system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

209system.cpu.fetch.rateDist::0 486849125 57.03% 57.03% # Number of instructions fetched each cycle (Total)
210system.cpu.fetch.rateDist::1 24709977 2.89% 59.92% # Number of instructions fetched each cycle (Total)
211system.cpu.fetch.rateDist::2 27353576 3.20% 63.12% # Number of instructions fetched each cycle (Total)
212system.cpu.fetch.rateDist::3 28812018 3.37% 66.50% # Number of instructions fetched each cycle (Total)
213system.cpu.fetch.rateDist::4 18473026 2.16% 68.66% # Number of instructions fetched each cycle (Total)
214system.cpu.fetch.rateDist::5 24594053 2.88% 71.54% # Number of instructions fetched each cycle (Total)
215system.cpu.fetch.rateDist::6 30667708 3.59% 75.14% # Number of instructions fetched each cycle (Total)
216system.cpu.fetch.rateDist::7 28872353 3.38% 78.52% # Number of instructions fetched each cycle (Total)
217system.cpu.fetch.rateDist::8 183407655 21.48% 100.00% # Number of instructions fetched each cycle (Total)

209system.cpu.fetch.rateDist::0 486899007 57.03% 57.03% # Number of instructions fetched each cycle (Total)
210system.cpu.fetch.rateDist::1 24703220 2.89% 59.92% # Number of instructions fetched each cycle (Total)
211system.cpu.fetch.rateDist::2 27351293 3.20% 63.13% # Number of instructions fetched each cycle (Total)
212system.cpu.fetch.rateDist::3 28808692 3.37% 66.50% # Number of instructions fetched each cycle (Total)
213system.cpu.fetch.rateDist::4 18472602 2.16% 68.66% # Number of instructions fetched each cycle (Total)
214system.cpu.fetch.rateDist::5 24587756 2.88% 71.54% # Number of instructions fetched each cycle (Total)
215system.cpu.fetch.rateDist::6 30665646 3.59% 75.14% # Number of instructions fetched each cycle (Total)
216system.cpu.fetch.rateDist::7 28871909 3.38% 78.52% # Number of instructions fetched each cycle (Total)
217system.cpu.fetch.rateDist::8 183401472 21.48% 100.00% # Number of instructions fetched each cycle (Total)

218system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
219system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
220system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

221system.cpu.fetch.rateDist::total 853739491 # Number of instructions fetched each cycle (Total)
222system.cpu.fetch.branchRate 0.247348 # Number of branch fetches per cycle
223system.cpu.fetch.rate 1.373531 # Number of inst fetches per cycle
224system.cpu.decode.IdleCycles 237039901 # Number of cycles decode is idle
225system.cpu.decode.BlockedCycles 188071412 # Number of cycles decode is blocked
226system.cpu.decode.RunCycles 313434986 # Number of cycles decode is running
227system.cpu.decode.UnblockCycles 45163547 # Number of cycles decode is unblocking
228system.cpu.decode.SquashCycles 70029645 # Number of cycles decode is squashing
229system.cpu.decode.DecodedInsts 2166977882 # Number of instructions handled by decode
230system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
231system.cpu.rename.SquashCycles 70029645 # Number of cycles rename is squashing
232system.cpu.rename.IdleCycles 270401805 # Number of cycles rename is idle
233system.cpu.rename.BlockCycles 53948111 # Number of cycles rename is blocking
234system.cpu.rename.serializeStallCycles 16882 # count of cycles rename stalled for serializing inst
235system.cpu.rename.RunCycles 322744473 # Number of cycles rename is running
236system.cpu.rename.UnblockCycles 136598575 # Number of cycles rename is unblocking
237system.cpu.rename.RenamedInsts 2120230208 # Number of instructions processed by rename
238system.cpu.rename.ROBFullEvents 31449 # Number of times rename has blocked due to ROB full
239system.cpu.rename.IQFullEvents 21240578 # Number of times rename has blocked due to IQ full
240system.cpu.rename.LSQFullEvents 101108934 # Number of times rename has blocked due to LSQ full
241system.cpu.rename.FullRegisterEvents 75 # Number of times there has been no free registers
242system.cpu.rename.RenamedOperands 2216675851 # Number of destination operands rename has renamed
243system.cpu.rename.RenameLookups 5356592687 # Number of register rename lookups that rename has made
244system.cpu.rename.int_rename_lookups 5356461793 # Number of integer rename lookups
245system.cpu.rename.fp_rename_lookups 130894 # Number of floating rename lookups

221system.cpu.fetch.rateDist::total 853761597 # Number of instructions fetched each cycle (Total)
222system.cpu.fetch.branchRate 0.247318 # Number of branch fetches per cycle
223system.cpu.fetch.rate 1.373368 # Number of inst fetches per cycle
224system.cpu.decode.IdleCycles 236998203 # Number of cycles decode is idle
225system.cpu.decode.BlockedCycles 188180276 # Number of cycles decode is blocked
226system.cpu.decode.RunCycles 313422880 # Number of cycles decode is running
227system.cpu.decode.UnblockCycles 45147633 # Number of cycles decode is unblocking
228system.cpu.decode.SquashCycles 70012605 # Number of cycles decode is squashing
229system.cpu.decode.DecodedInsts 2166855434 # Number of instructions handled by decode
230system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
231system.cpu.rename.SquashCycles 70012605 # Number of cycles rename is squashing
232system.cpu.rename.IdleCycles 270389606 # Number of cycles rename is idle
233system.cpu.rename.BlockCycles 53986414 # Number of cycles rename is blocking
234system.cpu.rename.serializeStallCycles 16429 # count of cycles rename stalled for serializing inst
235system.cpu.rename.RunCycles 322684460 # Number of cycles rename is running
236system.cpu.rename.UnblockCycles 136672083 # Number of cycles rename is unblocking
237system.cpu.rename.RenamedInsts 2120106693 # Number of instructions processed by rename
238system.cpu.rename.ROBFullEvents 31519 # Number of times rename has blocked due to ROB full
239system.cpu.rename.IQFullEvents 21337249 # Number of times rename has blocked due to IQ full
240system.cpu.rename.LSQFullEvents 101081597 # Number of times rename has blocked due to LSQ full
241system.cpu.rename.FullRegisterEvents 78 # Number of times there has been no free registers
242system.cpu.rename.RenamedOperands 2216557030 # Number of destination operands rename has renamed
243system.cpu.rename.RenameLookups 5356293513 # Number of register rename lookups that rename has made
244system.cpu.rename.int_rename_lookups 5356152135 # Number of integer rename lookups
245system.cpu.rename.fp_rename_lookups 141378 # Number of floating rename lookups

246system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed

247system.cpu.rename.UndoneMaps 602634997 # Number of HB maps that are undone due to squashing
248system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed
249system.cpu.rename.tempSerializingInsts 1357 # count of temporary serializing insts renamed
250system.cpu.rename.skidInsts 330209766 # count of insts added to the skid buffer
251system.cpu.memDep0.insertedLoads 512741559 # Number of loads inserted to the mem dependence unit.
252system.cpu.memDep0.insertedStores 204921816 # Number of stores inserted to the mem dependence unit.
253system.cpu.memDep0.conflictingLoads 196294424 # Number of conflicting loads.
254system.cpu.memDep0.conflictingStores 55462952 # Number of conflicting stores.
255system.cpu.iq.iqInstsAdded 2034039963 # Number of instructions added to the IQ (excludes non-spec)
256system.cpu.iq.iqNonSpecInstsAdded 22861 # Number of non-speculative instructions added to the IQ
257system.cpu.iq.iqInstsIssued 1808186247 # Number of instructions issued
258system.cpu.iq.iqSquashedInstsIssued 841927 # Number of squashed instructions issued
259system.cpu.iq.iqSquashedInstsExamined 499552997 # Number of squashed instructions iterated over during squash; mainly for profiling
260system.cpu.iq.iqSquashedOperandsExamined 818679497 # Number of squashed operands that are examined and possibly removed from graph
261system.cpu.iq.iqSquashedNonSpecRemoved 22309 # Number of squashed non-spec instructions that were removed
262system.cpu.iq.issued_per_cycle::samples 853739491 # Number of insts issued each cycle
263system.cpu.iq.issued_per_cycle::mean 2.117960 # Number of insts issued each cycle
264system.cpu.iq.issued_per_cycle::stdev 1.887291 # Number of insts issued each cycle

247system.cpu.rename.UndoneMaps 602516176 # Number of HB maps that are undone due to squashing
248system.cpu.rename.serializingInsts 1382 # count of serializing insts renamed
249system.cpu.rename.tempSerializingInsts 1352 # count of temporary serializing insts renamed
250system.cpu.rename.skidInsts 330488922 # count of insts added to the skid buffer
251system.cpu.memDep0.insertedLoads 512705517 # Number of loads inserted to the mem dependence unit.
252system.cpu.memDep0.insertedStores 204907925 # Number of stores inserted to the mem dependence unit.
253system.cpu.memDep0.conflictingLoads 196340700 # Number of conflicting loads.
254system.cpu.memDep0.conflictingStores 55518293 # Number of conflicting stores.
255system.cpu.iq.iqInstsAdded 2033906543 # Number of instructions added to the IQ (excludes non-spec)
256system.cpu.iq.iqNonSpecInstsAdded 22903 # Number of non-speculative instructions added to the IQ
257system.cpu.iq.iqInstsIssued 1808080301 # Number of instructions issued
258system.cpu.iq.iqSquashedInstsIssued 844129 # Number of squashed instructions issued
259system.cpu.iq.iqSquashedInstsExamined 499423460 # Number of squashed instructions iterated over during squash; mainly for profiling
260system.cpu.iq.iqSquashedOperandsExamined 818593930 # Number of squashed operands that are examined and possibly removed from graph
261system.cpu.iq.iqSquashedNonSpecRemoved 22351 # Number of squashed non-spec instructions that were removed
262system.cpu.iq.issued_per_cycle::samples 853761597 # Number of insts issued each cycle
263system.cpu.iq.issued_per_cycle::mean 2.117781 # Number of insts issued each cycle
264system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle

265system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

266system.cpu.iq.issued_per_cycle::0 233388219 27.34% 27.34% # Number of insts issued each cycle
267system.cpu.iq.issued_per_cycle::1 145263278 17.01% 44.35% # Number of insts issued each cycle
268system.cpu.iq.issued_per_cycle::2 138308175 16.20% 60.55% # Number of insts issued each cycle
269system.cpu.iq.issued_per_cycle::3 133084460 15.59% 76.14% # Number of insts issued each cycle
270system.cpu.iq.issued_per_cycle::4 96060946 11.25% 87.39% # Number of insts issued each cycle
271system.cpu.iq.issued_per_cycle::5 58814461 6.89% 94.28% # Number of insts issued each cycle
272system.cpu.iq.issued_per_cycle::6 34920030 4.09% 98.37% # Number of insts issued each cycle
273system.cpu.iq.issued_per_cycle::7 11982406 1.40% 99.78% # Number of insts issued each cycle
274system.cpu.iq.issued_per_cycle::8 1917516 0.22% 100.00% # Number of insts issued each cycle

266system.cpu.iq.issued_per_cycle::0 233333722 27.33% 27.33% # Number of insts issued each cycle
267system.cpu.iq.issued_per_cycle::1 145354336 17.03% 44.36% # Number of insts issued each cycle
268system.cpu.iq.issued_per_cycle::2 138354387 16.21% 60.56% # Number of insts issued each cycle
269system.cpu.iq.issued_per_cycle::3 133038603 15.58% 76.14% # Number of insts issued each cycle
270system.cpu.iq.issued_per_cycle::4 96103978 11.26% 87.40% # Number of insts issued each cycle
271system.cpu.iq.issued_per_cycle::5 58771252 6.88% 94.28% # Number of insts issued each cycle
272system.cpu.iq.issued_per_cycle::6 34916322 4.09% 98.37% # Number of insts issued each cycle
273system.cpu.iq.issued_per_cycle::7 11980698 1.40% 99.78% # Number of insts issued each cycle
274system.cpu.iq.issued_per_cycle::8 1908299 0.22% 100.00% # Number of insts issued each cycle

275system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
276system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
277system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

278system.cpu.iq.issued_per_cycle::total 853739491 # Number of insts issued each cycle

278system.cpu.iq.issued_per_cycle::total 853761597 # Number of insts issued each cycle

279system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

280system.cpu.iq.fu_full::IntAlu 4979468 32.47% 32.47% # attempts to use FU when none available
281system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available
282system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available
283system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available
284system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available
285system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available
286system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available
287system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available
288system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
289system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available
290system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available
291system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available
292system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available
293system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available
294system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available
295system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available
296system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available
297system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available
298system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available
299system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available
300system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available
301system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available
302system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available
303system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available
304system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available
305system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available
306system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available
307system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available
308system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
309system.cpu.iq.fu_full::MemRead 7769551 50.66% 83.13% # attempts to use FU when none available
310system.cpu.iq.fu_full::MemWrite 2586637 16.87% 100.00% # attempts to use FU when none available

280system.cpu.iq.fu_full::IntAlu 4978338 32.41% 32.41% # attempts to use FU when none available
281system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available
282system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available
283system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available
284system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available
285system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available
286system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available
287system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available
288system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available
289system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available
290system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available
291system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available
292system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available
293system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available
294system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available
295system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available
296system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available
297system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available
298system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available
299system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available
300system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available
301system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available
302system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available
303system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available
304system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available
305system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available
306system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available
307system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available
308system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available
309system.cpu.iq.fu_full::MemRead 7792932 50.73% 83.13% # attempts to use FU when none available
310system.cpu.iq.fu_full::MemWrite 2590948 16.87% 100.00% # attempts to use FU when none available

311system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
312system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

313system.cpu.iq.FU_type_0::No_OpClass 2717049 0.15% 0.15% # Type of FU issued
314system.cpu.iq.FU_type_0::IntAlu 1190849468 65.86% 66.01% # Type of FU issued

313system.cpu.iq.FU_type_0::No_OpClass 2717915 0.15% 0.15% # Type of FU issued
314system.cpu.iq.FU_type_0::IntAlu 1190782663 65.86% 66.01% # Type of FU issued

315system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued
316system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued
317system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued
318system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued
319system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued
320system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued
321system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued
322system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued

--- 12 unchanged lines hidden (view full) ---

335system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
336system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
337system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
338system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
339system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
340system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
341system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
342system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued

343system.cpu.iq.FU_type_0::MemRead 438947652 24.28% 90.28% # Type of FU issued
344system.cpu.iq.FU_type_0::MemWrite 175672078 9.72% 100.00% # Type of FU issued

343system.cpu.iq.FU_type_0::MemRead 438926011 24.28% 90.29% # Type of FU issued
344system.cpu.iq.FU_type_0::MemWrite 175653712 9.71% 100.00% # Type of FU issued

345system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
346system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

347system.cpu.iq.FU_type_0::total 1808186247 # Type of FU issued
348system.cpu.iq.rate 2.080688 # Inst issue rate
349system.cpu.iq.fu_busy_cnt 15335656 # FU busy when requested
350system.cpu.iq.fu_busy_rate 0.008481 # FU busy rate (busy events/executed inst)
351system.cpu.iq.int_inst_queue_reads 4486267345 # Number of integer instruction queue reads
352system.cpu.iq.int_inst_queue_writes 2533832707 # Number of integer instruction queue writes
353system.cpu.iq.int_inst_queue_wakeup_accesses 1768692964 # Number of integer instruction queue wakeup accesses
354system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads
355system.cpu.iq.fp_inst_queue_writes 41984 # Number of floating instruction queue writes
356system.cpu.iq.fp_inst_queue_wakeup_accesses 4908 # Number of floating instruction queue wakeup accesses
357system.cpu.iq.int_alu_accesses 1820794592 # Number of integer alu accesses
358system.cpu.iq.fp_alu_accesses 10262 # Number of floating point alu accesses
359system.cpu.iew.lsq.thread0.forwLoads 170635682 # Number of loads that had data forwarded from stores

347system.cpu.iq.FU_type_0::total 1808080301 # Type of FU issued
348system.cpu.iq.rate 2.080436 # Inst issue rate
349system.cpu.iq.fu_busy_cnt 15362218 # FU busy when requested
350system.cpu.iq.fu_busy_rate 0.008496 # FU busy rate (busy events/executed inst)
351system.cpu.iq.int_inst_queue_reads 4486103997 # Number of integer instruction queue reads
352system.cpu.iq.int_inst_queue_writes 2533565590 # Number of integer instruction queue writes
353system.cpu.iq.int_inst_queue_wakeup_accesses 1768588128 # Number of integer instruction queue wakeup accesses
354system.cpu.iq.fp_inst_queue_reads 24549 # Number of floating instruction queue reads
355system.cpu.iq.fp_inst_queue_writes 46362 # Number of floating instruction queue writes
356system.cpu.iq.fp_inst_queue_wakeup_accesses 5401 # Number of floating instruction queue wakeup accesses
357system.cpu.iq.int_alu_accesses 1820713311 # Number of integer alu accesses
358system.cpu.iq.fp_alu_accesses 11293 # Number of floating point alu accesses
359system.cpu.iew.lsq.thread0.forwLoads 170590285 # Number of loads that had data forwarded from stores

360system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

361system.cpu.iew.lsq.thread0.squashedLoads 128639402 # Number of loads squashed
362system.cpu.iew.lsq.thread0.ignoredResponses 477025 # Number of memory responses ignored because the instruction is squashed
363system.cpu.iew.lsq.thread0.memOrderViolation 270655 # Number of memory ordering violations
364system.cpu.iew.lsq.thread0.squashedStores 55762006 # Number of stores squashed

361system.cpu.iew.lsq.thread0.squashedLoads 128603360 # Number of loads squashed
362system.cpu.iew.lsq.thread0.ignoredResponses 477781 # Number of memory responses ignored because the instruction is squashed
363system.cpu.iew.lsq.thread0.memOrderViolation 270908 # Number of memory ordering violations
364system.cpu.iew.lsq.thread0.squashedStores 55748152 # Number of stores squashed

365system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
366system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

367system.cpu.iew.lsq.thread0.rescheduledLoads 12171 # Number of loads that were rescheduled
368system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked

367system.cpu.iew.lsq.thread0.rescheduledLoads 12303 # Number of loads that were rescheduled
368system.cpu.iew.lsq.thread0.cacheBlocked 614 # Number of times an access to memory failed due to the cache being blocked

369system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

370system.cpu.iew.iewSquashCycles 70029645 # Number of cycles IEW is squashing
371system.cpu.iew.iewBlockCycles 16354856 # Number of cycles IEW is blocking
372system.cpu.iew.iewUnblockCycles 2869041 # Number of cycles IEW is unblocking
373system.cpu.iew.iewDispatchedInsts 2034062824 # Number of instructions dispatched to IQ
374system.cpu.iew.iewDispSquashedInsts 2371349 # Number of squashed instructions skipped by dispatch
375system.cpu.iew.iewDispLoadInsts 512741559 # Number of dispatched load instructions
376system.cpu.iew.iewDispStoreInsts 204922192 # Number of dispatched store instructions
377system.cpu.iew.iewDispNonSpecInsts 5971 # Number of dispatched non-speculative instructions
378system.cpu.iew.iewIQFullEvents 1818134 # Number of times the IQ has become full, causing a stall
379system.cpu.iew.iewLSQFullEvents 76688 # Number of times the LSQ has become full, causing a stall
380system.cpu.iew.memOrderViolationEvents 270655 # Number of memory order violations
381system.cpu.iew.predictedTakenIncorrect 9112390 # Number of branches that were predicted taken incorrectly
382system.cpu.iew.predictedNotTakenIncorrect 4491959 # Number of branches that were predicted not taken incorrectly
383system.cpu.iew.branchMispredicts 13604349 # Number of branch mispredicts detected at execute
384system.cpu.iew.iewExecutedInsts 1780493134 # Number of executed instructions
385system.cpu.iew.iewExecLoadInsts 431419821 # Number of load instructions executed
386system.cpu.iew.iewExecSquashedInsts 27693113 # Number of squashed instructions skipped in execute

370system.cpu.iew.iewSquashCycles 70012605 # Number of cycles IEW is squashing
371system.cpu.iew.iewBlockCycles 16361207 # Number of cycles IEW is blocking
372system.cpu.iew.iewUnblockCycles 2863228 # Number of cycles IEW is unblocking
373system.cpu.iew.iewDispatchedInsts 2033929446 # Number of instructions dispatched to IQ
374system.cpu.iew.iewDispSquashedInsts 2371289 # Number of squashed instructions skipped by dispatch
375system.cpu.iew.iewDispLoadInsts 512705517 # Number of dispatched load instructions
376system.cpu.iew.iewDispStoreInsts 204908338 # Number of dispatched store instructions
377system.cpu.iew.iewDispNonSpecInsts 6072 # Number of dispatched non-speculative instructions
378system.cpu.iew.iewIQFullEvents 1817776 # Number of times the IQ has become full, causing a stall
379system.cpu.iew.iewLSQFullEvents 76759 # Number of times the LSQ has become full, causing a stall
380system.cpu.iew.memOrderViolationEvents 270908 # Number of memory order violations
381system.cpu.iew.predictedTakenIncorrect 9111612 # Number of branches that were predicted taken incorrectly
382system.cpu.iew.predictedNotTakenIncorrect 4490464 # Number of branches that were predicted not taken incorrectly
383system.cpu.iew.branchMispredicts 13602076 # Number of branch mispredicts detected at execute
384system.cpu.iew.iewExecutedInsts 1780387317 # Number of executed instructions
385system.cpu.iew.iewExecLoadInsts 431399251 # Number of load instructions executed
386system.cpu.iew.iewExecSquashedInsts 27692984 # Number of squashed instructions skipped in execute

387system.cpu.iew.exec_swp 0 # number of swp insts executed
388system.cpu.iew.exec_nop 0 # number of nop insts executed

389system.cpu.iew.exec_refs 602103819 # number of memory reference insts executed
390system.cpu.iew.exec_branches 169268529 # Number of branches executed
391system.cpu.iew.exec_stores 170683998 # Number of stores executed
392system.cpu.iew.exec_rate 2.048822 # Inst execution rate
393system.cpu.iew.wb_sent 1775386741 # cumulative count of insts sent to commit
394system.cpu.iew.wb_count 1768697872 # cumulative count of insts written-back
395system.cpu.iew.wb_producers 1341621194 # num instructions producing a value
396system.cpu.iew.wb_consumers 1964432295 # num instructions consuming a value

389system.cpu.iew.exec_refs 602062000 # number of memory reference insts executed
390system.cpu.iew.exec_branches 169264678 # Number of branches executed
391system.cpu.iew.exec_stores 170662749 # Number of stores executed
392system.cpu.iew.exec_rate 2.048572 # Inst execution rate
393system.cpu.iew.wb_sent 1775274937 # cumulative count of insts sent to commit
394system.cpu.iew.wb_count 1768593529 # cumulative count of insts written-back
395system.cpu.iew.wb_producers 1341496349 # num instructions producing a value
396system.cpu.iew.wb_consumers 1964252976 # num instructions consuming a value

397system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

398system.cpu.iew.wb_rate 2.035249 # insts written-back per cycle
399system.cpu.iew.wb_fanout 0.682956 # average fanout of values written-back

398system.cpu.iew.wb_rate 2.035001 # insts written-back per cycle
399system.cpu.iew.wb_fanout 0.682955 # average fanout of values written-back

400system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

401system.cpu.commit.commitSquashedInsts 505108426 # The number of squashed insts skipped by commit

401system.cpu.commit.commitSquashedInsts 504973387 # The number of squashed insts skipped by commit

402system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards

403system.cpu.commit.branchMispredicts 13166732 # The number of times a branch was mispredicted
404system.cpu.commit.committed_per_cycle::samples 783709846 # Number of insts commited each cycle
405system.cpu.commit.committed_per_cycle::mean 1.950963 # Number of insts commited each cycle
406system.cpu.commit.committed_per_cycle::stdev 2.458599 # Number of insts commited each cycle

403system.cpu.commit.branchMispredicts 13165974 # The number of times a branch was mispredicted
404system.cpu.commit.committed_per_cycle::samples 783748992 # Number of insts commited each cycle
405system.cpu.commit.committed_per_cycle::mean 1.950865 # Number of insts commited each cycle
406system.cpu.commit.committed_per_cycle::stdev 2.458310 # Number of insts commited each cycle

407system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

408system.cpu.commit.committed_per_cycle::0 290449300 37.06% 37.06% # Number of insts commited each cycle
409system.cpu.commit.committed_per_cycle::1 195531985 24.95% 62.01% # Number of insts commited each cycle
410system.cpu.commit.committed_per_cycle::2 62027309 7.91% 69.92% # Number of insts commited each cycle
411system.cpu.commit.committed_per_cycle::3 92272320 11.77% 81.70% # Number of insts commited each cycle
412system.cpu.commit.committed_per_cycle::4 25028455 3.19% 84.89% # Number of insts commited each cycle
413system.cpu.commit.committed_per_cycle::5 28378984 3.62% 88.51% # Number of insts commited each cycle
414system.cpu.commit.committed_per_cycle::6 9417725 1.20% 89.72% # Number of insts commited each cycle
415system.cpu.commit.committed_per_cycle::7 10760096 1.37% 91.09% # Number of insts commited each cycle
416system.cpu.commit.committed_per_cycle::8 69843672 8.91% 100.00% # Number of insts commited each cycle

408system.cpu.commit.committed_per_cycle::0 290412107 37.05% 37.05% # Number of insts commited each cycle
409system.cpu.commit.committed_per_cycle::1 195557118 24.95% 62.01% # Number of insts commited each cycle
410system.cpu.commit.committed_per_cycle::2 62107499 7.92% 69.93% # Number of insts commited each cycle
411system.cpu.commit.committed_per_cycle::3 92255388 11.77% 81.70% # Number of insts commited each cycle
412system.cpu.commit.committed_per_cycle::4 25035287 3.19% 84.90% # Number of insts commited each cycle
413system.cpu.commit.committed_per_cycle::5 28388589 3.62% 88.52% # Number of insts commited each cycle
414system.cpu.commit.committed_per_cycle::6 9410992 1.20% 89.72% # Number of insts commited each cycle
415system.cpu.commit.committed_per_cycle::7 10755720 1.37% 91.09% # Number of insts commited each cycle
416system.cpu.commit.committed_per_cycle::8 69826292 8.91% 100.00% # Number of insts commited each cycle

417system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
418system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
419system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

420system.cpu.commit.committed_per_cycle::total 783709846 # Number of insts commited each cycle

420system.cpu.commit.committed_per_cycle::total 783748992 # Number of insts commited each cycle

421system.cpu.commit.committedInsts 826877109 # Number of instructions committed
422system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
423system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
424system.cpu.commit.refs 533262343 # Number of memory references committed
425system.cpu.commit.loads 384102157 # Number of loads committed
426system.cpu.commit.membars 0 # Number of memory barriers committed
427system.cpu.commit.branches 149758583 # Number of branches committed
428system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
429system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions.
430system.cpu.commit.function_calls 0 # Number of function calls committed.

431system.cpu.commit.bw_lim_events 69843672 # number cycles where commit BW limit reached

431system.cpu.commit.bw_lim_events 69826292 # number cycles where commit BW limit reached

432system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

433system.cpu.rob.rob_reads 2747963301 # The number of ROB reads
434system.cpu.rob.rob_writes 4138406089 # The number of ROB writes
435system.cpu.timesIdled 337869 # Number of times that the entire CPU went into an idle state and unscheduled itself
436system.cpu.idleCycles 15293202 # Total number of cycles that the CPU has spent unscheduled due to idling

433system.cpu.rob.rob_reads 2747884788 # The number of ROB reads
434system.cpu.rob.rob_writes 4138119354 # The number of ROB writes
435system.cpu.timesIdled 343577 # Number of times that the entire CPU went into an idle state and unscheduled itself
436system.cpu.idleCycles 15325594 # Total number of cycles that the CPU has spent unscheduled due to idling

437system.cpu.committedInsts 826877109 # Number of Instructions Simulated
438system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
439system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated

440system.cpu.cpi 1.050982 # CPI: Cycles Per Instruction
441system.cpu.cpi_total 1.050982 # CPI: Total CPI of All Threads
442system.cpu.ipc 0.951491 # IPC: Instructions Per Cycle
443system.cpu.ipc_total 0.951491 # IPC: Total IPC of All Threads
444system.cpu.int_regfile_reads 3357369347 # number of integer regfile reads
445system.cpu.int_regfile_writes 1848457687 # number of integer regfile writes
446system.cpu.fp_regfile_reads 4903 # number of floating regfile reads

440system.cpu.cpi 1.051048 # CPI: Cycles Per Instruction
441system.cpu.cpi_total 1.051048 # CPI: Total CPI of All Threads
442system.cpu.ipc 0.951432 # IPC: Instructions Per Cycle
443system.cpu.ipc_total 0.951432 # IPC: Total IPC of All Threads
444system.cpu.int_regfile_reads 3357192668 # number of integer regfile reads
445system.cpu.int_regfile_writes 1848351672 # number of integer regfile writes
446system.cpu.fp_regfile_reads 5396 # number of floating regfile reads

447system.cpu.fp_regfile_writes 7 # number of floating regfile writes

448system.cpu.misc_regfile_reads 980231667 # number of misc regfile reads

448system.cpu.misc_regfile_reads 980175338 # number of misc regfile reads

449system.cpu.misc_regfile_writes 1 # number of misc regfile writes

450system.cpu.icache.replacements 5495 # number of replacements
451system.cpu.icache.tagsinuse 1031.765588 # Cycle average of tags in use
452system.cpu.icache.total_refs 173216071 # Total number of references to valid blocks.
453system.cpu.icache.sampled_refs 7085 # Sample count of references to valid blocks.
454system.cpu.icache.avg_refs 24448.281016 # Average number of references to valid blocks.

450system.cpu.icache.replacements 5459 # number of replacements
451system.cpu.icache.tagsinuse 1031.272902 # Cycle average of tags in use
452system.cpu.icache.total_refs 173201219 # Total number of references to valid blocks.
453system.cpu.icache.sampled_refs 7046 # Sample count of references to valid blocks.
454system.cpu.icache.avg_refs 24581.495742 # Average number of references to valid blocks.

455system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

456system.cpu.icache.occ_blocks::cpu.inst 1031.765588 # Average occupied blocks per requestor
457system.cpu.icache.occ_percent::cpu.inst 0.503792 # Average percentage of cache occupancy
458system.cpu.icache.occ_percent::total 0.503792 # Average percentage of cache occupancy
459system.cpu.icache.ReadReq_hits::cpu.inst 173231264 # number of ReadReq hits
460system.cpu.icache.ReadReq_hits::total 173231264 # number of ReadReq hits
461system.cpu.icache.demand_hits::cpu.inst 173231264 # number of demand (read+write) hits
462system.cpu.icache.demand_hits::total 173231264 # number of demand (read+write) hits
463system.cpu.icache.overall_hits::cpu.inst 173231264 # number of overall hits
464system.cpu.icache.overall_hits::total 173231264 # number of overall hits
465system.cpu.icache.ReadReq_misses::cpu.inst 221064 # number of ReadReq misses
466system.cpu.icache.ReadReq_misses::total 221064 # number of ReadReq misses
467system.cpu.icache.demand_misses::cpu.inst 221064 # number of demand (read+write) misses
468system.cpu.icache.demand_misses::total 221064 # number of demand (read+write) misses
469system.cpu.icache.overall_misses::cpu.inst 221064 # number of overall misses
470system.cpu.icache.overall_misses::total 221064 # number of overall misses
471system.cpu.icache.ReadReq_miss_latency::cpu.inst 1408552499 # number of ReadReq miss cycles
472system.cpu.icache.ReadReq_miss_latency::total 1408552499 # number of ReadReq miss cycles
473system.cpu.icache.demand_miss_latency::cpu.inst 1408552499 # number of demand (read+write) miss cycles
474system.cpu.icache.demand_miss_latency::total 1408552499 # number of demand (read+write) miss cycles
475system.cpu.icache.overall_miss_latency::cpu.inst 1408552499 # number of overall miss cycles
476system.cpu.icache.overall_miss_latency::total 1408552499 # number of overall miss cycles
477system.cpu.icache.ReadReq_accesses::cpu.inst 173452328 # number of ReadReq accesses(hits+misses)
478system.cpu.icache.ReadReq_accesses::total 173452328 # number of ReadReq accesses(hits+misses)
479system.cpu.icache.demand_accesses::cpu.inst 173452328 # number of demand (read+write) accesses
480system.cpu.icache.demand_accesses::total 173452328 # number of demand (read+write) accesses
481system.cpu.icache.overall_accesses::cpu.inst 173452328 # number of overall (read+write) accesses
482system.cpu.icache.overall_accesses::total 173452328 # number of overall (read+write) accesses
483system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001274 # miss rate for ReadReq accesses
484system.cpu.icache.ReadReq_miss_rate::total 0.001274 # miss rate for ReadReq accesses
485system.cpu.icache.demand_miss_rate::cpu.inst 0.001274 # miss rate for demand accesses
486system.cpu.icache.demand_miss_rate::total 0.001274 # miss rate for demand accesses
487system.cpu.icache.overall_miss_rate::cpu.inst 0.001274 # miss rate for overall accesses
488system.cpu.icache.overall_miss_rate::total 0.001274 # miss rate for overall accesses
489system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6371.695523 # average ReadReq miss latency
490system.cpu.icache.ReadReq_avg_miss_latency::total 6371.695523 # average ReadReq miss latency
491system.cpu.icache.demand_avg_miss_latency::cpu.inst 6371.695523 # average overall miss latency
492system.cpu.icache.demand_avg_miss_latency::total 6371.695523 # average overall miss latency
493system.cpu.icache.overall_avg_miss_latency::cpu.inst 6371.695523 # average overall miss latency
494system.cpu.icache.overall_avg_miss_latency::total 6371.695523 # average overall miss latency
495system.cpu.icache.blocked_cycles::no_mshrs 444 # number of cycles access was blocked

456system.cpu.icache.occ_blocks::cpu.inst 1031.272902 # Average occupied blocks per requestor
457system.cpu.icache.occ_percent::cpu.inst 0.503551 # Average percentage of cache occupancy
458system.cpu.icache.occ_percent::total 0.503551 # Average percentage of cache occupancy
459system.cpu.icache.ReadReq_hits::cpu.inst 173216530 # number of ReadReq hits
460system.cpu.icache.ReadReq_hits::total 173216530 # number of ReadReq hits
461system.cpu.icache.demand_hits::cpu.inst 173216530 # number of demand (read+write) hits
462system.cpu.icache.demand_hits::total 173216530 # number of demand (read+write) hits
463system.cpu.icache.overall_hits::cpu.inst 173216530 # number of overall hits
464system.cpu.icache.overall_hits::total 173216530 # number of overall hits
465system.cpu.icache.ReadReq_misses::cpu.inst 221250 # number of ReadReq misses
466system.cpu.icache.ReadReq_misses::total 221250 # number of ReadReq misses
467system.cpu.icache.demand_misses::cpu.inst 221250 # number of demand (read+write) misses
468system.cpu.icache.demand_misses::total 221250 # number of demand (read+write) misses
469system.cpu.icache.overall_misses::cpu.inst 221250 # number of overall misses
470system.cpu.icache.overall_misses::total 221250 # number of overall misses
471system.cpu.icache.ReadReq_miss_latency::cpu.inst 1405122498 # number of ReadReq miss cycles
472system.cpu.icache.ReadReq_miss_latency::total 1405122498 # number of ReadReq miss cycles
473system.cpu.icache.demand_miss_latency::cpu.inst 1405122498 # number of demand (read+write) miss cycles
474system.cpu.icache.demand_miss_latency::total 1405122498 # number of demand (read+write) miss cycles
475system.cpu.icache.overall_miss_latency::cpu.inst 1405122498 # number of overall miss cycles
476system.cpu.icache.overall_miss_latency::total 1405122498 # number of overall miss cycles
477system.cpu.icache.ReadReq_accesses::cpu.inst 173437780 # number of ReadReq accesses(hits+misses)
478system.cpu.icache.ReadReq_accesses::total 173437780 # number of ReadReq accesses(hits+misses)
479system.cpu.icache.demand_accesses::cpu.inst 173437780 # number of demand (read+write) accesses
480system.cpu.icache.demand_accesses::total 173437780 # number of demand (read+write) accesses
481system.cpu.icache.overall_accesses::cpu.inst 173437780 # number of overall (read+write) accesses
482system.cpu.icache.overall_accesses::total 173437780 # number of overall (read+write) accesses
483system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001276 # miss rate for ReadReq accesses
484system.cpu.icache.ReadReq_miss_rate::total 0.001276 # miss rate for ReadReq accesses
485system.cpu.icache.demand_miss_rate::cpu.inst 0.001276 # miss rate for demand accesses
486system.cpu.icache.demand_miss_rate::total 0.001276 # miss rate for demand accesses
487system.cpu.icache.overall_miss_rate::cpu.inst 0.001276 # miss rate for overall accesses
488system.cpu.icache.overall_miss_rate::total 0.001276 # miss rate for overall accesses
489system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6350.836149 # average ReadReq miss latency
490system.cpu.icache.ReadReq_avg_miss_latency::total 6350.836149 # average ReadReq miss latency
491system.cpu.icache.demand_avg_miss_latency::cpu.inst 6350.836149 # average overall miss latency
492system.cpu.icache.demand_avg_miss_latency::total 6350.836149 # average overall miss latency
493system.cpu.icache.overall_avg_miss_latency::cpu.inst 6350.836149 # average overall miss latency
494system.cpu.icache.overall_avg_miss_latency::total 6350.836149 # average overall miss latency
495system.cpu.icache.blocked_cycles::no_mshrs 511 # number of cycles access was blocked

496system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

497system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked

497system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked

498system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

499system.cpu.icache.avg_blocked_cycles::no_mshrs 31.714286 # average number of cycles each access was blocked

499system.cpu.icache.avg_blocked_cycles::no_mshrs 34.066667 # average number of cycles each access was blocked

500system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
501system.cpu.icache.fast_writes 0 # number of fast writes performed
502system.cpu.icache.cache_copies 0 # number of cache copies performed

503system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2465 # number of ReadReq MSHR hits
504system.cpu.icache.ReadReq_mshr_hits::total 2465 # number of ReadReq MSHR hits
505system.cpu.icache.demand_mshr_hits::cpu.inst 2465 # number of demand (read+write) MSHR hits
506system.cpu.icache.demand_mshr_hits::total 2465 # number of demand (read+write) MSHR hits
507system.cpu.icache.overall_mshr_hits::cpu.inst 2465 # number of overall MSHR hits
508system.cpu.icache.overall_mshr_hits::total 2465 # number of overall MSHR hits
509system.cpu.icache.ReadReq_mshr_misses::cpu.inst 218599 # number of ReadReq MSHR misses
510system.cpu.icache.ReadReq_mshr_misses::total 218599 # number of ReadReq MSHR misses
511system.cpu.icache.demand_mshr_misses::cpu.inst 218599 # number of demand (read+write) MSHR misses
512system.cpu.icache.demand_mshr_misses::total 218599 # number of demand (read+write) MSHR misses
513system.cpu.icache.overall_mshr_misses::cpu.inst 218599 # number of overall MSHR misses
514system.cpu.icache.overall_mshr_misses::total 218599 # number of overall MSHR misses
515system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 888293499 # number of ReadReq MSHR miss cycles
516system.cpu.icache.ReadReq_mshr_miss_latency::total 888293499 # number of ReadReq MSHR miss cycles
517system.cpu.icache.demand_mshr_miss_latency::cpu.inst 888293499 # number of demand (read+write) MSHR miss cycles
518system.cpu.icache.demand_mshr_miss_latency::total 888293499 # number of demand (read+write) MSHR miss cycles
519system.cpu.icache.overall_mshr_miss_latency::cpu.inst 888293499 # number of overall MSHR miss cycles
520system.cpu.icache.overall_mshr_miss_latency::total 888293499 # number of overall MSHR miss cycles
521system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for ReadReq accesses
522system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001260 # mshr miss rate for ReadReq accesses
523system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for demand accesses
524system.cpu.icache.demand_mshr_miss_rate::total 0.001260 # mshr miss rate for demand accesses
525system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for overall accesses
526system.cpu.icache.overall_mshr_miss_rate::total 0.001260 # mshr miss rate for overall accesses
527system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4063.575309 # average ReadReq mshr miss latency
528system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4063.575309 # average ReadReq mshr miss latency
529system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4063.575309 # average overall mshr miss latency
530system.cpu.icache.demand_avg_mshr_miss_latency::total 4063.575309 # average overall mshr miss latency
531system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4063.575309 # average overall mshr miss latency
532system.cpu.icache.overall_avg_mshr_miss_latency::total 4063.575309 # average overall mshr miss latency

503system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2445 # number of ReadReq MSHR hits
504system.cpu.icache.ReadReq_mshr_hits::total 2445 # number of ReadReq MSHR hits
505system.cpu.icache.demand_mshr_hits::cpu.inst 2445 # number of demand (read+write) MSHR hits
506system.cpu.icache.demand_mshr_hits::total 2445 # number of demand (read+write) MSHR hits
507system.cpu.icache.overall_mshr_hits::cpu.inst 2445 # number of overall MSHR hits
508system.cpu.icache.overall_mshr_hits::total 2445 # number of overall MSHR hits
509system.cpu.icache.ReadReq_mshr_misses::cpu.inst 218805 # number of ReadReq MSHR misses
510system.cpu.icache.ReadReq_mshr_misses::total 218805 # number of ReadReq MSHR misses
511system.cpu.icache.demand_mshr_misses::cpu.inst 218805 # number of demand (read+write) MSHR misses
512system.cpu.icache.demand_mshr_misses::total 218805 # number of demand (read+write) MSHR misses
513system.cpu.icache.overall_mshr_misses::cpu.inst 218805 # number of overall MSHR misses
514system.cpu.icache.overall_mshr_misses::total 218805 # number of overall MSHR misses
515system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 886299999 # number of ReadReq MSHR miss cycles
516system.cpu.icache.ReadReq_mshr_miss_latency::total 886299999 # number of ReadReq MSHR miss cycles
517system.cpu.icache.demand_mshr_miss_latency::cpu.inst 886299999 # number of demand (read+write) MSHR miss cycles
518system.cpu.icache.demand_mshr_miss_latency::total 886299999 # number of demand (read+write) MSHR miss cycles
519system.cpu.icache.overall_mshr_miss_latency::cpu.inst 886299999 # number of overall MSHR miss cycles
520system.cpu.icache.overall_mshr_miss_latency::total 886299999 # number of overall MSHR miss cycles
521system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for ReadReq accesses
522system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001262 # mshr miss rate for ReadReq accesses
523system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for demand accesses
524system.cpu.icache.demand_mshr_miss_rate::total 0.001262 # mshr miss rate for demand accesses
525system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001262 # mshr miss rate for overall accesses
526system.cpu.icache.overall_mshr_miss_rate::total 0.001262 # mshr miss rate for overall accesses
527system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4050.638692 # average ReadReq mshr miss latency
528system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4050.638692 # average ReadReq mshr miss latency
529system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4050.638692 # average overall mshr miss latency
530system.cpu.icache.demand_avg_mshr_miss_latency::total 4050.638692 # average overall mshr miss latency
531system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4050.638692 # average overall mshr miss latency
532system.cpu.icache.overall_avg_mshr_miss_latency::total 4050.638692 # average overall mshr miss latency

533system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

534system.cpu.l2cache.replacements 352874 # number of replacements
535system.cpu.l2cache.tagsinuse 29622.750601 # Cycle average of tags in use
536system.cpu.l2cache.total_refs 3697631 # Total number of references to valid blocks.
537system.cpu.l2cache.sampled_refs 385235 # Sample count of references to valid blocks.
538system.cpu.l2cache.avg_refs 9.598378 # Average number of references to valid blocks.

534system.cpu.l2cache.replacements 352890 # number of replacements
535system.cpu.l2cache.tagsinuse 29622.917064 # Cycle average of tags in use
536system.cpu.l2cache.total_refs 3697451 # Total number of references to valid blocks.
537system.cpu.l2cache.sampled_refs 385249 # Sample count of references to valid blocks.
538system.cpu.l2cache.avg_refs 9.597562 # Average number of references to valid blocks.

539system.cpu.l2cache.warmup_cycle 202056635000 # Cycle when the warmup percentage was hit.

540system.cpu.l2cache.occ_blocks::writebacks 21052.992991 # Average occupied blocks per requestor
541system.cpu.l2cache.occ_blocks::cpu.inst 232.749062 # Average occupied blocks per requestor
542system.cpu.l2cache.occ_blocks::cpu.data 8337.008547 # Average occupied blocks per requestor
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544system.cpu.l2cache.occ_percent::cpu.inst 0.007103 # Average percentage of cache occupancy
545system.cpu.l2cache.occ_percent::cpu.data 0.254425 # Average percentage of cache occupancy
546system.cpu.l2cache.occ_percent::total 0.904015 # Average percentage of cache occupancy
547system.cpu.l2cache.ReadReq_hits::cpu.inst 3789 # number of ReadReq hits
548system.cpu.l2cache.ReadReq_hits::cpu.data 1586693 # number of ReadReq hits
549system.cpu.l2cache.ReadReq_hits::total 1590482 # number of ReadReq hits
550system.cpu.l2cache.Writeback_hits::writebacks 2331206 # number of Writeback hits
551system.cpu.l2cache.Writeback_hits::total 2331206 # number of Writeback hits
552system.cpu.l2cache.UpgradeReq_hits::cpu.data 1519 # number of UpgradeReq hits
553system.cpu.l2cache.UpgradeReq_hits::total 1519 # number of UpgradeReq hits
554system.cpu.l2cache.ReadExReq_hits::cpu.data 564639 # number of ReadExReq hits
555system.cpu.l2cache.ReadExReq_hits::total 564639 # number of ReadExReq hits
556system.cpu.l2cache.demand_hits::cpu.inst 3789 # number of demand (read+write) hits
557system.cpu.l2cache.demand_hits::cpu.data 2151332 # number of demand (read+write) hits
558system.cpu.l2cache.demand_hits::total 2155121 # number of demand (read+write) hits
559system.cpu.l2cache.overall_hits::cpu.inst 3789 # number of overall hits
560system.cpu.l2cache.overall_hits::cpu.data 2151332 # number of overall hits
561system.cpu.l2cache.overall_hits::total 2155121 # number of overall hits
562system.cpu.l2cache.ReadReq_misses::cpu.inst 3244 # number of ReadReq misses
563system.cpu.l2cache.ReadReq_misses::cpu.data 175574 # number of ReadReq misses
564system.cpu.l2cache.ReadReq_misses::total 178818 # number of ReadReq misses
565system.cpu.l2cache.UpgradeReq_misses::cpu.data 209962 # number of UpgradeReq misses
566system.cpu.l2cache.UpgradeReq_misses::total 209962 # number of UpgradeReq misses
567system.cpu.l2cache.ReadExReq_misses::cpu.data 206766 # number of ReadExReq misses
568system.cpu.l2cache.ReadExReq_misses::total 206766 # number of ReadExReq misses
569system.cpu.l2cache.demand_misses::cpu.inst 3244 # number of demand (read+write) misses
570system.cpu.l2cache.demand_misses::cpu.data 382340 # number of demand (read+write) misses
571system.cpu.l2cache.demand_misses::total 385584 # number of demand (read+write) misses
572system.cpu.l2cache.overall_misses::cpu.inst 3244 # number of overall misses
573system.cpu.l2cache.overall_misses::cpu.data 382340 # number of overall misses
574system.cpu.l2cache.overall_misses::total 385584 # number of overall misses
575system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200651500 # number of ReadReq miss cycles
576system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10110867455 # number of ReadReq miss cycles
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578system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7224500 # number of UpgradeReq miss cycles
579system.cpu.l2cache.UpgradeReq_miss_latency::total 7224500 # number of UpgradeReq miss cycles
580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10373782000 # number of ReadExReq miss cycles
581system.cpu.l2cache.ReadExReq_miss_latency::total 10373782000 # number of ReadExReq miss cycles
582system.cpu.l2cache.demand_miss_latency::cpu.inst 200651500 # number of demand (read+write) miss cycles
583system.cpu.l2cache.demand_miss_latency::cpu.data 20484649455 # number of demand (read+write) miss cycles
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585system.cpu.l2cache.overall_miss_latency::cpu.inst 200651500 # number of overall miss cycles
586system.cpu.l2cache.overall_miss_latency::cpu.data 20484649455 # number of overall miss cycles
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588system.cpu.l2cache.ReadReq_accesses::cpu.inst 7033 # number of ReadReq accesses(hits+misses)
589system.cpu.l2cache.ReadReq_accesses::cpu.data 1762267 # number of ReadReq accesses(hits+misses)
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591system.cpu.l2cache.Writeback_accesses::writebacks 2331206 # number of Writeback accesses(hits+misses)
592system.cpu.l2cache.Writeback_accesses::total 2331206 # number of Writeback accesses(hits+misses)
593system.cpu.l2cache.UpgradeReq_accesses::cpu.data 211481 # number of UpgradeReq accesses(hits+misses)
594system.cpu.l2cache.UpgradeReq_accesses::total 211481 # number of UpgradeReq accesses(hits+misses)
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601system.cpu.l2cache.overall_accesses::cpu.data 2533672 # number of overall (read+write) accesses
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606system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992817 # miss rate for UpgradeReq accesses
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610system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461254 # miss rate for demand accesses
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613system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461254 # miss rate for overall accesses
614system.cpu.l2cache.overall_miss_rate::cpu.data 0.150904 # miss rate for overall accesses
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619system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.408607 # average UpgradeReq miss latency
620system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.408607 # average UpgradeReq miss latency
621system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50171.604616 # average ReadExReq miss latency
622system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50171.604616 # average ReadExReq miss latency
623system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61853.113440 # average overall miss latency
624system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53577.050413 # average overall miss latency
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626system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61853.113440 # average overall miss latency
627system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53577.050413 # average overall miss latency
628system.cpu.l2cache.overall_avg_miss_latency::total 53646.678687 # average overall miss latency

540system.cpu.l2cache.occ_blocks::writebacks 21050.647644 # Average occupied blocks per requestor
541system.cpu.l2cache.occ_blocks::cpu.inst 232.691985 # Average occupied blocks per requestor
542system.cpu.l2cache.occ_blocks::cpu.data 8339.577435 # Average occupied blocks per requestor
543system.cpu.l2cache.occ_percent::writebacks 0.642415 # Average percentage of cache occupancy
544system.cpu.l2cache.occ_percent::cpu.inst 0.007101 # Average percentage of cache occupancy
545system.cpu.l2cache.occ_percent::cpu.data 0.254504 # Average percentage of cache occupancy
546system.cpu.l2cache.occ_percent::total 0.904020 # Average percentage of cache occupancy
547system.cpu.l2cache.ReadReq_hits::cpu.inst 3783 # number of ReadReq hits
548system.cpu.l2cache.ReadReq_hits::cpu.data 1586610 # number of ReadReq hits
549system.cpu.l2cache.ReadReq_hits::total 1590393 # number of ReadReq hits
550system.cpu.l2cache.Writeback_hits::writebacks 2331126 # number of Writeback hits
551system.cpu.l2cache.Writeback_hits::total 2331126 # number of Writeback hits
552system.cpu.l2cache.UpgradeReq_hits::cpu.data 1528 # number of UpgradeReq hits
553system.cpu.l2cache.UpgradeReq_hits::total 1528 # number of UpgradeReq hits
554system.cpu.l2cache.ReadExReq_hits::cpu.data 564574 # number of ReadExReq hits
555system.cpu.l2cache.ReadExReq_hits::total 564574 # number of ReadExReq hits
556system.cpu.l2cache.demand_hits::cpu.inst 3783 # number of demand (read+write) hits
557system.cpu.l2cache.demand_hits::cpu.data 2151184 # number of demand (read+write) hits
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559system.cpu.l2cache.overall_hits::cpu.inst 3783 # number of overall hits
560system.cpu.l2cache.overall_hits::cpu.data 2151184 # number of overall hits
561system.cpu.l2cache.overall_hits::total 2154967 # number of overall hits
562system.cpu.l2cache.ReadReq_misses::cpu.inst 3238 # number of ReadReq misses
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566system.cpu.l2cache.UpgradeReq_misses::total 210169 # number of UpgradeReq misses
567system.cpu.l2cache.ReadExReq_misses::cpu.data 206764 # number of ReadExReq misses
568system.cpu.l2cache.ReadExReq_misses::total 206764 # number of ReadExReq misses
569system.cpu.l2cache.demand_misses::cpu.inst 3238 # number of demand (read+write) misses
570system.cpu.l2cache.demand_misses::cpu.data 382364 # number of demand (read+write) misses
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572system.cpu.l2cache.overall_misses::cpu.inst 3238 # number of overall misses
573system.cpu.l2cache.overall_misses::cpu.data 382364 # number of overall misses
574system.cpu.l2cache.overall_misses::total 385602 # number of overall misses
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580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10370858500 # number of ReadExReq miss cycles
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592system.cpu.l2cache.Writeback_accesses::total 2331126 # number of Writeback accesses(hits+misses)
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617system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57602.539601 # average ReadReq miss latency
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621system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50157.950610 # average ReadExReq miss latency
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627system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53576.865118 # average overall miss latency
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634system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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669system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992817 # mshr miss rate for UpgradeReq accesses
670system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268038 # mshr miss rate for ReadExReq accesses
671system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268038 # mshr miss rate for ReadExReq accesses
672system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461254 # mshr miss rate for demand accesses
673system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150904 # mshr miss rate for demand accesses
674system.cpu.l2cache.demand_mshr_miss_rate::total 0.151763 # mshr miss rate for demand accesses
675system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461254 # mshr miss rate for overall accesses
676system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150904 # mshr miss rate for overall accesses
677system.cpu.l2cache.overall_mshr_miss_rate::total 0.151763 # mshr miss rate for overall accesses
678system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49427.329223 # average ReadReq mshr miss latency
679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45212.075193 # average ReadReq mshr miss latency
680system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45288.545594 # average ReadReq mshr miss latency
681system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.762467 # average UpgradeReq mshr miss latency
682system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.762467 # average UpgradeReq mshr miss latency
683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37660.219925 # average ReadExReq mshr miss latency
684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37660.219925 # average ReadExReq mshr miss latency
685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49427.329223 # average overall mshr miss latency
686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41128.100442 # average overall mshr miss latency
687system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41197.923615 # average overall mshr miss latency
688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49427.329223 # average overall mshr miss latency
689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41128.100442 # average overall mshr miss latency
690system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41197.923615 # average overall mshr miss latency

637system.cpu.l2cache.writebacks::writebacks 293616 # number of writebacks
638system.cpu.l2cache.writebacks::total 293616 # number of writebacks
639system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3238 # number of ReadReq MSHR misses
640system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175600 # number of ReadReq MSHR misses
641system.cpu.l2cache.ReadReq_mshr_misses::total 178838 # number of ReadReq MSHR misses
642system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 210169 # number of UpgradeReq MSHR misses
643system.cpu.l2cache.UpgradeReq_mshr_misses::total 210169 # number of UpgradeReq MSHR misses
644system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206764 # number of ReadExReq MSHR misses
645system.cpu.l2cache.ReadExReq_mshr_misses::total 206764 # number of ReadExReq MSHR misses
646system.cpu.l2cache.demand_mshr_misses::cpu.inst 3238 # number of demand (read+write) MSHR misses
647system.cpu.l2cache.demand_mshr_misses::cpu.data 382364 # number of demand (read+write) MSHR misses
648system.cpu.l2cache.demand_mshr_misses::total 385602 # number of demand (read+write) MSHR misses
649system.cpu.l2cache.overall_mshr_misses::cpu.inst 3238 # number of overall MSHR misses
650system.cpu.l2cache.overall_mshr_misses::cpu.data 382364 # number of overall MSHR misses
651system.cpu.l2cache.overall_mshr_misses::total 385602 # number of overall MSHR misses
652system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158016497 # number of ReadReq MSHR miss cycles
653system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7941834689 # number of ReadReq MSHR miss cycles
654system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8099851186 # number of ReadReq MSHR miss cycles
655system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2107112859 # number of UpgradeReq MSHR miss cycles
656system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2107112859 # number of UpgradeReq MSHR miss cycles
657system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7783948782 # number of ReadExReq MSHR miss cycles
658system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7783948782 # number of ReadExReq MSHR miss cycles
659system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158016497 # number of demand (read+write) MSHR miss cycles
660system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15725783471 # number of demand (read+write) MSHR miss cycles
661system.cpu.l2cache.demand_mshr_miss_latency::total 15883799968 # number of demand (read+write) MSHR miss cycles
662system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158016497 # number of overall MSHR miss cycles
663system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15725783471 # number of overall MSHR miss cycles
664system.cpu.l2cache.overall_mshr_miss_latency::total 15883799968 # number of overall MSHR miss cycles
665system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for ReadReq accesses
666system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099648 # mshr miss rate for ReadReq accesses
667system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101082 # mshr miss rate for ReadReq accesses
668system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992782 # mshr miss rate for UpgradeReq accesses
669system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992782 # mshr miss rate for UpgradeReq accesses
670system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268059 # mshr miss rate for ReadExReq accesses
671system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268059 # mshr miss rate for ReadExReq accesses
672system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for demand accesses
673system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for demand accesses
674system.cpu.l2cache.demand_mshr_miss_rate::total 0.151778 # mshr miss rate for demand accesses
675system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461188 # mshr miss rate for overall accesses
676system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for overall accesses
677system.cpu.l2cache.overall_mshr_miss_rate::total 0.151778 # mshr miss rate for overall accesses
678system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48800.647622 # average ReadReq mshr miss latency
679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45226.849026 # average ReadReq mshr miss latency
680system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45291.555408 # average ReadReq mshr miss latency
681system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.802373 # average UpgradeReq mshr miss latency
682system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.802373 # average UpgradeReq mshr miss latency
683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.537995 # average ReadExReq mshr miss latency
684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.537995 # average ReadExReq mshr miss latency
685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48800.647622 # average overall mshr miss latency
686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.782613 # average overall mshr miss latency
687system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41192.213650 # average overall mshr miss latency
688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48800.647622 # average overall mshr miss latency
689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.782613 # average overall mshr miss latency
690system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41192.213650 # average overall mshr miss latency

691system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

692system.cpu.dcache.replacements 2529574 # number of replacements
693system.cpu.dcache.tagsinuse 4087.791317 # Cycle average of tags in use
694system.cpu.dcache.total_refs 405282445 # Total number of references to valid blocks.
695system.cpu.dcache.sampled_refs 2533670 # Sample count of references to valid blocks.
696system.cpu.dcache.avg_refs 159.958655 # Average number of references to valid blocks.

692system.cpu.dcache.replacements 2529450 # number of replacements
693system.cpu.dcache.tagsinuse 4087.791832 # Cycle average of tags in use
694system.cpu.dcache.total_refs 405306727 # Total number of references to valid blocks.
695system.cpu.dcache.sampled_refs 2533546 # Sample count of references to valid blocks.
696system.cpu.dcache.avg_refs 159.976068 # Average number of references to valid blocks.

697system.cpu.dcache.warmup_cycle 1794502000 # Cycle when the warmup percentage was hit.

698system.cpu.dcache.occ_blocks::cpu.data 4087.791317 # Average occupied blocks per requestor

698system.cpu.dcache.occ_blocks::cpu.data 4087.791832 # Average occupied blocks per requestor

699system.cpu.dcache.occ_percent::cpu.data 0.997996 # Average percentage of cache occupancy
700system.cpu.dcache.occ_percent::total 0.997996 # Average percentage of cache occupancy

701system.cpu.dcache.ReadReq_hits::cpu.data 256552049 # number of ReadReq hits
702system.cpu.dcache.ReadReq_hits::total 256552049 # number of ReadReq hits
703system.cpu.dcache.WriteReq_hits::cpu.data 148160784 # number of WriteReq hits
704system.cpu.dcache.WriteReq_hits::total 148160784 # number of WriteReq hits
705system.cpu.dcache.demand_hits::cpu.data 404712833 # number of demand (read+write) hits
706system.cpu.dcache.demand_hits::total 404712833 # number of demand (read+write) hits
707system.cpu.dcache.overall_hits::cpu.data 404712833 # number of overall hits
708system.cpu.dcache.overall_hits::total 404712833 # number of overall hits
709system.cpu.dcache.ReadReq_misses::cpu.data 2890159 # number of ReadReq misses
710system.cpu.dcache.ReadReq_misses::total 2890159 # number of ReadReq misses
711system.cpu.dcache.WriteReq_misses::cpu.data 999418 # number of WriteReq misses
712system.cpu.dcache.WriteReq_misses::total 999418 # number of WriteReq misses
713system.cpu.dcache.demand_misses::cpu.data 3889577 # number of demand (read+write) misses
714system.cpu.dcache.demand_misses::total 3889577 # number of demand (read+write) misses
715system.cpu.dcache.overall_misses::cpu.data 3889577 # number of overall misses
716system.cpu.dcache.overall_misses::total 3889577 # number of overall misses
717system.cpu.dcache.ReadReq_miss_latency::cpu.data 51333969000 # number of ReadReq miss cycles
718system.cpu.dcache.ReadReq_miss_latency::total 51333969000 # number of ReadReq miss cycles
719system.cpu.dcache.WriteReq_miss_latency::cpu.data 23756626000 # number of WriteReq miss cycles
720system.cpu.dcache.WriteReq_miss_latency::total 23756626000 # number of WriteReq miss cycles
721system.cpu.dcache.demand_miss_latency::cpu.data 75090595000 # number of demand (read+write) miss cycles
722system.cpu.dcache.demand_miss_latency::total 75090595000 # number of demand (read+write) miss cycles
723system.cpu.dcache.overall_miss_latency::cpu.data 75090595000 # number of overall miss cycles
724system.cpu.dcache.overall_miss_latency::total 75090595000 # number of overall miss cycles
725system.cpu.dcache.ReadReq_accesses::cpu.data 259442208 # number of ReadReq accesses(hits+misses)
726system.cpu.dcache.ReadReq_accesses::total 259442208 # number of ReadReq accesses(hits+misses)

701system.cpu.dcache.ReadReq_hits::cpu.data 256575503 # number of ReadReq hits
702system.cpu.dcache.ReadReq_hits::total 256575503 # number of ReadReq hits
703system.cpu.dcache.WriteReq_hits::cpu.data 148160629 # number of WriteReq hits
704system.cpu.dcache.WriteReq_hits::total 148160629 # number of WriteReq hits
705system.cpu.dcache.demand_hits::cpu.data 404736132 # number of demand (read+write) hits
706system.cpu.dcache.demand_hits::total 404736132 # number of demand (read+write) hits
707system.cpu.dcache.overall_hits::cpu.data 404736132 # number of overall hits
708system.cpu.dcache.overall_hits::total 404736132 # number of overall hits
709system.cpu.dcache.ReadReq_misses::cpu.data 2890458 # number of ReadReq misses
710system.cpu.dcache.ReadReq_misses::total 2890458 # number of ReadReq misses
711system.cpu.dcache.WriteReq_misses::cpu.data 999573 # number of WriteReq misses
712system.cpu.dcache.WriteReq_misses::total 999573 # number of WriteReq misses
713system.cpu.dcache.demand_misses::cpu.data 3890031 # number of demand (read+write) misses
714system.cpu.dcache.demand_misses::total 3890031 # number of demand (read+write) misses
715system.cpu.dcache.overall_misses::cpu.data 3890031 # number of overall misses
716system.cpu.dcache.overall_misses::total 3890031 # number of overall misses
717system.cpu.dcache.ReadReq_miss_latency::cpu.data 51324442500 # number of ReadReq miss cycles
718system.cpu.dcache.ReadReq_miss_latency::total 51324442500 # number of ReadReq miss cycles
719system.cpu.dcache.WriteReq_miss_latency::cpu.data 23758155000 # number of WriteReq miss cycles
720system.cpu.dcache.WriteReq_miss_latency::total 23758155000 # number of WriteReq miss cycles
721system.cpu.dcache.demand_miss_latency::cpu.data 75082597500 # number of demand (read+write) miss cycles
722system.cpu.dcache.demand_miss_latency::total 75082597500 # number of demand (read+write) miss cycles
723system.cpu.dcache.overall_miss_latency::cpu.data 75082597500 # number of overall miss cycles
724system.cpu.dcache.overall_miss_latency::total 75082597500 # number of overall miss cycles
725system.cpu.dcache.ReadReq_accesses::cpu.data 259465961 # number of ReadReq accesses(hits+misses)
726system.cpu.dcache.ReadReq_accesses::total 259465961 # number of ReadReq accesses(hits+misses)

727system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
728system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)

729system.cpu.dcache.demand_accesses::cpu.data 408602410 # number of demand (read+write) accesses
730system.cpu.dcache.demand_accesses::total 408602410 # number of demand (read+write) accesses
731system.cpu.dcache.overall_accesses::cpu.data 408602410 # number of overall (read+write) accesses
732system.cpu.dcache.overall_accesses::total 408602410 # number of overall (read+write) accesses

729system.cpu.dcache.demand_accesses::cpu.data 408626163 # number of demand (read+write) accesses
730system.cpu.dcache.demand_accesses::total 408626163 # number of demand (read+write) accesses
731system.cpu.dcache.overall_accesses::cpu.data 408626163 # number of overall (read+write) accesses
732system.cpu.dcache.overall_accesses::total 408626163 # number of overall (read+write) accesses

733system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011140 # miss rate for ReadReq accesses
734system.cpu.dcache.ReadReq_miss_rate::total 0.011140 # miss rate for ReadReq accesses

735system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006700 # miss rate for WriteReq accesses
736system.cpu.dcache.WriteReq_miss_rate::total 0.006700 # miss rate for WriteReq accesses
737system.cpu.dcache.demand_miss_rate::cpu.data 0.009519 # miss rate for demand accesses
738system.cpu.dcache.demand_miss_rate::total 0.009519 # miss rate for demand accesses
739system.cpu.dcache.overall_miss_rate::cpu.data 0.009519 # miss rate for overall accesses
740system.cpu.dcache.overall_miss_rate::total 0.009519 # miss rate for overall accesses
741system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17761.641834 # average ReadReq miss latency
742system.cpu.dcache.ReadReq_avg_miss_latency::total 17761.641834 # average ReadReq miss latency
743system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23770.460408 # average WriteReq miss latency
744system.cpu.dcache.WriteReq_avg_miss_latency::total 23770.460408 # average WriteReq miss latency
745system.cpu.dcache.demand_avg_miss_latency::cpu.data 19305.594156 # average overall miss latency
746system.cpu.dcache.demand_avg_miss_latency::total 19305.594156 # average overall miss latency
747system.cpu.dcache.overall_avg_miss_latency::cpu.data 19305.594156 # average overall miss latency
748system.cpu.dcache.overall_avg_miss_latency::total 19305.594156 # average overall miss latency
749system.cpu.dcache.blocked_cycles::no_mshrs 6831 # number of cycles access was blocked

735system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006701 # miss rate for WriteReq accesses
736system.cpu.dcache.WriteReq_miss_rate::total 0.006701 # miss rate for WriteReq accesses
737system.cpu.dcache.demand_miss_rate::cpu.data 0.009520 # miss rate for demand accesses
738system.cpu.dcache.demand_miss_rate::total 0.009520 # miss rate for demand accesses
739system.cpu.dcache.overall_miss_rate::cpu.data 0.009520 # miss rate for overall accesses
740system.cpu.dcache.overall_miss_rate::total 0.009520 # miss rate for overall accesses
741system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17756.508657 # average ReadReq miss latency
742system.cpu.dcache.ReadReq_avg_miss_latency::total 17756.508657 # average ReadReq miss latency
743system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23768.304066 # average WriteReq miss latency
744system.cpu.dcache.WriteReq_avg_miss_latency::total 23768.304066 # average WriteReq miss latency
745system.cpu.dcache.demand_avg_miss_latency::cpu.data 19301.285131 # average overall miss latency
746system.cpu.dcache.demand_avg_miss_latency::total 19301.285131 # average overall miss latency
747system.cpu.dcache.overall_avg_miss_latency::cpu.data 19301.285131 # average overall miss latency
748system.cpu.dcache.overall_avg_miss_latency::total 19301.285131 # average overall miss latency
749system.cpu.dcache.blocked_cycles::no_mshrs 6798 # number of cycles access was blocked

750system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

751system.cpu.dcache.blocked::no_mshrs 659 # number of cycles access was blocked

751system.cpu.dcache.blocked::no_mshrs 655 # number of cycles access was blocked

752system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

753system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.365706 # average number of cycles each access was blocked

753system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.378626 # average number of cycles each access was blocked

754system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
755system.cpu.dcache.fast_writes 0 # number of fast writes performed
756system.cpu.dcache.cache_copies 0 # number of cache copies performed

757system.cpu.dcache.writebacks::writebacks 2331206 # number of writebacks
758system.cpu.dcache.writebacks::total 2331206 # number of writebacks
759system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127586 # number of ReadReq MSHR hits
760system.cpu.dcache.ReadReq_mshr_hits::total 1127586 # number of ReadReq MSHR hits
761system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16841 # number of WriteReq MSHR hits
762system.cpu.dcache.WriteReq_mshr_hits::total 16841 # number of WriteReq MSHR hits
763system.cpu.dcache.demand_mshr_hits::cpu.data 1144427 # number of demand (read+write) MSHR hits
764system.cpu.dcache.demand_mshr_hits::total 1144427 # number of demand (read+write) MSHR hits
765system.cpu.dcache.overall_mshr_hits::cpu.data 1144427 # number of overall MSHR hits
766system.cpu.dcache.overall_mshr_hits::total 1144427 # number of overall MSHR hits
767system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762573 # number of ReadReq MSHR misses
768system.cpu.dcache.ReadReq_mshr_misses::total 1762573 # number of ReadReq MSHR misses
769system.cpu.dcache.WriteReq_mshr_misses::cpu.data 982577 # number of WriteReq MSHR misses
770system.cpu.dcache.WriteReq_mshr_misses::total 982577 # number of WriteReq MSHR misses
771system.cpu.dcache.demand_mshr_misses::cpu.data 2745150 # number of demand (read+write) MSHR misses
772system.cpu.dcache.demand_mshr_misses::total 2745150 # number of demand (read+write) MSHR misses
773system.cpu.dcache.overall_mshr_misses::cpu.data 2745150 # number of overall MSHR misses
774system.cpu.dcache.overall_mshr_misses::total 2745150 # number of overall MSHR misses
775system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27778194500 # number of ReadReq MSHR miss cycles
776system.cpu.dcache.ReadReq_mshr_miss_latency::total 27778194500 # number of ReadReq MSHR miss cycles
777system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21591081000 # number of WriteReq MSHR miss cycles
778system.cpu.dcache.WriteReq_mshr_miss_latency::total 21591081000 # number of WriteReq MSHR miss cycles
779system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49369275500 # number of demand (read+write) MSHR miss cycles
780system.cpu.dcache.demand_mshr_miss_latency::total 49369275500 # number of demand (read+write) MSHR miss cycles
781system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49369275500 # number of overall MSHR miss cycles
782system.cpu.dcache.overall_mshr_miss_latency::total 49369275500 # number of overall MSHR miss cycles
783system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses
784system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses
785system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006587 # mshr miss rate for WriteReq accesses
786system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006587 # mshr miss rate for WriteReq accesses

757system.cpu.dcache.writebacks::writebacks 2331126 # number of writebacks
758system.cpu.dcache.writebacks::total 2331126 # number of writebacks
759system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127945 # number of ReadReq MSHR hits
760system.cpu.dcache.ReadReq_mshr_hits::total 1127945 # number of ReadReq MSHR hits
761system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16844 # number of WriteReq MSHR hits
762system.cpu.dcache.WriteReq_mshr_hits::total 16844 # number of WriteReq MSHR hits
763system.cpu.dcache.demand_mshr_hits::cpu.data 1144789 # number of demand (read+write) MSHR hits
764system.cpu.dcache.demand_mshr_hits::total 1144789 # number of demand (read+write) MSHR hits
765system.cpu.dcache.overall_mshr_hits::cpu.data 1144789 # number of overall MSHR hits
766system.cpu.dcache.overall_mshr_hits::total 1144789 # number of overall MSHR hits
767system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762513 # number of ReadReq MSHR misses
768system.cpu.dcache.ReadReq_mshr_misses::total 1762513 # number of ReadReq MSHR misses
769system.cpu.dcache.WriteReq_mshr_misses::cpu.data 982729 # number of WriteReq MSHR misses
770system.cpu.dcache.WriteReq_mshr_misses::total 982729 # number of WriteReq MSHR misses
771system.cpu.dcache.demand_mshr_misses::cpu.data 2745242 # number of demand (read+write) MSHR misses
772system.cpu.dcache.demand_mshr_misses::total 2745242 # number of demand (read+write) MSHR misses
773system.cpu.dcache.overall_mshr_misses::cpu.data 2745242 # number of overall MSHR misses
774system.cpu.dcache.overall_mshr_misses::total 2745242 # number of overall MSHR misses
775system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27781259000 # number of ReadReq MSHR miss cycles
776system.cpu.dcache.ReadReq_mshr_miss_latency::total 27781259000 # number of ReadReq MSHR miss cycles
777system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21592303500 # number of WriteReq MSHR miss cycles
778system.cpu.dcache.WriteReq_mshr_miss_latency::total 21592303500 # number of WriteReq MSHR miss cycles
779system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49373562500 # number of demand (read+write) MSHR miss cycles
780system.cpu.dcache.demand_mshr_miss_latency::total 49373562500 # number of demand (read+write) MSHR miss cycles
781system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49373562500 # number of overall MSHR miss cycles
782system.cpu.dcache.overall_mshr_miss_latency::total 49373562500 # number of overall MSHR miss cycles
783system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses
784system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses
785system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006588 # mshr miss rate for WriteReq accesses
786system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006588 # mshr miss rate for WriteReq accesses

787system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for demand accesses
788system.cpu.dcache.demand_mshr_miss_rate::total 0.006718 # mshr miss rate for demand accesses
789system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for overall accesses
790system.cpu.dcache.overall_mshr_miss_rate::total 0.006718 # mshr miss rate for overall accesses

791system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15760.024975 # average ReadReq mshr miss latency
792system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15760.024975 # average ReadReq mshr miss latency
793system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21973.932832 # average WriteReq mshr miss latency
794system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21973.932832 # average WriteReq mshr miss latency
795system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency
796system.cpu.dcache.demand_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency
797system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency
798system.cpu.dcache.overall_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency

791system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15762.300193 # average ReadReq mshr miss latency
792system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15762.300193 # average ReadReq mshr miss latency
793system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21971.778079 # average WriteReq mshr miss latency
794system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21971.778079 # average WriteReq mshr miss latency
795system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17985.140290 # average overall mshr miss latency
796system.cpu.dcache.demand_avg_mshr_miss_latency::total 17985.140290 # average overall mshr miss latency
797system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17985.140290 # average overall mshr miss latency
798system.cpu.dcache.overall_avg_mshr_miss_latency::total 17985.140290 # average overall mshr miss latency