| stats.txt (9490:e6a09d97bdc9) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.434532 # Number of seconds simulated 4sim_ticks 434531908500 # Number of ticks simulated 5final_tick 434531908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.434431 # Number of seconds simulated 4sim_ticks 434430920500 # Number of ticks simulated 5final_tick 434430920500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 91853 # Simulator instruction rate (inst/s) 8host_op_rate 169847 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48269802 # Simulator tick rate (ticks/s) 10host_mem_usage 425632 # Number of bytes of host memory used 11host_seconds 9002.15 # Real time elapsed on the host | 7host_inst_rate 103951 # Simulator instruction rate (inst/s) 8host_op_rate 192218 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54614710 # Simulator tick rate (ticks/s) 10host_mem_usage 421552 # Number of bytes of host memory used 11host_seconds 7954.47 # Real time elapsed on the host |
| 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988700 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory | 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988700 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 24475072 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24681728 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 24473856 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24680512 # Number of bytes read from this memory |
| 17system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory | 17system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory |
| 19system.physmem.bytes_written::writebacks 18793472 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18793472 # Number of bytes written to this memory | 19system.physmem.bytes_written::writebacks 18792192 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18792192 # Number of bytes written to this memory |
| 21system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory | 21system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory |
| 22system.physmem.num_reads::cpu.data 382423 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385652 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293648 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293648 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 475583 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 56325143 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 56800726 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 475583 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 475583 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 43249924 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 43249924 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 43249924 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 475583 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 56325143 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 100050650 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385654 # Total number of read requests seen 38system.physmem.writeReqs 293648 # Total number of write requests seen 39system.physmem.cpureqs 897087 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 24681728 # Total number of bytes read from memory 41system.physmem.bytesWritten 18793472 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 24681728 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 18793472 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 151 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 214401 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 23129 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 24463 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 23958 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 22626 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 23437 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 24746 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 24520 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 24217 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 24346 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 24649 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 24306 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 24351 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 23427 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 24871 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 23990 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 17780 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 18806 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 18330 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 17563 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 18009 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 18654 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 18307 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 18738 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 18746 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 18443 # Track writes on a per bank basis | 22system.physmem.num_reads::cpu.data 382404 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385633 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293628 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293628 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 475694 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 56335438 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 56811131 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 475694 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 475694 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 43257031 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 43257031 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 43257031 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 475694 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 56335438 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 100068163 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385635 # Total number of read requests seen 38system.physmem.writeReqs 293628 # Total number of write requests seen 39system.physmem.cpureqs 897306 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 24680512 # Total number of bytes read from memory 41system.physmem.bytesWritten 18792192 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 24680512 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 18792192 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 215167 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 23200 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 24440 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 23926 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 22603 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 23455 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 24726 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 24470 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 24228 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 24367 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 24672 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 24294 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 24362 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 24487 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 23459 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 24852 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 23959 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 17796 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 18805 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 18324 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 17566 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 18653 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 18315 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 18311 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 18728 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 18743 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 18429 # Track writes on a per bank basis |
| 73system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis | 73system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis |
| 74system.physmem.perBankWrReqs::12 18554 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 17877 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 18850 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 18109 # Track writes on a per bank basis | 74system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 17863 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 18856 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 18104 # Track writes on a per bank basis |
| 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 79system.physmem.numWrRetry 3384 # Number of times wr buffer was full causing retry 80system.physmem.totGap 434531891500 # Total gap between requests | 79system.physmem.numWrRetry 2876 # Number of times wr buffer was full causing retry 80system.physmem.totGap 434430903500 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 385654 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 297032 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 214401 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 380704 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 4364 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see | 87system.physmem.readPktSize::6 385635 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 293628 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 380797 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 4262 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 378 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see |
| 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 12721 # What write queue length does an incoming req see | 127system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 12719 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 12720 # What write queue length does an incoming req see |
| 144system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see | 130system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see |
| 145system.physmem.wrQLenPdf::4 12726 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 12730 # What write queue length does an incoming req see | 131system.physmem.wrQLenPdf::4 12725 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 12729 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see | 133system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 12737 # What write queue length does an incoming req see | 134system.physmem.wrQLenPdf::7 12739 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 12741 # What write queue length does an incoming req see |
| 150system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see | 136system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::10 12767 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 62 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see | 137system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 48 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see |
| 167system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see | 153system.physmem.wrQLenPdf::26 45 # What write queue length does an incoming req see |
| 168system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see |
| 170system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 30 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 3414434563 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 12002683313 # Sum of mem lat for all requests 176system.physmem.totBusLat 1927515000 # Total cycles spent in databus access 177system.physmem.totBankLat 6660733750 # Total cycles spent in bank access 178system.physmem.avgQLat 8857.09 # Average queueing delay per request 179system.physmem.avgBankLat 17278.03 # Average bank access latency per request | 156system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 28 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see 159system.physmem.totQLat 3409479750 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 11997177250 # Sum of mem lat for all requests 161system.physmem.totBusLat 1927500000 # Total cycles spent in databus access 162system.physmem.totBankLat 6660197500 # Total cycles spent in bank access 163system.physmem.avgQLat 8844.31 # Average queueing delay per request 164system.physmem.avgBankLat 17276.78 # Average bank access latency per request |
| 180system.physmem.avgBusLat 5000.00 # Average bus latency per request | 165system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 181system.physmem.avgMemAccLat 31135.12 # Average memory access latency 182system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s | 166system.physmem.avgMemAccLat 31121.08 # Average memory access latency 167system.physmem.avgRdBW 56.81 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 56.81 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s |
| 186system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.78 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.03 # Average read queue length over time | 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 172system.physmem.busUtil 0.78 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.03 # Average read queue length over time |
| 189system.physmem.avgWrQLen 9.81 # Average write queue length over time 190system.physmem.readRowHits 331850 # Number of row buffer hits during reads 191system.physmem.writeRowHits 191739 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 86.08 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 65.30 # Row buffer hit rate for writes 194system.physmem.avgGap 639674.09 # Average gap between requests 195system.cpu.branchPred.lookups 214985170 # Number of BP lookups 196system.cpu.branchPred.condPredicted 214985170 # Number of conditional branches predicted 197system.cpu.branchPred.condIncorrect 13134974 # Number of conditional branches incorrect 198system.cpu.branchPred.BTBLookups 150557498 # Number of BTB lookups 199system.cpu.branchPred.BTBHits 147831953 # Number of BTB hits | 174system.physmem.avgWrQLen 9.17 # Average write queue length over time 175system.physmem.readRowHits 331860 # Number of row buffer hits during reads 176system.physmem.writeRowHits 191798 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes 179system.physmem.avgGap 639562.15 # Average gap between requests 180system.cpu.branchPred.lookups 214905339 # Number of BP lookups 181system.cpu.branchPred.condPredicted 214905339 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 13127433 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 150477516 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 147823689 # Number of BTB hits |
| 200system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 201system.cpu.branchPred.BTBHitPct 98.189698 # BTB Hit Percentage | 186system.cpu.branchPred.BTBHitPct 98.236396 # BTB Hit Percentage |
| 202system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 203system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 204system.cpu.workload.num_syscalls 551 # Number of system calls | 187system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 189system.cpu.workload.num_syscalls 551 # Number of system calls |
| 205system.cpu.numCycles 869063818 # number of cpu cycles simulated | 190system.cpu.numCycles 868861842 # number of cpu cycles simulated |
| 206system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 207system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 191system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 192system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 208system.cpu.fetch.icacheStallCycles 180571756 # Number of cycles fetch is stalled on an Icache miss 209system.cpu.fetch.Insts 1193203975 # Number of instructions fetch has processed 210system.cpu.fetch.Branches 214985170 # Number of branches that fetch encountered 211system.cpu.fetch.predictedBranches 147831953 # Number of branches that fetch has predicted taken 212system.cpu.fetch.Cycles 371215101 # Number of cycles fetch has run and was not squashing or blocked 213system.cpu.fetch.SquashCycles 83387755 # Number of cycles fetch has spent squashing 214system.cpu.fetch.BlockedCycles 231673075 # Number of cycles fetch has spent blocked 215system.cpu.fetch.MiscStallCycles 33185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 216system.cpu.fetch.PendingTrapStallCycles 322843 # Number of stall cycles due to pending traps 217system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR 218system.cpu.fetch.CacheLines 173439567 # Number of cache lines fetched 219system.cpu.fetch.IcacheSquashes 3823649 # Number of outstanding Icache misses that were squashed 220system.cpu.fetch.rateDist::samples 853812868 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::mean 2.595051 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::stdev 3.389323 # Number of instructions fetched each cycle (Total) | 193system.cpu.fetch.icacheStallCycles 180577504 # Number of cycles fetch is stalled on an Icache miss 194system.cpu.fetch.Insts 1192973241 # Number of instructions fetch has processed 195system.cpu.fetch.Branches 214905339 # Number of branches that fetch encountered 196system.cpu.fetch.predictedBranches 147823689 # Number of branches that fetch has predicted taken 197system.cpu.fetch.Cycles 371150852 # Number of cycles fetch has run and was not squashing or blocked 198system.cpu.fetch.SquashCycles 83341611 # Number of cycles fetch has spent squashing 199system.cpu.fetch.BlockedCycles 231393952 # Number of cycles fetch has spent blocked 200system.cpu.fetch.MiscStallCycles 33171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 201system.cpu.fetch.PendingTrapStallCycles 324598 # Number of stall cycles due to pending traps 202system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR 203system.cpu.fetch.CacheLines 173446874 # Number of cache lines fetched 204system.cpu.fetch.IcacheSquashes 3818726 # Number of outstanding Icache misses that were squashed 205system.cpu.fetch.rateDist::samples 853436670 # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::mean 2.595518 # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::stdev 3.389389 # Number of instructions fetched each cycle (Total) |
| 223system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 208system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 224system.cpu.fetch.rateDist::0 486992667 57.04% 57.04% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::1 24704335 2.89% 59.93% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::2 27327411 3.20% 63.13% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::3 28832283 3.38% 66.51% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::4 18475468 2.16% 68.67% # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::5 24603692 2.88% 71.55% # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::6 30623589 3.59% 75.14% # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::7 28857730 3.38% 78.52% # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::8 183395693 21.48% 100.00% # Number of instructions fetched each cycle (Total) | 209system.cpu.fetch.rateDist::0 486691437 57.03% 57.03% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::1 24707790 2.90% 59.92% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::2 27346098 3.20% 63.13% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::3 28808795 3.38% 66.50% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::4 18459850 2.16% 68.67% # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::5 24598509 2.88% 71.55% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::6 30642263 3.59% 75.14% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::7 28856964 3.38% 78.52% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::8 183324964 21.48% 100.00% # Number of instructions fetched each cycle (Total) |
| 233system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 218system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 236system.cpu.fetch.rateDist::total 853812868 # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.branchRate 0.247376 # Number of branch fetches per cycle 238system.cpu.fetch.rate 1.372976 # Number of inst fetches per cycle 239system.cpu.decode.IdleCycles 237064473 # Number of cycles decode is idle 240system.cpu.decode.BlockedCycles 188186572 # Number of cycles decode is blocked 241system.cpu.decode.RunCycles 313399146 # Number of cycles decode is running 242system.cpu.decode.UnblockCycles 45165837 # Number of cycles decode is unblocking 243system.cpu.decode.SquashCycles 69996840 # Number of cycles decode is squashing 244system.cpu.decode.DecodedInsts 2166788008 # Number of instructions handled by decode 245system.cpu.rename.SquashCycles 69996840 # Number of cycles rename is squashing 246system.cpu.rename.IdleCycles 270473923 # Number of cycles rename is idle 247system.cpu.rename.BlockCycles 53975472 # Number of cycles rename is blocking 248system.cpu.rename.serializeStallCycles 17892 # count of cycles rename stalled for serializing inst 249system.cpu.rename.RunCycles 322682449 # Number of cycles rename is running 250system.cpu.rename.UnblockCycles 136666292 # Number of cycles rename is unblocking 251system.cpu.rename.RenamedInsts 2119871980 # Number of instructions processed by rename 252system.cpu.rename.ROBFullEvents 32012 # Number of times rename has blocked due to ROB full 253system.cpu.rename.IQFullEvents 21236600 # Number of times rename has blocked due to IQ full 254system.cpu.rename.LSQFullEvents 101165935 # Number of times rename has blocked due to LSQ full 255system.cpu.rename.FullRegisterEvents 102 # Number of times there has been no free registers 256system.cpu.rename.RenamedOperands 2216234467 # Number of destination operands rename has renamed 257system.cpu.rename.RenameLookups 5355317387 # Number of register rename lookups that rename has made 258system.cpu.rename.int_rename_lookups 5355179179 # Number of integer rename lookups 259system.cpu.rename.fp_rename_lookups 138208 # Number of floating rename lookups | 221system.cpu.fetch.rateDist::total 853436670 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.branchRate 0.247341 # Number of branch fetches per cycle 223system.cpu.fetch.rate 1.373030 # Number of inst fetches per cycle 224system.cpu.decode.IdleCycles 237036597 # Number of cycles decode is idle 225system.cpu.decode.BlockedCycles 187932241 # Number of cycles decode is blocked 226system.cpu.decode.RunCycles 313348177 # Number of cycles decode is running 227system.cpu.decode.UnblockCycles 45163149 # Number of cycles decode is unblocking 228system.cpu.decode.SquashCycles 69956506 # Number of cycles decode is squashing 229system.cpu.decode.DecodedInsts 2166370172 # Number of instructions handled by decode 230system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode 231system.cpu.rename.SquashCycles 69956506 # Number of cycles rename is squashing 232system.cpu.rename.IdleCycles 270406129 # Number of cycles rename is idle 233system.cpu.rename.BlockCycles 53950609 # Number of cycles rename is blocking 234system.cpu.rename.serializeStallCycles 16000 # count of cycles rename stalled for serializing inst 235system.cpu.rename.RunCycles 322641702 # Number of cycles rename is running 236system.cpu.rename.UnblockCycles 136465724 # Number of cycles rename is unblocking 237system.cpu.rename.RenamedInsts 2119600897 # Number of instructions processed by rename 238system.cpu.rename.ROBFullEvents 32452 # Number of times rename has blocked due to ROB full 239system.cpu.rename.IQFullEvents 20939189 # Number of times rename has blocked due to IQ full 240system.cpu.rename.LSQFullEvents 101244294 # Number of times rename has blocked due to LSQ full 241system.cpu.rename.FullRegisterEvents 109 # Number of times there has been no free registers 242system.cpu.rename.RenamedOperands 2216054849 # Number of destination operands rename has renamed 243system.cpu.rename.RenameLookups 5354933162 # Number of register rename lookups that rename has made 244system.cpu.rename.int_rename_lookups 5354796739 # Number of integer rename lookups 245system.cpu.rename.fp_rename_lookups 136423 # Number of floating rename lookups |
| 260system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed | 246system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed |
| 261system.cpu.rename.UndoneMaps 602193615 # Number of HB maps that are undone due to squashing 262system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed 263system.cpu.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed 264system.cpu.rename.skidInsts 330022122 # count of insts added to the skid buffer 265system.cpu.memDep0.insertedLoads 512693840 # Number of loads inserted to the mem dependence unit. 266system.cpu.memDep0.insertedStores 204894369 # Number of stores inserted to the mem dependence unit. 267system.cpu.memDep0.conflictingLoads 196280742 # Number of conflicting loads. 268system.cpu.memDep0.conflictingStores 55580246 # Number of conflicting stores. 269system.cpu.iq.iqInstsAdded 2033860002 # Number of instructions added to the IQ (excludes non-spec) 270system.cpu.iq.iqNonSpecInstsAdded 23240 # Number of non-speculative instructions added to the IQ 271system.cpu.iq.iqInstsIssued 1808188122 # Number of instructions issued 272system.cpu.iq.iqSquashedInstsIssued 845695 # Number of squashed instructions issued 273system.cpu.iq.iqSquashedInstsExamined 499369913 # Number of squashed instructions iterated over during squash; mainly for profiling 274system.cpu.iq.iqSquashedOperandsExamined 817987835 # Number of squashed operands that are examined and possibly removed from graph 275system.cpu.iq.iqSquashedNonSpecRemoved 22688 # Number of squashed non-spec instructions that were removed 276system.cpu.iq.issued_per_cycle::samples 853812868 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::mean 2.117780 # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::stdev 1.887735 # Number of insts issued each cycle | 247system.cpu.rename.UndoneMaps 602013997 # Number of HB maps that are undone due to squashing 248system.cpu.rename.serializingInsts 1381 # count of serializing insts renamed 249system.cpu.rename.tempSerializingInsts 1341 # count of temporary serializing insts renamed 250system.cpu.rename.skidInsts 329887917 # count of insts added to the skid buffer 251system.cpu.memDep0.insertedLoads 512569621 # Number of loads inserted to the mem dependence unit. 252system.cpu.memDep0.insertedStores 204871608 # Number of stores inserted to the mem dependence unit. 253system.cpu.memDep0.conflictingLoads 196009794 # Number of conflicting loads. 254system.cpu.memDep0.conflictingStores 55366102 # Number of conflicting stores. 255system.cpu.iq.iqInstsAdded 2033547368 # Number of instructions added to the IQ (excludes non-spec) 256system.cpu.iq.iqNonSpecInstsAdded 23672 # Number of non-speculative instructions added to the IQ 257system.cpu.iq.iqInstsIssued 1807958991 # Number of instructions issued 258system.cpu.iq.iqSquashedInstsIssued 824800 # Number of squashed instructions issued 259system.cpu.iq.iqSquashedInstsExamined 499056334 # Number of squashed instructions iterated over during squash; mainly for profiling 260system.cpu.iq.iqSquashedOperandsExamined 817700270 # Number of squashed operands that are examined and possibly removed from graph 261system.cpu.iq.iqSquashedNonSpecRemoved 23120 # Number of squashed non-spec instructions that were removed 262system.cpu.iq.issued_per_cycle::samples 853436670 # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::mean 2.118445 # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::stdev 1.887633 # Number of insts issued each cycle |
| 279system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 265system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 280system.cpu.iq.issued_per_cycle::0 233534658 27.35% 27.35% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::1 145245329 17.01% 44.36% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::2 138299025 16.20% 60.56% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::3 133036648 15.58% 76.14% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::4 95993641 11.24% 87.39% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::5 58825628 6.89% 94.28% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::6 34908775 4.09% 98.36% # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::7 12073867 1.41% 99.78% # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::8 1895297 0.22% 100.00% # Number of insts issued each cycle | 266system.cpu.iq.issued_per_cycle::0 233342895 27.34% 27.34% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::1 145008680 16.99% 44.33% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::2 138353825 16.21% 60.54% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::3 133057886 15.59% 76.13% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::4 96025914 11.25% 87.39% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::5 58740201 6.88% 94.27% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::6 34984970 4.10% 98.37% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::7 12023870 1.41% 99.78% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::8 1898429 0.22% 100.00% # Number of insts issued each cycle |
| 289system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 275system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 292system.cpu.iq.issued_per_cycle::total 853812868 # Number of insts issued each cycle | 278system.cpu.iq.issued_per_cycle::total 853436670 # Number of insts issued each cycle |
| 293system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 279system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 294system.cpu.iq.fu_full::IntAlu 4968961 32.44% 32.44% # attempts to use FU when none available 295system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available 296system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available 299system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available 300system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available 301system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available 302system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available 323system.cpu.iq.fu_full::MemRead 7761394 50.67% 83.11% # attempts to use FU when none available 324system.cpu.iq.fu_full::MemWrite 2587769 16.89% 100.00% # attempts to use FU when none available | 280system.cpu.iq.fu_full::IntAlu 4945296 32.31% 32.31% # attempts to use FU when none available 281system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available 282system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available 287system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available 288system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available 309system.cpu.iq.fu_full::MemRead 7774785 50.79% 83.10% # attempts to use FU when none available 310system.cpu.iq.fu_full::MemWrite 2587375 16.90% 100.00% # attempts to use FU when none available |
| 325system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 326system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 311system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 312system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 327system.cpu.iq.FU_type_0::No_OpClass 2719358 0.15% 0.15% # Type of FU issued 328system.cpu.iq.FU_type_0::IntAlu 1190817504 65.86% 66.01% # Type of FU issued | 313system.cpu.iq.FU_type_0::No_OpClass 2719757 0.15% 0.15% # Type of FU issued 314system.cpu.iq.FU_type_0::IntAlu 1190688442 65.86% 66.01% # Type of FU issued |
| 329system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued 330system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued 333system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued 334system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued 335system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued 336system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 349system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued 356system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued | 315system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued 316system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued 321system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 335system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued |
| 357system.cpu.iq.FU_type_0::MemRead 438925166 24.27% 90.28% # Type of FU issued 358system.cpu.iq.FU_type_0::MemWrite 175726094 9.72% 100.00% # Type of FU issued | 343system.cpu.iq.FU_type_0::MemRead 438864121 24.27% 90.28% # Type of FU issued 344system.cpu.iq.FU_type_0::MemWrite 175686671 9.72% 100.00% # Type of FU issued |
| 359system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 360system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 345system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 346system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 361system.cpu.iq.FU_type_0::total 1808188122 # Type of FU issued 362system.cpu.iq.rate 2.080616 # Inst issue rate 363system.cpu.iq.fu_busy_cnt 15318124 # FU busy when requested 364system.cpu.iq.fu_busy_rate 0.008472 # FU busy rate (busy events/executed inst) 365system.cpu.iq.int_inst_queue_reads 4486330411 # Number of integer instruction queue reads 366system.cpu.iq.int_inst_queue_writes 2533466617 # Number of integer instruction queue writes 367system.cpu.iq.int_inst_queue_wakeup_accesses 1768665835 # Number of integer instruction queue wakeup accesses 368system.cpu.iq.fp_inst_queue_reads 22520 # Number of floating instruction queue reads 369system.cpu.iq.fp_inst_queue_writes 43644 # Number of floating instruction queue writes 370system.cpu.iq.fp_inst_queue_wakeup_accesses 4990 # Number of floating instruction queue wakeup accesses 371system.cpu.iq.int_alu_accesses 1820776414 # Number of integer alu accesses 372system.cpu.iq.fp_alu_accesses 10474 # Number of floating point alu accesses 373system.cpu.iew.lsq.thread0.forwLoads 170620885 # Number of loads that had data forwarded from stores | 347system.cpu.iq.FU_type_0::total 1807958991 # Type of FU issued 348system.cpu.iq.rate 2.080836 # Inst issue rate 349system.cpu.iq.fu_busy_cnt 15307456 # FU busy when requested 350system.cpu.iq.fu_busy_rate 0.008467 # FU busy rate (busy events/executed inst) 351system.cpu.iq.int_inst_queue_reads 4485463564 # Number of integer instruction queue reads 352system.cpu.iq.int_inst_queue_writes 2532842226 # Number of integer instruction queue writes 353system.cpu.iq.int_inst_queue_wakeup_accesses 1768511816 # Number of integer instruction queue wakeup accesses 354system.cpu.iq.fp_inst_queue_reads 23344 # Number of floating instruction queue reads 355system.cpu.iq.fp_inst_queue_writes 44056 # Number of floating instruction queue writes 356system.cpu.iq.fp_inst_queue_wakeup_accesses 5298 # Number of floating instruction queue wakeup accesses 357system.cpu.iq.int_alu_accesses 1820535825 # Number of integer alu accesses 358system.cpu.iq.fp_alu_accesses 10865 # Number of floating point alu accesses 359system.cpu.iew.lsq.thread0.forwLoads 170531860 # Number of loads that had data forwarded from stores |
| 374system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 360system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 375system.cpu.iew.lsq.thread0.squashedLoads 128591684 # Number of loads squashed 376system.cpu.iew.lsq.thread0.ignoredResponses 469733 # Number of memory responses ignored because the instruction is squashed 377system.cpu.iew.lsq.thread0.memOrderViolation 268884 # Number of memory ordering violations 378system.cpu.iew.lsq.thread0.squashedStores 55734548 # Number of stores squashed | 361system.cpu.iew.lsq.thread0.squashedLoads 128467465 # Number of loads squashed 362system.cpu.iew.lsq.thread0.ignoredResponses 477996 # Number of memory responses ignored because the instruction is squashed 363system.cpu.iew.lsq.thread0.memOrderViolation 270600 # Number of memory ordering violations 364system.cpu.iew.lsq.thread0.squashedStores 55711763 # Number of stores squashed |
| 379system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 380system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 365system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 366system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 381system.cpu.iew.lsq.thread0.rescheduledLoads 12443 # Number of loads that were rescheduled 382system.cpu.iew.lsq.thread0.cacheBlocked 683 # Number of times an access to memory failed due to the cache being blocked | 367system.cpu.iew.lsq.thread0.rescheduledLoads 12158 # Number of loads that were rescheduled 368system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked |
| 383system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 369system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 384system.cpu.iew.iewSquashCycles 69996840 # Number of cycles IEW is squashing 385system.cpu.iew.iewBlockCycles 16364844 # Number of cycles IEW is blocking 386system.cpu.iew.iewUnblockCycles 2884009 # Number of cycles IEW is unblocking 387system.cpu.iew.iewDispatchedInsts 2033883242 # Number of instructions dispatched to IQ 388system.cpu.iew.iewDispSquashedInsts 2403682 # Number of squashed instructions skipped by dispatch 389system.cpu.iew.iewDispLoadInsts 512693840 # Number of dispatched load instructions 390system.cpu.iew.iewDispStoreInsts 204894734 # Number of dispatched store instructions 391system.cpu.iew.iewDispNonSpecInsts 6182 # Number of dispatched non-speculative instructions 392system.cpu.iew.iewIQFullEvents 1820537 # Number of times the IQ has become full, causing a stall 393system.cpu.iew.iewLSQFullEvents 77063 # Number of times the LSQ has become full, causing a stall 394system.cpu.iew.memOrderViolationEvents 268884 # Number of memory order violations 395system.cpu.iew.predictedTakenIncorrect 9113160 # Number of branches that were predicted taken incorrectly 396system.cpu.iew.predictedNotTakenIncorrect 4488782 # Number of branches that were predicted not taken incorrectly 397system.cpu.iew.branchMispredicts 13601942 # Number of branch mispredicts detected at execute 398system.cpu.iew.iewExecutedInsts 1780436006 # Number of executed instructions 399system.cpu.iew.iewExecLoadInsts 431388742 # Number of load instructions executed 400system.cpu.iew.iewExecSquashedInsts 27752116 # Number of squashed instructions skipped in execute | 370system.cpu.iew.iewSquashCycles 69956506 # Number of cycles IEW is squashing 371system.cpu.iew.iewBlockCycles 16270481 # Number of cycles IEW is blocking 372system.cpu.iew.iewUnblockCycles 2882420 # Number of cycles IEW is unblocking 373system.cpu.iew.iewDispatchedInsts 2033571040 # Number of instructions dispatched to IQ 374system.cpu.iew.iewDispSquashedInsts 2388116 # Number of squashed instructions skipped by dispatch 375system.cpu.iew.iewDispLoadInsts 512569621 # Number of dispatched load instructions 376system.cpu.iew.iewDispStoreInsts 204871949 # Number of dispatched store instructions 377system.cpu.iew.iewDispNonSpecInsts 6204 # Number of dispatched non-speculative instructions 378system.cpu.iew.iewIQFullEvents 1819124 # Number of times the IQ has become full, causing a stall 379system.cpu.iew.iewLSQFullEvents 76761 # Number of times the LSQ has become full, causing a stall 380system.cpu.iew.memOrderViolationEvents 270600 # Number of memory order violations 381system.cpu.iew.predictedTakenIncorrect 9107192 # Number of branches that were predicted taken incorrectly 382system.cpu.iew.predictedNotTakenIncorrect 4485988 # Number of branches that were predicted not taken incorrectly 383system.cpu.iew.branchMispredicts 13593180 # Number of branch mispredicts detected at execute 384system.cpu.iew.iewExecutedInsts 1780284053 # Number of executed instructions 385system.cpu.iew.iewExecLoadInsts 431339374 # Number of load instructions executed 386system.cpu.iew.iewExecSquashedInsts 27674938 # Number of squashed instructions skipped in execute |
| 401system.cpu.iew.exec_swp 0 # number of swp insts executed 402system.cpu.iew.exec_nop 0 # number of nop insts executed | 387system.cpu.iew.exec_swp 0 # number of swp insts executed 388system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 403system.cpu.iew.exec_refs 602101798 # number of memory reference insts executed 404system.cpu.iew.exec_branches 169273677 # Number of branches executed 405system.cpu.iew.exec_stores 170713056 # Number of stores executed 406system.cpu.iew.exec_rate 2.048683 # Inst execution rate 407system.cpu.iew.wb_sent 1775376016 # cumulative count of insts sent to commit 408system.cpu.iew.wb_count 1768670825 # cumulative count of insts written-back 409system.cpu.iew.wb_producers 1341566013 # num instructions producing a value 410system.cpu.iew.wb_consumers 1964312147 # num instructions consuming a value | 389system.cpu.iew.exec_refs 602039294 # number of memory reference insts executed 390system.cpu.iew.exec_branches 169246967 # Number of branches executed 391system.cpu.iew.exec_stores 170699920 # Number of stores executed 392system.cpu.iew.exec_rate 2.048984 # Inst execution rate 393system.cpu.iew.wb_sent 1775206038 # cumulative count of insts sent to commit 394system.cpu.iew.wb_count 1768517114 # cumulative count of insts written-back 395system.cpu.iew.wb_producers 1341481369 # num instructions producing a value 396system.cpu.iew.wb_consumers 1964281102 # num instructions consuming a value |
| 411system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 397system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 412system.cpu.iew.wb_rate 2.035145 # insts written-back per cycle 413system.cpu.iew.wb_fanout 0.682970 # average fanout of values written-back | 398system.cpu.iew.wb_rate 2.035441 # insts written-back per cycle 399system.cpu.iew.wb_fanout 0.682938 # average fanout of values written-back |
| 414system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 400system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 415system.cpu.commit.commitSquashedInsts 504930562 # The number of squashed insts skipped by commit | 401system.cpu.commit.commitSquashedInsts 504616245 # The number of squashed insts skipped by commit |
| 416system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 402system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 417system.cpu.commit.branchMispredicts 13167809 # The number of times a branch was mispredicted 418system.cpu.commit.committed_per_cycle::samples 783816028 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::mean 1.950698 # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::stdev 2.458733 # Number of insts commited each cycle | 403system.cpu.commit.branchMispredicts 13160386 # The number of times a branch was mispredicted 404system.cpu.commit.committed_per_cycle::samples 783480164 # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::mean 1.951535 # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::stdev 2.459630 # Number of insts commited each cycle |
| 421system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 407system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 422system.cpu.commit.committed_per_cycle::0 290605318 37.08% 37.08% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::1 195507197 24.94% 62.02% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::2 61957017 7.90% 69.92% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::3 92299201 11.78% 81.70% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::4 25131164 3.21% 84.91% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::5 28287004 3.61% 88.51% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::6 9364104 1.19% 89.71% # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::7 10794618 1.38% 91.09% # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::8 69870405 8.91% 100.00% # Number of insts commited each cycle | 408system.cpu.commit.committed_per_cycle::0 290390176 37.06% 37.06% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::1 195527314 24.96% 62.02% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::2 61904118 7.90% 69.92% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::3 92200524 11.77% 81.69% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::4 25009746 3.19% 84.88% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::5 28276907 3.61% 88.49% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::6 9452853 1.21% 89.70% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::7 10837267 1.38% 91.08% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::8 69881259 8.92% 100.00% # Number of insts commited each cycle |
| 431system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 417system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 434system.cpu.commit.committed_per_cycle::total 783816028 # Number of insts commited each cycle | 420system.cpu.commit.committed_per_cycle::total 783480164 # Number of insts commited each cycle |
| 435system.cpu.commit.committedInsts 826877109 # Number of instructions committed 436system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed 437system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 438system.cpu.commit.refs 533262342 # Number of memory references committed 439system.cpu.commit.loads 384102156 # Number of loads committed 440system.cpu.commit.membars 0 # Number of memory barriers committed 441system.cpu.commit.branches 149758583 # Number of branches committed 442system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 443system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. 444system.cpu.commit.function_calls 0 # Number of function calls committed. | 421system.cpu.commit.committedInsts 826877109 # Number of instructions committed 422system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed 423system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 424system.cpu.commit.refs 533262342 # Number of memory references committed 425system.cpu.commit.loads 384102156 # Number of loads committed 426system.cpu.commit.membars 0 # Number of memory barriers committed 427system.cpu.commit.branches 149758583 # Number of branches committed 428system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 429system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. 430system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 445system.cpu.commit.bw_lim_events 69870405 # number cycles where commit BW limit reached | 431system.cpu.commit.bw_lim_events 69881259 # number cycles where commit BW limit reached |
| 446system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 432system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 447system.cpu.rob.rob_reads 2747864885 # The number of ROB reads 448system.cpu.rob.rob_writes 4138016116 # The number of ROB writes 449system.cpu.timesIdled 327647 # Number of times that the entire CPU went into an idle state and unscheduled itself 450system.cpu.idleCycles 15250950 # Total number of cycles that the CPU has spent unscheduled due to idling | 433system.cpu.rob.rob_reads 2747203850 # The number of ROB reads 434system.cpu.rob.rob_writes 4137345189 # The number of ROB writes 435system.cpu.timesIdled 333192 # Number of times that the entire CPU went into an idle state and unscheduled itself 436system.cpu.idleCycles 15425172 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 451system.cpu.committedInsts 826877109 # Number of Instructions Simulated 452system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated 453system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated | 437system.cpu.committedInsts 826877109 # Number of Instructions Simulated 438system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated 439system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated |
| 454system.cpu.cpi 1.051019 # CPI: Cycles Per Instruction 455system.cpu.cpi_total 1.051019 # CPI: Total CPI of All Threads 456system.cpu.ipc 0.951457 # IPC: Instructions Per Cycle 457system.cpu.ipc_total 0.951457 # IPC: Total IPC of All Threads 458system.cpu.int_regfile_reads 3357381544 # number of integer regfile reads 459system.cpu.int_regfile_writes 1848396157 # number of integer regfile writes 460system.cpu.fp_regfile_reads 4985 # number of floating regfile reads 461system.cpu.fp_regfile_writes 5 # number of floating regfile writes 462system.cpu.misc_regfile_reads 980232069 # number of misc regfile reads 463system.cpu.icache.replacements 5428 # number of replacements 464system.cpu.icache.tagsinuse 1035.426880 # Cycle average of tags in use 465system.cpu.icache.total_refs 173198733 # Total number of references to valid blocks. 466system.cpu.icache.sampled_refs 7017 # Sample count of references to valid blocks. 467system.cpu.icache.avg_refs 24682.732364 # Average number of references to valid blocks. | 440system.cpu.cpi 1.050775 # CPI: Cycles Per Instruction 441system.cpu.cpi_total 1.050775 # CPI: Total CPI of All Threads 442system.cpu.ipc 0.951678 # IPC: Instructions Per Cycle 443system.cpu.ipc_total 0.951678 # IPC: Total IPC of All Threads 444system.cpu.int_regfile_reads 3357185623 # number of integer regfile reads 445system.cpu.int_regfile_writes 1848288300 # number of integer regfile writes 446system.cpu.fp_regfile_reads 5295 # number of floating regfile reads 447system.cpu.fp_regfile_writes 3 # number of floating regfile writes 448system.cpu.misc_regfile_reads 980095444 # number of misc regfile reads 449system.cpu.icache.replacements 5498 # number of replacements 450system.cpu.icache.tagsinuse 1034.775539 # Cycle average of tags in use 451system.cpu.icache.total_refs 173205275 # Total number of references to valid blocks. 452system.cpu.icache.sampled_refs 7087 # Sample count of references to valid blocks. 453system.cpu.icache.avg_refs 24439.858191 # Average number of references to valid blocks. |
| 468system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 454system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 469system.cpu.icache.occ_blocks::cpu.inst 1035.426880 # Average occupied blocks per requestor 470system.cpu.icache.occ_percent::cpu.inst 0.505580 # Average percentage of cache occupancy 471system.cpu.icache.occ_percent::total 0.505580 # Average percentage of cache occupancy 472system.cpu.icache.ReadReq_hits::cpu.inst 173214256 # number of ReadReq hits 473system.cpu.icache.ReadReq_hits::total 173214256 # number of ReadReq hits 474system.cpu.icache.demand_hits::cpu.inst 173214256 # number of demand (read+write) hits 475system.cpu.icache.demand_hits::total 173214256 # number of demand (read+write) hits 476system.cpu.icache.overall_hits::cpu.inst 173214256 # number of overall hits 477system.cpu.icache.overall_hits::total 173214256 # number of overall hits 478system.cpu.icache.ReadReq_misses::cpu.inst 225311 # number of ReadReq misses 479system.cpu.icache.ReadReq_misses::total 225311 # number of ReadReq misses 480system.cpu.icache.demand_misses::cpu.inst 225311 # number of demand (read+write) misses 481system.cpu.icache.demand_misses::total 225311 # number of demand (read+write) misses 482system.cpu.icache.overall_misses::cpu.inst 225311 # number of overall misses 483system.cpu.icache.overall_misses::total 225311 # number of overall misses 484system.cpu.icache.ReadReq_miss_latency::cpu.inst 1422825499 # number of ReadReq miss cycles 485system.cpu.icache.ReadReq_miss_latency::total 1422825499 # number of ReadReq miss cycles 486system.cpu.icache.demand_miss_latency::cpu.inst 1422825499 # number of demand (read+write) miss cycles 487system.cpu.icache.demand_miss_latency::total 1422825499 # number of demand (read+write) miss cycles 488system.cpu.icache.overall_miss_latency::cpu.inst 1422825499 # number of overall miss cycles 489system.cpu.icache.overall_miss_latency::total 1422825499 # number of overall miss cycles 490system.cpu.icache.ReadReq_accesses::cpu.inst 173439567 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.ReadReq_accesses::total 173439567 # number of ReadReq accesses(hits+misses) 492system.cpu.icache.demand_accesses::cpu.inst 173439567 # number of demand (read+write) accesses 493system.cpu.icache.demand_accesses::total 173439567 # number of demand (read+write) accesses 494system.cpu.icache.overall_accesses::cpu.inst 173439567 # number of overall (read+write) accesses 495system.cpu.icache.overall_accesses::total 173439567 # number of overall (read+write) accesses 496system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001299 # miss rate for ReadReq accesses 497system.cpu.icache.ReadReq_miss_rate::total 0.001299 # miss rate for ReadReq accesses 498system.cpu.icache.demand_miss_rate::cpu.inst 0.001299 # miss rate for demand accesses 499system.cpu.icache.demand_miss_rate::total 0.001299 # miss rate for demand accesses 500system.cpu.icache.overall_miss_rate::cpu.inst 0.001299 # miss rate for overall accesses 501system.cpu.icache.overall_miss_rate::total 0.001299 # miss rate for overall accesses 502system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6314.940234 # average ReadReq miss latency 503system.cpu.icache.ReadReq_avg_miss_latency::total 6314.940234 # average ReadReq miss latency 504system.cpu.icache.demand_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency 505system.cpu.icache.demand_avg_miss_latency::total 6314.940234 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency 507system.cpu.icache.overall_avg_miss_latency::total 6314.940234 # average overall miss latency 508system.cpu.icache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked | 455system.cpu.icache.occ_blocks::cpu.inst 1034.775539 # Average occupied blocks per requestor 456system.cpu.icache.occ_percent::cpu.inst 0.505261 # Average percentage of cache occupancy 457system.cpu.icache.occ_percent::total 0.505261 # Average percentage of cache occupancy 458system.cpu.icache.ReadReq_hits::cpu.inst 173220667 # number of ReadReq hits 459system.cpu.icache.ReadReq_hits::total 173220667 # number of ReadReq hits 460system.cpu.icache.demand_hits::cpu.inst 173220667 # number of demand (read+write) hits 461system.cpu.icache.demand_hits::total 173220667 # number of demand (read+write) hits 462system.cpu.icache.overall_hits::cpu.inst 173220667 # number of overall hits 463system.cpu.icache.overall_hits::total 173220667 # number of overall hits 464system.cpu.icache.ReadReq_misses::cpu.inst 226207 # number of ReadReq misses 465system.cpu.icache.ReadReq_misses::total 226207 # number of ReadReq misses 466system.cpu.icache.demand_misses::cpu.inst 226207 # number of demand (read+write) misses 467system.cpu.icache.demand_misses::total 226207 # number of demand (read+write) misses 468system.cpu.icache.overall_misses::cpu.inst 226207 # number of overall misses 469system.cpu.icache.overall_misses::total 226207 # number of overall misses 470system.cpu.icache.ReadReq_miss_latency::cpu.inst 1445018998 # number of ReadReq miss cycles 471system.cpu.icache.ReadReq_miss_latency::total 1445018998 # number of ReadReq miss cycles 472system.cpu.icache.demand_miss_latency::cpu.inst 1445018998 # number of demand (read+write) miss cycles 473system.cpu.icache.demand_miss_latency::total 1445018998 # number of demand (read+write) miss cycles 474system.cpu.icache.overall_miss_latency::cpu.inst 1445018998 # number of overall miss cycles 475system.cpu.icache.overall_miss_latency::total 1445018998 # number of overall miss cycles 476system.cpu.icache.ReadReq_accesses::cpu.inst 173446874 # number of ReadReq accesses(hits+misses) 477system.cpu.icache.ReadReq_accesses::total 173446874 # number of ReadReq accesses(hits+misses) 478system.cpu.icache.demand_accesses::cpu.inst 173446874 # number of demand (read+write) accesses 479system.cpu.icache.demand_accesses::total 173446874 # number of demand (read+write) accesses 480system.cpu.icache.overall_accesses::cpu.inst 173446874 # number of overall (read+write) accesses 481system.cpu.icache.overall_accesses::total 173446874 # number of overall (read+write) accesses 482system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001304 # miss rate for ReadReq accesses 483system.cpu.icache.ReadReq_miss_rate::total 0.001304 # miss rate for ReadReq accesses 484system.cpu.icache.demand_miss_rate::cpu.inst 0.001304 # miss rate for demand accesses 485system.cpu.icache.demand_miss_rate::total 0.001304 # miss rate for demand accesses 486system.cpu.icache.overall_miss_rate::cpu.inst 0.001304 # miss rate for overall accesses 487system.cpu.icache.overall_miss_rate::total 0.001304 # miss rate for overall accesses 488system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6388.038381 # average ReadReq miss latency 489system.cpu.icache.ReadReq_avg_miss_latency::total 6388.038381 # average ReadReq miss latency 490system.cpu.icache.demand_avg_miss_latency::cpu.inst 6388.038381 # average overall miss latency 491system.cpu.icache.demand_avg_miss_latency::total 6388.038381 # average overall miss latency 492system.cpu.icache.overall_avg_miss_latency::cpu.inst 6388.038381 # average overall miss latency 493system.cpu.icache.overall_avg_miss_latency::total 6388.038381 # average overall miss latency 494system.cpu.icache.blocked_cycles::no_mshrs 531 # number of cycles access was blocked |
| 509system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 495system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 510system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked | 496system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked |
| 511system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 497system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 512system.cpu.icache.avg_blocked_cycles::no_mshrs 63.785714 # average number of cycles each access was blocked | 498system.cpu.icache.avg_blocked_cycles::no_mshrs 33.187500 # average number of cycles each access was blocked |
| 513system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 514system.cpu.icache.fast_writes 0 # number of fast writes performed 515system.cpu.icache.cache_copies 0 # number of cache copies performed | 499system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 500system.cpu.icache.fast_writes 0 # number of fast writes performed 501system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 516system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2350 # number of ReadReq MSHR hits 517system.cpu.icache.ReadReq_mshr_hits::total 2350 # number of ReadReq MSHR hits 518system.cpu.icache.demand_mshr_hits::cpu.inst 2350 # number of demand (read+write) MSHR hits 519system.cpu.icache.demand_mshr_hits::total 2350 # number of demand (read+write) MSHR hits 520system.cpu.icache.overall_mshr_hits::cpu.inst 2350 # number of overall MSHR hits 521system.cpu.icache.overall_mshr_hits::total 2350 # number of overall MSHR hits 522system.cpu.icache.ReadReq_mshr_misses::cpu.inst 222961 # number of ReadReq MSHR misses 523system.cpu.icache.ReadReq_mshr_misses::total 222961 # number of ReadReq MSHR misses 524system.cpu.icache.demand_mshr_misses::cpu.inst 222961 # number of demand (read+write) MSHR misses 525system.cpu.icache.demand_mshr_misses::total 222961 # number of demand (read+write) MSHR misses 526system.cpu.icache.overall_mshr_misses::cpu.inst 222961 # number of overall MSHR misses 527system.cpu.icache.overall_mshr_misses::total 222961 # number of overall MSHR misses 528system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 908771999 # number of ReadReq MSHR miss cycles 529system.cpu.icache.ReadReq_mshr_miss_latency::total 908771999 # number of ReadReq MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::cpu.inst 908771999 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::total 908771999 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::cpu.inst 908771999 # number of overall MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::total 908771999 # number of overall MSHR miss cycles 534system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for ReadReq accesses 535system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses 536system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for demand accesses 537system.cpu.icache.demand_mshr_miss_rate::total 0.001286 # mshr miss rate for demand accesses 538system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for overall accesses 539system.cpu.icache.overall_mshr_miss_rate::total 0.001286 # mshr miss rate for overall accesses 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4075.923588 # average ReadReq mshr miss latency 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4075.923588 # average ReadReq mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4075.923588 # average overall mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::total 4075.923588 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4075.923588 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::total 4075.923588 # average overall mshr miss latency | 502system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2416 # number of ReadReq MSHR hits 503system.cpu.icache.ReadReq_mshr_hits::total 2416 # number of ReadReq MSHR hits 504system.cpu.icache.demand_mshr_hits::cpu.inst 2416 # number of demand (read+write) MSHR hits 505system.cpu.icache.demand_mshr_hits::total 2416 # number of demand (read+write) MSHR hits 506system.cpu.icache.overall_mshr_hits::cpu.inst 2416 # number of overall MSHR hits 507system.cpu.icache.overall_mshr_hits::total 2416 # number of overall MSHR hits 508system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223791 # number of ReadReq MSHR misses 509system.cpu.icache.ReadReq_mshr_misses::total 223791 # number of ReadReq MSHR misses 510system.cpu.icache.demand_mshr_misses::cpu.inst 223791 # number of demand (read+write) MSHR misses 511system.cpu.icache.demand_mshr_misses::total 223791 # number of demand (read+write) MSHR misses 512system.cpu.icache.overall_mshr_misses::cpu.inst 223791 # number of overall MSHR misses 513system.cpu.icache.overall_mshr_misses::total 223791 # number of overall MSHR misses 514system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 922806998 # number of ReadReq MSHR miss cycles 515system.cpu.icache.ReadReq_mshr_miss_latency::total 922806998 # number of ReadReq MSHR miss cycles 516system.cpu.icache.demand_mshr_miss_latency::cpu.inst 922806998 # number of demand (read+write) MSHR miss cycles 517system.cpu.icache.demand_mshr_miss_latency::total 922806998 # number of demand (read+write) MSHR miss cycles 518system.cpu.icache.overall_mshr_miss_latency::cpu.inst 922806998 # number of overall MSHR miss cycles 519system.cpu.icache.overall_mshr_miss_latency::total 922806998 # number of overall MSHR miss cycles 520system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for ReadReq accesses 521system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001290 # mshr miss rate for ReadReq accesses 522system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for demand accesses 523system.cpu.icache.demand_mshr_miss_rate::total 0.001290 # mshr miss rate for demand accesses 524system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for overall accesses 525system.cpu.icache.overall_mshr_miss_rate::total 0.001290 # mshr miss rate for overall accesses 526system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4123.521491 # average ReadReq mshr miss latency 527system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4123.521491 # average ReadReq mshr miss latency 528system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4123.521491 # average overall mshr miss latency 529system.cpu.icache.demand_avg_mshr_miss_latency::total 4123.521491 # average overall mshr miss latency 530system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4123.521491 # average overall mshr miss latency 531system.cpu.icache.overall_avg_mshr_miss_latency::total 4123.521491 # average overall mshr miss latency |
| 546system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 532system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 547system.cpu.l2cache.replacements 352967 # number of replacements 548system.cpu.l2cache.tagsinuse 29623.610985 # Cycle average of tags in use 549system.cpu.l2cache.total_refs 3697581 # Total number of references to valid blocks. 550system.cpu.l2cache.sampled_refs 385328 # Sample count of references to valid blocks. 551system.cpu.l2cache.avg_refs 9.595931 # Average number of references to valid blocks. 552system.cpu.l2cache.warmup_cycle 202031394500 # Cycle when the warmup percentage was hit. 553system.cpu.l2cache.occ_blocks::writebacks 21046.511292 # Average occupied blocks per requestor 554system.cpu.l2cache.occ_blocks::cpu.inst 232.202938 # Average occupied blocks per requestor 555system.cpu.l2cache.occ_blocks::cpu.data 8344.896755 # Average occupied blocks per requestor 556system.cpu.l2cache.occ_percent::writebacks 0.642289 # Average percentage of cache occupancy 557system.cpu.l2cache.occ_percent::cpu.inst 0.007086 # Average percentage of cache occupancy 558system.cpu.l2cache.occ_percent::cpu.data 0.254666 # Average percentage of cache occupancy 559system.cpu.l2cache.occ_percent::total 0.904041 # Average percentage of cache occupancy 560system.cpu.l2cache.ReadReq_hits::cpu.inst 3753 # number of ReadReq hits 561system.cpu.l2cache.ReadReq_hits::cpu.data 1586557 # number of ReadReq hits 562system.cpu.l2cache.ReadReq_hits::total 1590310 # number of ReadReq hits 563system.cpu.l2cache.Writeback_hits::writebacks 2331178 # number of Writeback hits 564system.cpu.l2cache.Writeback_hits::total 2331178 # number of Writeback hits 565system.cpu.l2cache.UpgradeReq_hits::cpu.data 1519 # number of UpgradeReq hits 566system.cpu.l2cache.UpgradeReq_hits::total 1519 # number of UpgradeReq hits 567system.cpu.l2cache.ReadExReq_hits::cpu.data 564630 # number of ReadExReq hits 568system.cpu.l2cache.ReadExReq_hits::total 564630 # number of ReadExReq hits 569system.cpu.l2cache.demand_hits::cpu.inst 3753 # number of demand (read+write) hits 570system.cpu.l2cache.demand_hits::cpu.data 2151187 # number of demand (read+write) hits 571system.cpu.l2cache.demand_hits::total 2154940 # number of demand (read+write) hits 572system.cpu.l2cache.overall_hits::cpu.inst 3753 # number of overall hits 573system.cpu.l2cache.overall_hits::cpu.data 2151187 # number of overall hits 574system.cpu.l2cache.overall_hits::total 2154940 # number of overall hits | 533system.cpu.l2cache.replacements 352952 # number of replacements 534system.cpu.l2cache.tagsinuse 29623.817782 # Cycle average of tags in use 535system.cpu.l2cache.total_refs 3697849 # Total number of references to valid blocks. 536system.cpu.l2cache.sampled_refs 385320 # Sample count of references to valid blocks. 537system.cpu.l2cache.avg_refs 9.596826 # Average number of references to valid blocks. 538system.cpu.l2cache.warmup_cycle 201967197500 # Cycle when the warmup percentage was hit. 539system.cpu.l2cache.occ_blocks::writebacks 21048.763248 # Average occupied blocks per requestor 540system.cpu.l2cache.occ_blocks::cpu.inst 234.229259 # Average occupied blocks per requestor 541system.cpu.l2cache.occ_blocks::cpu.data 8340.825274 # Average occupied blocks per requestor 542system.cpu.l2cache.occ_percent::writebacks 0.642357 # Average percentage of cache occupancy 543system.cpu.l2cache.occ_percent::cpu.inst 0.007148 # Average percentage of cache occupancy 544system.cpu.l2cache.occ_percent::cpu.data 0.254542 # Average percentage of cache occupancy 545system.cpu.l2cache.occ_percent::total 0.904047 # Average percentage of cache occupancy 546system.cpu.l2cache.ReadReq_hits::cpu.inst 3812 # number of ReadReq hits 547system.cpu.l2cache.ReadReq_hits::cpu.data 1586582 # number of ReadReq hits 548system.cpu.l2cache.ReadReq_hits::total 1590394 # number of ReadReq hits 549system.cpu.l2cache.Writeback_hits::writebacks 2331083 # number of Writeback hits 550system.cpu.l2cache.Writeback_hits::total 2331083 # number of Writeback hits 551system.cpu.l2cache.UpgradeReq_hits::cpu.data 1524 # number of UpgradeReq hits 552system.cpu.l2cache.UpgradeReq_hits::total 1524 # number of UpgradeReq hits 553system.cpu.l2cache.ReadExReq_hits::cpu.data 564588 # number of ReadExReq hits 554system.cpu.l2cache.ReadExReq_hits::total 564588 # number of ReadExReq hits 555system.cpu.l2cache.demand_hits::cpu.inst 3812 # number of demand (read+write) hits 556system.cpu.l2cache.demand_hits::cpu.data 2151170 # number of demand (read+write) hits 557system.cpu.l2cache.demand_hits::total 2154982 # number of demand (read+write) hits 558system.cpu.l2cache.overall_hits::cpu.inst 3812 # number of overall hits 559system.cpu.l2cache.overall_hits::cpu.data 2151170 # number of overall hits 560system.cpu.l2cache.overall_hits::total 2154982 # number of overall hits |
| 575system.cpu.l2cache.ReadReq_misses::cpu.inst 3230 # number of ReadReq misses | 561system.cpu.l2cache.ReadReq_misses::cpu.inst 3230 # number of ReadReq misses |
| 576system.cpu.l2cache.ReadReq_misses::cpu.data 175686 # number of ReadReq misses 577system.cpu.l2cache.ReadReq_misses::total 178916 # number of ReadReq misses 578system.cpu.l2cache.UpgradeReq_misses::cpu.data 214369 # number of UpgradeReq misses 579system.cpu.l2cache.UpgradeReq_misses::total 214369 # number of UpgradeReq misses 580system.cpu.l2cache.ReadExReq_misses::cpu.data 206771 # number of ReadExReq misses 581system.cpu.l2cache.ReadExReq_misses::total 206771 # number of ReadExReq misses | 562system.cpu.l2cache.ReadReq_misses::cpu.data 175670 # number of ReadReq misses 563system.cpu.l2cache.ReadReq_misses::total 178900 # number of ReadReq misses 564system.cpu.l2cache.UpgradeReq_misses::cpu.data 215135 # number of UpgradeReq misses 565system.cpu.l2cache.UpgradeReq_misses::total 215135 # number of UpgradeReq misses 566system.cpu.l2cache.ReadExReq_misses::cpu.data 206768 # number of ReadExReq misses 567system.cpu.l2cache.ReadExReq_misses::total 206768 # number of ReadExReq misses |
| 582system.cpu.l2cache.demand_misses::cpu.inst 3230 # number of demand (read+write) misses | 568system.cpu.l2cache.demand_misses::cpu.inst 3230 # number of demand (read+write) misses |
| 583system.cpu.l2cache.demand_misses::cpu.data 382457 # number of demand (read+write) misses 584system.cpu.l2cache.demand_misses::total 385687 # number of demand (read+write) misses | 569system.cpu.l2cache.demand_misses::cpu.data 382438 # number of demand (read+write) misses 570system.cpu.l2cache.demand_misses::total 385668 # number of demand (read+write) misses |
| 585system.cpu.l2cache.overall_misses::cpu.inst 3230 # number of overall misses | 571system.cpu.l2cache.overall_misses::cpu.inst 3230 # number of overall misses |
| 586system.cpu.l2cache.overall_misses::cpu.data 382457 # number of overall misses 587system.cpu.l2cache.overall_misses::total 385687 # number of overall misses 588system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196335000 # number of ReadReq miss cycles 589system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10103953956 # number of ReadReq miss cycles 590system.cpu.l2cache.ReadReq_miss_latency::total 10300288956 # number of ReadReq miss cycles 591system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7210000 # number of UpgradeReq miss cycles 592system.cpu.l2cache.UpgradeReq_miss_latency::total 7210000 # number of UpgradeReq miss cycles 593system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10386868500 # number of ReadExReq miss cycles 594system.cpu.l2cache.ReadExReq_miss_latency::total 10386868500 # number of ReadExReq miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.inst 196335000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::cpu.data 20490822456 # number of demand (read+write) miss cycles 597system.cpu.l2cache.demand_miss_latency::total 20687157456 # number of demand (read+write) miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.inst 196335000 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::cpu.data 20490822456 # number of overall miss cycles 600system.cpu.l2cache.overall_miss_latency::total 20687157456 # number of overall miss cycles 601system.cpu.l2cache.ReadReq_accesses::cpu.inst 6983 # number of ReadReq accesses(hits+misses) 602system.cpu.l2cache.ReadReq_accesses::cpu.data 1762243 # number of ReadReq accesses(hits+misses) 603system.cpu.l2cache.ReadReq_accesses::total 1769226 # number of ReadReq accesses(hits+misses) 604system.cpu.l2cache.Writeback_accesses::writebacks 2331178 # number of Writeback accesses(hits+misses) 605system.cpu.l2cache.Writeback_accesses::total 2331178 # number of Writeback accesses(hits+misses) 606system.cpu.l2cache.UpgradeReq_accesses::cpu.data 215888 # number of UpgradeReq accesses(hits+misses) 607system.cpu.l2cache.UpgradeReq_accesses::total 215888 # number of UpgradeReq accesses(hits+misses) 608system.cpu.l2cache.ReadExReq_accesses::cpu.data 771401 # number of ReadExReq accesses(hits+misses) 609system.cpu.l2cache.ReadExReq_accesses::total 771401 # number of ReadExReq accesses(hits+misses) 610system.cpu.l2cache.demand_accesses::cpu.inst 6983 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::cpu.data 2533644 # number of demand (read+write) accesses 612system.cpu.l2cache.demand_accesses::total 2540627 # number of demand (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.inst 6983 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::cpu.data 2533644 # number of overall (read+write) accesses 615system.cpu.l2cache.overall_accesses::total 2540627 # number of overall (read+write) accesses 616system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462552 # miss rate for ReadReq accesses 617system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099695 # miss rate for ReadReq accesses 618system.cpu.l2cache.ReadReq_miss_rate::total 0.101127 # miss rate for ReadReq accesses 619system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992964 # miss rate for UpgradeReq accesses 620system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992964 # miss rate for UpgradeReq accesses 621system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268046 # miss rate for ReadExReq accesses 622system.cpu.l2cache.ReadExReq_miss_rate::total 0.268046 # miss rate for ReadExReq accesses 623system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462552 # miss rate for demand accesses 624system.cpu.l2cache.demand_miss_rate::cpu.data 0.150951 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::total 0.151808 # miss rate for demand accesses 626system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462552 # miss rate for overall accesses 627system.cpu.l2cache.overall_miss_rate::cpu.data 0.150951 # miss rate for overall accesses 628system.cpu.l2cache.overall_miss_rate::total 0.151808 # miss rate for overall accesses 629system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60784.829721 # average ReadReq miss latency 630system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57511.434924 # average ReadReq miss latency 631system.cpu.l2cache.ReadReq_avg_miss_latency::total 57570.530059 # average ReadReq miss latency 632system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 33.633594 # average UpgradeReq miss latency 633system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 33.633594 # average UpgradeReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50233.681222 # average ReadExReq miss latency 635system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50233.681222 # average ReadExReq miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency 638system.cpu.l2cache.demand_avg_miss_latency::total 53637.165515 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency 641system.cpu.l2cache.overall_avg_miss_latency::total 53637.165515 # average overall miss latency | 572system.cpu.l2cache.overall_misses::cpu.data 382438 # number of overall misses 573system.cpu.l2cache.overall_misses::total 385668 # number of overall misses 574system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200745500 # number of ReadReq miss cycles 575system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10125783456 # number of ReadReq miss cycles 576system.cpu.l2cache.ReadReq_miss_latency::total 10326528956 # number of ReadReq miss cycles 577system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7277000 # number of UpgradeReq miss cycles 578system.cpu.l2cache.UpgradeReq_miss_latency::total 7277000 # number of UpgradeReq miss cycles 579system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10354954000 # number of ReadExReq miss cycles 580system.cpu.l2cache.ReadExReq_miss_latency::total 10354954000 # number of ReadExReq miss cycles 581system.cpu.l2cache.demand_miss_latency::cpu.inst 200745500 # number of demand (read+write) miss cycles 582system.cpu.l2cache.demand_miss_latency::cpu.data 20480737456 # number of demand (read+write) miss cycles 583system.cpu.l2cache.demand_miss_latency::total 20681482956 # number of demand (read+write) miss cycles 584system.cpu.l2cache.overall_miss_latency::cpu.inst 200745500 # number of overall miss cycles 585system.cpu.l2cache.overall_miss_latency::cpu.data 20480737456 # number of overall miss cycles 586system.cpu.l2cache.overall_miss_latency::total 20681482956 # number of overall miss cycles 587system.cpu.l2cache.ReadReq_accesses::cpu.inst 7042 # number of ReadReq accesses(hits+misses) 588system.cpu.l2cache.ReadReq_accesses::cpu.data 1762252 # number of ReadReq accesses(hits+misses) 589system.cpu.l2cache.ReadReq_accesses::total 1769294 # number of ReadReq accesses(hits+misses) 590system.cpu.l2cache.Writeback_accesses::writebacks 2331083 # number of Writeback accesses(hits+misses) 591system.cpu.l2cache.Writeback_accesses::total 2331083 # number of Writeback accesses(hits+misses) 592system.cpu.l2cache.UpgradeReq_accesses::cpu.data 216659 # number of UpgradeReq accesses(hits+misses) 593system.cpu.l2cache.UpgradeReq_accesses::total 216659 # number of UpgradeReq accesses(hits+misses) 594system.cpu.l2cache.ReadExReq_accesses::cpu.data 771356 # number of ReadExReq accesses(hits+misses) 595system.cpu.l2cache.ReadExReq_accesses::total 771356 # number of ReadExReq accesses(hits+misses) 596system.cpu.l2cache.demand_accesses::cpu.inst 7042 # number of demand (read+write) accesses 597system.cpu.l2cache.demand_accesses::cpu.data 2533608 # number of demand (read+write) accesses 598system.cpu.l2cache.demand_accesses::total 2540650 # number of demand (read+write) accesses 599system.cpu.l2cache.overall_accesses::cpu.inst 7042 # number of overall (read+write) accesses 600system.cpu.l2cache.overall_accesses::cpu.data 2533608 # number of overall (read+write) accesses 601system.cpu.l2cache.overall_accesses::total 2540650 # number of overall (read+write) accesses 602system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.458677 # miss rate for ReadReq accesses 603system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099685 # miss rate for ReadReq accesses 604system.cpu.l2cache.ReadReq_miss_rate::total 0.101114 # miss rate for ReadReq accesses 605system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992966 # miss rate for UpgradeReq accesses 606system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992966 # miss rate for UpgradeReq accesses 607system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268058 # miss rate for ReadExReq accesses 608system.cpu.l2cache.ReadExReq_miss_rate::total 0.268058 # miss rate for ReadExReq accesses 609system.cpu.l2cache.demand_miss_rate::cpu.inst 0.458677 # miss rate for demand accesses 610system.cpu.l2cache.demand_miss_rate::cpu.data 0.150946 # miss rate for demand accesses 611system.cpu.l2cache.demand_miss_rate::total 0.151799 # miss rate for demand accesses 612system.cpu.l2cache.overall_miss_rate::cpu.inst 0.458677 # miss rate for overall accesses 613system.cpu.l2cache.overall_miss_rate::cpu.data 0.150946 # miss rate for overall accesses 614system.cpu.l2cache.overall_miss_rate::total 0.151799 # miss rate for overall accesses 615system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62150.309598 # average ReadReq miss latency 616system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57640.937303 # average ReadReq miss latency 617system.cpu.l2cache.ReadReq_avg_miss_latency::total 57722.353024 # average ReadReq miss latency 618system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 33.825273 # average UpgradeReq miss latency 619system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 33.825273 # average UpgradeReq miss latency 620system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50080.060744 # average ReadExReq miss latency 621system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50080.060744 # average ReadExReq miss latency 622system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62150.309598 # average overall miss latency 623system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53553.092151 # average overall miss latency 624system.cpu.l2cache.demand_avg_miss_latency::total 53625.094527 # average overall miss latency 625system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62150.309598 # average overall miss latency 626system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53553.092151 # average overall miss latency 627system.cpu.l2cache.overall_avg_miss_latency::total 53625.094527 # average overall miss latency |
| 642system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 645system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 647system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.l2cache.fast_writes 0 # number of fast writes performed 649system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 628system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 629system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 630system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 632system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 633system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 634system.cpu.l2cache.fast_writes 0 # number of fast writes performed 635system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 650system.cpu.l2cache.writebacks::writebacks 293648 # number of writebacks 651system.cpu.l2cache.writebacks::total 293648 # number of writebacks | 636system.cpu.l2cache.writebacks::writebacks 293628 # number of writebacks 637system.cpu.l2cache.writebacks::total 293628 # number of writebacks |
| 652system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3230 # number of ReadReq MSHR misses | 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3230 # number of ReadReq MSHR misses |
| 653system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175686 # number of ReadReq MSHR misses 654system.cpu.l2cache.ReadReq_mshr_misses::total 178916 # number of ReadReq MSHR misses 655system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 214369 # number of UpgradeReq MSHR misses 656system.cpu.l2cache.UpgradeReq_mshr_misses::total 214369 # number of UpgradeReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206771 # number of ReadExReq MSHR misses 658system.cpu.l2cache.ReadExReq_mshr_misses::total 206771 # number of ReadExReq MSHR misses | 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175670 # number of ReadReq MSHR misses 640system.cpu.l2cache.ReadReq_mshr_misses::total 178900 # number of ReadReq MSHR misses 641system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 215135 # number of UpgradeReq MSHR misses 642system.cpu.l2cache.UpgradeReq_mshr_misses::total 215135 # number of UpgradeReq MSHR misses 643system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206768 # number of ReadExReq MSHR misses 644system.cpu.l2cache.ReadExReq_mshr_misses::total 206768 # number of ReadExReq MSHR misses |
| 659system.cpu.l2cache.demand_mshr_misses::cpu.inst 3230 # number of demand (read+write) MSHR misses | 645system.cpu.l2cache.demand_mshr_misses::cpu.inst 3230 # number of demand (read+write) MSHR misses |
| 660system.cpu.l2cache.demand_mshr_misses::cpu.data 382457 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.demand_mshr_misses::total 385687 # number of demand (read+write) MSHR misses | 646system.cpu.l2cache.demand_mshr_misses::cpu.data 382438 # number of demand (read+write) MSHR misses 647system.cpu.l2cache.demand_mshr_misses::total 385668 # number of demand (read+write) MSHR misses |
| 662system.cpu.l2cache.overall_mshr_misses::cpu.inst 3230 # number of overall MSHR misses | 648system.cpu.l2cache.overall_mshr_misses::cpu.inst 3230 # number of overall MSHR misses |
| 663system.cpu.l2cache.overall_mshr_misses::cpu.data 382457 # number of overall MSHR misses 664system.cpu.l2cache.overall_mshr_misses::total 385687 # number of overall MSHR misses 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156219180 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7929842195 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8086061375 # number of ReadReq MSHR miss cycles 668system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2149350076 # number of UpgradeReq MSHR miss cycles 669system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2149350076 # number of UpgradeReq MSHR miss cycles 670system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7799617575 # number of ReadExReq MSHR miss cycles 671system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7799617575 # number of ReadExReq MSHR miss cycles 672system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156219180 # number of demand (read+write) MSHR miss cycles 673system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15729459770 # number of demand (read+write) MSHR miss cycles 674system.cpu.l2cache.demand_mshr_miss_latency::total 15885678950 # number of demand (read+write) MSHR miss cycles 675system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156219180 # number of overall MSHR miss cycles 676system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15729459770 # number of overall MSHR miss cycles 677system.cpu.l2cache.overall_mshr_miss_latency::total 15885678950 # number of overall MSHR miss cycles 678system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for ReadReq accesses 679system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099695 # mshr miss rate for ReadReq accesses 680system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101127 # mshr miss rate for ReadReq accesses 681system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992964 # mshr miss rate for UpgradeReq accesses 682system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992964 # mshr miss rate for UpgradeReq accesses 683system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses 684system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses 685system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for demand accesses 686system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for demand accesses 687system.cpu.l2cache.demand_mshr_miss_rate::total 0.151808 # mshr miss rate for demand accesses 688system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for overall accesses 689system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for overall accesses 690system.cpu.l2cache.overall_mshr_miss_rate::total 0.151808 # mshr miss rate for overall accesses 691system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48365.071207 # average ReadReq mshr miss latency 692system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45136.449091 # average ReadReq mshr miss latency 693system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45194.735938 # average ReadReq mshr miss latency 694system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.403426 # average UpgradeReq mshr miss latency 695system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.403426 # average UpgradeReq mshr miss latency 696system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37721.041998 # average ReadExReq mshr miss latency 697system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37721.041998 # average ReadExReq mshr miss latency 698system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency 699system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency 700system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency 701system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency 702system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency 703system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency | 649system.cpu.l2cache.overall_mshr_misses::cpu.data 382438 # number of overall MSHR misses 650system.cpu.l2cache.overall_mshr_misses::total 385668 # number of overall MSHR misses 651system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160592502 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7951741535 # number of ReadReq MSHR miss cycles 653system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8112334037 # number of ReadReq MSHR miss cycles 654system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2156878107 # number of UpgradeReq MSHR miss cycles 655system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2156878107 # number of UpgradeReq MSHR miss cycles 656system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7767550023 # number of ReadExReq MSHR miss cycles 657system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7767550023 # number of ReadExReq MSHR miss cycles 658system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160592502 # number of demand (read+write) MSHR miss cycles 659system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15719291558 # number of demand (read+write) MSHR miss cycles 660system.cpu.l2cache.demand_mshr_miss_latency::total 15879884060 # number of demand (read+write) MSHR miss cycles 661system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160592502 # number of overall MSHR miss cycles 662system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15719291558 # number of overall MSHR miss cycles 663system.cpu.l2cache.overall_mshr_miss_latency::total 15879884060 # number of overall MSHR miss cycles 664system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for ReadReq accesses 665system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099685 # mshr miss rate for ReadReq accesses 666system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101114 # mshr miss rate for ReadReq accesses 667system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992966 # mshr miss rate for UpgradeReq accesses 668system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992966 # mshr miss rate for UpgradeReq accesses 669system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268058 # mshr miss rate for ReadExReq accesses 670system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268058 # mshr miss rate for ReadExReq accesses 671system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for demand accesses 672system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150946 # mshr miss rate for demand accesses 673system.cpu.l2cache.demand_mshr_miss_rate::total 0.151799 # mshr miss rate for demand accesses 674system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for overall accesses 675system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150946 # mshr miss rate for overall accesses 676system.cpu.l2cache.overall_mshr_miss_rate::total 0.151799 # mshr miss rate for overall accesses 677system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.040867 # average ReadReq mshr miss latency 678system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45265.221922 # average ReadReq mshr miss latency 679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45345.634639 # average ReadReq mshr miss latency 680system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.695991 # average UpgradeReq mshr miss latency 681system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.695991 # average UpgradeReq mshr miss latency 682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37566.499763 # average ReadExReq mshr miss latency 683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37566.499763 # average ReadExReq mshr miss latency 684system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49719.040867 # average overall mshr miss latency 685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41102.849502 # average overall mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41175.010786 # average overall mshr miss latency 687system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49719.040867 # average overall mshr miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41102.849502 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41175.010786 # average overall mshr miss latency |
| 704system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 690system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 705system.cpu.dcache.replacements 2529546 # number of replacements 706system.cpu.dcache.tagsinuse 4087.815974 # Cycle average of tags in use 707system.cpu.dcache.total_refs 405263721 # Total number of references to valid blocks. 708system.cpu.dcache.sampled_refs 2533642 # Sample count of references to valid blocks. 709system.cpu.dcache.avg_refs 159.953032 # Average number of references to valid blocks. | 691system.cpu.dcache.replacements 2529510 # number of replacements 692system.cpu.dcache.tagsinuse 4087.814071 # Cycle average of tags in use 693system.cpu.dcache.total_refs 405300363 # Total number of references to valid blocks. 694system.cpu.dcache.sampled_refs 2533606 # Sample count of references to valid blocks. 695system.cpu.dcache.avg_refs 159.969768 # Average number of references to valid blocks. |
| 710system.cpu.dcache.warmup_cycle 1790563000 # Cycle when the warmup percentage was hit. | 696system.cpu.dcache.warmup_cycle 1790563000 # Cycle when the warmup percentage was hit. |
| 711system.cpu.dcache.occ_blocks::cpu.data 4087.815974 # Average occupied blocks per requestor 712system.cpu.dcache.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy 713system.cpu.dcache.occ_percent::total 0.998002 # Average percentage of cache occupancy 714system.cpu.dcache.ReadReq_hits::cpu.data 256525921 # number of ReadReq hits 715system.cpu.dcache.ReadReq_hits::total 256525921 # number of ReadReq hits 716system.cpu.dcache.WriteReq_hits::cpu.data 148156323 # number of WriteReq hits 717system.cpu.dcache.WriteReq_hits::total 148156323 # number of WriteReq hits 718system.cpu.dcache.demand_hits::cpu.data 404682244 # number of demand (read+write) hits 719system.cpu.dcache.demand_hits::total 404682244 # number of demand (read+write) hits 720system.cpu.dcache.overall_hits::cpu.data 404682244 # number of overall hits 721system.cpu.dcache.overall_hits::total 404682244 # number of overall hits 722system.cpu.dcache.ReadReq_misses::cpu.data 2897766 # number of ReadReq misses 723system.cpu.dcache.ReadReq_misses::total 2897766 # number of ReadReq misses 724system.cpu.dcache.WriteReq_misses::cpu.data 1003879 # number of WriteReq misses 725system.cpu.dcache.WriteReq_misses::total 1003879 # number of WriteReq misses 726system.cpu.dcache.demand_misses::cpu.data 3901645 # number of demand (read+write) misses 727system.cpu.dcache.demand_misses::total 3901645 # number of demand (read+write) misses 728system.cpu.dcache.overall_misses::cpu.data 3901645 # number of overall misses 729system.cpu.dcache.overall_misses::total 3901645 # number of overall misses 730system.cpu.dcache.ReadReq_miss_latency::cpu.data 51407808000 # number of ReadReq miss cycles 731system.cpu.dcache.ReadReq_miss_latency::total 51407808000 # number of ReadReq miss cycles 732system.cpu.dcache.WriteReq_miss_latency::cpu.data 23879895000 # number of WriteReq miss cycles 733system.cpu.dcache.WriteReq_miss_latency::total 23879895000 # number of WriteReq miss cycles 734system.cpu.dcache.demand_miss_latency::cpu.data 75287703000 # number of demand (read+write) miss cycles 735system.cpu.dcache.demand_miss_latency::total 75287703000 # number of demand (read+write) miss cycles 736system.cpu.dcache.overall_miss_latency::cpu.data 75287703000 # number of overall miss cycles 737system.cpu.dcache.overall_miss_latency::total 75287703000 # number of overall miss cycles 738system.cpu.dcache.ReadReq_accesses::cpu.data 259423687 # number of ReadReq accesses(hits+misses) 739system.cpu.dcache.ReadReq_accesses::total 259423687 # number of ReadReq accesses(hits+misses) | 697system.cpu.dcache.occ_blocks::cpu.data 4087.814071 # Average occupied blocks per requestor 698system.cpu.dcache.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy 699system.cpu.dcache.occ_percent::total 0.998001 # Average percentage of cache occupancy 700system.cpu.dcache.ReadReq_hits::cpu.data 256561451 # number of ReadReq hits 701system.cpu.dcache.ReadReq_hits::total 256561451 # number of ReadReq hits 702system.cpu.dcache.WriteReq_hits::cpu.data 148155645 # number of WriteReq hits 703system.cpu.dcache.WriteReq_hits::total 148155645 # number of WriteReq hits 704system.cpu.dcache.demand_hits::cpu.data 404717096 # number of demand (read+write) hits 705system.cpu.dcache.demand_hits::total 404717096 # number of demand (read+write) hits 706system.cpu.dcache.overall_hits::cpu.data 404717096 # number of overall hits 707system.cpu.dcache.overall_hits::total 404717096 # number of overall hits 708system.cpu.dcache.ReadReq_misses::cpu.data 2903042 # number of ReadReq misses 709system.cpu.dcache.ReadReq_misses::total 2903042 # number of ReadReq misses 710system.cpu.dcache.WriteReq_misses::cpu.data 1004557 # number of WriteReq misses 711system.cpu.dcache.WriteReq_misses::total 1004557 # number of WriteReq misses 712system.cpu.dcache.demand_misses::cpu.data 3907599 # number of demand (read+write) misses 713system.cpu.dcache.demand_misses::total 3907599 # number of demand (read+write) misses 714system.cpu.dcache.overall_misses::cpu.data 3907599 # number of overall misses 715system.cpu.dcache.overall_misses::total 3907599 # number of overall misses 716system.cpu.dcache.ReadReq_miss_latency::cpu.data 51581963000 # number of ReadReq miss cycles 717system.cpu.dcache.ReadReq_miss_latency::total 51581963000 # number of ReadReq miss cycles 718system.cpu.dcache.WriteReq_miss_latency::cpu.data 23867126500 # number of WriteReq miss cycles 719system.cpu.dcache.WriteReq_miss_latency::total 23867126500 # number of WriteReq miss cycles 720system.cpu.dcache.demand_miss_latency::cpu.data 75449089500 # number of demand (read+write) miss cycles 721system.cpu.dcache.demand_miss_latency::total 75449089500 # number of demand (read+write) miss cycles 722system.cpu.dcache.overall_miss_latency::cpu.data 75449089500 # number of overall miss cycles 723system.cpu.dcache.overall_miss_latency::total 75449089500 # number of overall miss cycles 724system.cpu.dcache.ReadReq_accesses::cpu.data 259464493 # number of ReadReq accesses(hits+misses) 725system.cpu.dcache.ReadReq_accesses::total 259464493 # number of ReadReq accesses(hits+misses) |
| 740system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 741system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) | 726system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 727system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) |
| 742system.cpu.dcache.demand_accesses::cpu.data 408583889 # number of demand (read+write) accesses 743system.cpu.dcache.demand_accesses::total 408583889 # number of demand (read+write) accesses 744system.cpu.dcache.overall_accesses::cpu.data 408583889 # number of overall (read+write) accesses 745system.cpu.dcache.overall_accesses::total 408583889 # number of overall (read+write) accesses 746system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011170 # miss rate for ReadReq accesses 747system.cpu.dcache.ReadReq_miss_rate::total 0.011170 # miss rate for ReadReq accesses 748system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006730 # miss rate for WriteReq accesses 749system.cpu.dcache.WriteReq_miss_rate::total 0.006730 # miss rate for WriteReq accesses 750system.cpu.dcache.demand_miss_rate::cpu.data 0.009549 # miss rate for demand accesses 751system.cpu.dcache.demand_miss_rate::total 0.009549 # miss rate for demand accesses 752system.cpu.dcache.overall_miss_rate::cpu.data 0.009549 # miss rate for overall accesses 753system.cpu.dcache.overall_miss_rate::total 0.009549 # miss rate for overall accesses 754system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17740.496645 # average ReadReq miss latency 755system.cpu.dcache.ReadReq_avg_miss_latency::total 17740.496645 # average ReadReq miss latency 756system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23787.622811 # average WriteReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::total 23787.622811 # average WriteReq miss latency 758system.cpu.dcache.demand_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency 759system.cpu.dcache.demand_avg_miss_latency::total 19296.400108 # average overall miss latency 760system.cpu.dcache.overall_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency 761system.cpu.dcache.overall_avg_miss_latency::total 19296.400108 # average overall miss latency 762system.cpu.dcache.blocked_cycles::no_mshrs 6861 # number of cycles access was blocked | 728system.cpu.dcache.demand_accesses::cpu.data 408624695 # number of demand (read+write) accesses 729system.cpu.dcache.demand_accesses::total 408624695 # number of demand (read+write) accesses 730system.cpu.dcache.overall_accesses::cpu.data 408624695 # number of overall (read+write) accesses 731system.cpu.dcache.overall_accesses::total 408624695 # number of overall (read+write) accesses 732system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011189 # miss rate for ReadReq accesses 733system.cpu.dcache.ReadReq_miss_rate::total 0.011189 # miss rate for ReadReq accesses 734system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006735 # miss rate for WriteReq accesses 735system.cpu.dcache.WriteReq_miss_rate::total 0.006735 # miss rate for WriteReq accesses 736system.cpu.dcache.demand_miss_rate::cpu.data 0.009563 # miss rate for demand accesses 737system.cpu.dcache.demand_miss_rate::total 0.009563 # miss rate for demand accesses 738system.cpu.dcache.overall_miss_rate::cpu.data 0.009563 # miss rate for overall accesses 739system.cpu.dcache.overall_miss_rate::total 0.009563 # miss rate for overall accesses 740system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17768.245516 # average ReadReq miss latency 741system.cpu.dcache.ReadReq_avg_miss_latency::total 17768.245516 # average ReadReq miss latency 742system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23758.857387 # average WriteReq miss latency 743system.cpu.dcache.WriteReq_avg_miss_latency::total 23758.857387 # average WriteReq miss latency 744system.cpu.dcache.demand_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency 745system.cpu.dcache.demand_avg_miss_latency::total 19308.298907 # average overall miss latency 746system.cpu.dcache.overall_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency 747system.cpu.dcache.overall_avg_miss_latency::total 19308.298907 # average overall miss latency 748system.cpu.dcache.blocked_cycles::no_mshrs 6217 # number of cycles access was blocked |
| 763system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 749system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 764system.cpu.dcache.blocked::no_mshrs 663 # number of cycles access was blocked | 750system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked |
| 765system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 751system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 766system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.348416 # average number of cycles each access was blocked | 752system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.129222 # average number of cycles each access was blocked |
| 767system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu.dcache.fast_writes 0 # number of fast writes performed 769system.cpu.dcache.cache_copies 0 # number of cache copies performed | 753system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 754system.cpu.dcache.fast_writes 0 # number of fast writes performed 755system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 770system.cpu.dcache.writebacks::writebacks 2331178 # number of writebacks 771system.cpu.dcache.writebacks::total 2331178 # number of writebacks 772system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1135254 # number of ReadReq MSHR hits 773system.cpu.dcache.ReadReq_mshr_hits::total 1135254 # number of ReadReq MSHR hits 774system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16862 # number of WriteReq MSHR hits 775system.cpu.dcache.WriteReq_mshr_hits::total 16862 # number of WriteReq MSHR hits 776system.cpu.dcache.demand_mshr_hits::cpu.data 1152116 # number of demand (read+write) MSHR hits 777system.cpu.dcache.demand_mshr_hits::total 1152116 # number of demand (read+write) MSHR hits 778system.cpu.dcache.overall_mshr_hits::cpu.data 1152116 # number of overall MSHR hits 779system.cpu.dcache.overall_mshr_hits::total 1152116 # number of overall MSHR hits 780system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762512 # number of ReadReq MSHR misses 781system.cpu.dcache.ReadReq_mshr_misses::total 1762512 # number of ReadReq MSHR misses 782system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987017 # number of WriteReq MSHR misses 783system.cpu.dcache.WriteReq_mshr_misses::total 987017 # number of WriteReq MSHR misses 784system.cpu.dcache.demand_mshr_misses::cpu.data 2749529 # number of demand (read+write) MSHR misses 785system.cpu.dcache.demand_mshr_misses::total 2749529 # number of demand (read+write) MSHR misses 786system.cpu.dcache.overall_mshr_misses::cpu.data 2749529 # number of overall MSHR misses 787system.cpu.dcache.overall_mshr_misses::total 2749529 # number of overall MSHR misses 788system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27769073500 # number of ReadReq MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_latency::total 27769073500 # number of ReadReq MSHR miss cycles 790system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21705384500 # number of WriteReq MSHR miss cycles 791system.cpu.dcache.WriteReq_mshr_miss_latency::total 21705384500 # number of WriteReq MSHR miss cycles 792system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49474458000 # number of demand (read+write) MSHR miss cycles 793system.cpu.dcache.demand_mshr_miss_latency::total 49474458000 # number of demand (read+write) MSHR miss cycles 794system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49474458000 # number of overall MSHR miss cycles 795system.cpu.dcache.overall_mshr_miss_latency::total 49474458000 # number of overall MSHR miss cycles 796system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses 797system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses 798system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for WriteReq accesses 799system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006617 # mshr miss rate for WriteReq accesses 800system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for demand accesses 801system.cpu.dcache.demand_mshr_miss_rate::total 0.006729 # mshr miss rate for demand accesses 802system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for overall accesses 803system.cpu.dcache.overall_mshr_miss_rate::total 0.006729 # mshr miss rate for overall accesses 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15755.395424 # average ReadReq mshr miss latency 805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15755.395424 # average ReadReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21990.892254 # average WriteReq mshr miss latency 807system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21990.892254 # average WriteReq mshr miss latency 808system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency 809system.cpu.dcache.demand_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency 810system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency 811system.cpu.dcache.overall_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency | 756system.cpu.dcache.writebacks::writebacks 2331083 # number of writebacks 757system.cpu.dcache.writebacks::total 2331083 # number of writebacks 758system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140525 # number of ReadReq MSHR hits 759system.cpu.dcache.ReadReq_mshr_hits::total 1140525 # number of ReadReq MSHR hits 760system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16809 # number of WriteReq MSHR hits 761system.cpu.dcache.WriteReq_mshr_hits::total 16809 # number of WriteReq MSHR hits 762system.cpu.dcache.demand_mshr_hits::cpu.data 1157334 # number of demand (read+write) MSHR hits 763system.cpu.dcache.demand_mshr_hits::total 1157334 # number of demand (read+write) MSHR hits 764system.cpu.dcache.overall_mshr_hits::cpu.data 1157334 # number of overall MSHR hits 765system.cpu.dcache.overall_mshr_hits::total 1157334 # number of overall MSHR hits 766system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762517 # number of ReadReq MSHR misses 767system.cpu.dcache.ReadReq_mshr_misses::total 1762517 # number of ReadReq MSHR misses 768system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987748 # number of WriteReq MSHR misses 769system.cpu.dcache.WriteReq_mshr_misses::total 987748 # number of WriteReq MSHR misses 770system.cpu.dcache.demand_mshr_misses::cpu.data 2750265 # number of demand (read+write) MSHR misses 771system.cpu.dcache.demand_mshr_misses::total 2750265 # number of demand (read+write) MSHR misses 772system.cpu.dcache.overall_mshr_misses::cpu.data 2750265 # number of overall MSHR misses 773system.cpu.dcache.overall_mshr_misses::total 2750265 # number of overall MSHR misses 774system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27791691500 # number of ReadReq MSHR miss cycles 775system.cpu.dcache.ReadReq_mshr_miss_latency::total 27791691500 # number of ReadReq MSHR miss cycles 776system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21690054500 # number of WriteReq MSHR miss cycles 777system.cpu.dcache.WriteReq_mshr_miss_latency::total 21690054500 # number of WriteReq MSHR miss cycles 778system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49481746000 # number of demand (read+write) MSHR miss cycles 779system.cpu.dcache.demand_mshr_miss_latency::total 49481746000 # number of demand (read+write) MSHR miss cycles 780system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49481746000 # number of overall MSHR miss cycles 781system.cpu.dcache.overall_mshr_miss_latency::total 49481746000 # number of overall MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses 783system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses 784system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006622 # mshr miss rate for WriteReq accesses 785system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006622 # mshr miss rate for WriteReq accesses 786system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for demand accesses 787system.cpu.dcache.demand_mshr_miss_rate::total 0.006731 # mshr miss rate for demand accesses 788system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for overall accesses 789system.cpu.dcache.overall_mshr_miss_rate::total 0.006731 # mshr miss rate for overall accesses 790system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15768.183513 # average ReadReq mshr miss latency 791system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15768.183513 # average ReadReq mshr miss latency 792system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21959.097361 # average WriteReq mshr miss latency 793system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21959.097361 # average WriteReq mshr miss latency 794system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency 795system.cpu.dcache.demand_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency 796system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency 797system.cpu.dcache.overall_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency |
| 812system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 813 814---------- End Simulation Statistics ---------- | 798system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 799 800---------- End Simulation Statistics ---------- |