1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.460397 # Number of seconds simulated
4sim_ticks 460397003000 # Number of ticks simulated
5final_tick 460397003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.433562 # Number of seconds simulated
4sim_ticks 433562236500 # Number of ticks simulated
5final_tick 433562236500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 79363 # Simulator instruction rate (inst/s)
8host_op_rate 146752 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 44188751 # Simulator tick rate (ticks/s)
10host_mem_usage 271496 # Number of bytes of host memory used
11host_seconds 10418.87 # Real time elapsed on the host
| 7host_inst_rate 69861 # Simulator instruction rate (inst/s)
8host_op_rate 129182 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 36630948 # Simulator tick rate (ticks/s)
10host_mem_usage 312956 # Number of bytes of host memory used
11host_seconds 11835.95 # Real time elapsed on the host
|
12sim_insts 826877109 # Number of instructions simulated
13sim_ops 1528988699 # Number of ops (including micro ops) simulated
| 12sim_insts 826877109 # Number of instructions simulated
13sim_ops 1528988699 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read::cpu.inst 220608 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 27602816 # Number of bytes read from this memory
16system.physmem.bytes_read::total 27823424 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 220608 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 220608 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 20793216 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20793216 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3447 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 431294 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 434741 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 324894 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 324894 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 479169 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 59954378 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 60433547 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 479169 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 479169 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 45163665 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 45163665 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 45163665 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 479169 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 59954378 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 105597212 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu.inst 223808 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 27615936 # Number of bytes read from this memory
16system.physmem.bytes_read::total 27839744 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 223808 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 223808 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 20802240 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20802240 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3497 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 431499 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 434996 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 325035 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 325035 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 516207 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 63695437 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 64211644 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 516207 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 516207 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 47979824 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 47979824 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 47979824 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 516207 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 63695437 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 112191469 # Total bandwidth to/from this memory (bytes/s)
|
37system.cpu.workload.num_syscalls 551 # Number of system calls
| 37system.cpu.workload.num_syscalls 551 # Number of system calls
|
38system.cpu.numCycles 920794007 # number of cpu cycles simulated
| 38system.cpu.numCycles 867124474 # number of cpu cycles simulated
|
39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
41system.cpu.BPredUnit.lookups 225794462 # Number of BP lookups
42system.cpu.BPredUnit.condPredicted 225794462 # Number of conditional branches predicted
43system.cpu.BPredUnit.condIncorrect 14310990 # Number of conditional branches incorrect
44system.cpu.BPredUnit.BTBLookups 160522970 # Number of BTB lookups
45system.cpu.BPredUnit.BTBHits 155979425 # Number of BTB hits
| 41system.cpu.BPredUnit.lookups 221451605 # Number of BP lookups
42system.cpu.BPredUnit.condPredicted 221451605 # Number of conditional branches predicted
43system.cpu.BPredUnit.condIncorrect 14391219 # Number of conditional branches incorrect
44system.cpu.BPredUnit.BTBLookups 156554468 # Number of BTB lookups
45system.cpu.BPredUnit.BTBHits 152744780 # Number of BTB hits
|
46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
| 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
49system.cpu.fetch.icacheStallCycles 191744262 # Number of cycles fetch is stalled on an Icache miss
50system.cpu.fetch.Insts 1263331162 # Number of instructions fetch has processed
51system.cpu.fetch.Branches 225794462 # Number of branches that fetch encountered
52system.cpu.fetch.predictedBranches 155979425 # Number of branches that fetch has predicted taken
53system.cpu.fetch.Cycles 392171634 # Number of cycles fetch has run and was not squashing or blocked
54system.cpu.fetch.SquashCycles 98591454 # Number of cycles fetch has spent squashing
55system.cpu.fetch.BlockedCycles 238962985 # Number of cycles fetch has spent blocked
56system.cpu.fetch.MiscStallCycles 25426 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
57system.cpu.fetch.PendingTrapStallCycles 259827 # Number of stall cycles due to pending traps
58system.cpu.fetch.CacheLines 183595750 # Number of cache lines fetched
59system.cpu.fetch.IcacheSquashes 3654130 # Number of outstanding Icache misses that were squashed
60system.cpu.fetch.rateDist::samples 907193017 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::mean 2.581432 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::stdev 3.385361 # Number of instructions fetched each cycle (Total)
| 49system.cpu.fetch.icacheStallCycles 187033735 # Number of cycles fetch is stalled on an Icache miss
50system.cpu.fetch.Insts 1232378576 # Number of instructions fetch has processed
51system.cpu.fetch.Branches 221451605 # Number of branches that fetch encountered
52system.cpu.fetch.predictedBranches 152744780 # Number of branches that fetch has predicted taken
53system.cpu.fetch.Cycles 382759458 # Number of cycles fetch has run and was not squashing or blocked
54system.cpu.fetch.SquashCycles 92090467 # Number of cycles fetch has spent squashing
55system.cpu.fetch.BlockedCycles 211510860 # Number of cycles fetch has spent blocked
56system.cpu.fetch.MiscStallCycles 30313 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
57system.cpu.fetch.PendingTrapStallCycles 293412 # Number of stall cycles due to pending traps
58system.cpu.fetch.CacheLines 179381043 # Number of cache lines fetched
59system.cpu.fetch.IcacheSquashes 4119516 # Number of outstanding Icache misses that were squashed
60system.cpu.fetch.rateDist::samples 859080204 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::mean 2.662810 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::stdev 3.408007 # Number of instructions fetched each cycle (Total)
|
63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
64system.cpu.fetch.rateDist::0 519485485 57.26% 57.26% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::1 25996327 2.87% 60.13% # Number of instructions fetched each cycle (Total)
66system.cpu.fetch.rateDist::2 29110749 3.21% 63.34% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::3 30309742 3.34% 66.68% # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::4 19641750 2.17% 68.84% # Number of instructions fetched each cycle (Total)
69system.cpu.fetch.rateDist::5 25638200 2.83% 71.67% # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.rateDist::6 32631023 3.60% 75.27% # Number of instructions fetched each cycle (Total)
71system.cpu.fetch.rateDist::7 30872435 3.40% 78.67% # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::8 193507306 21.33% 100.00% # Number of instructions fetched each cycle (Total)
| 64system.cpu.fetch.rateDist::0 480734760 55.96% 55.96% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::1 25482181 2.97% 58.93% # Number of instructions fetched each cycle (Total)
66system.cpu.fetch.rateDist::2 28110276 3.27% 62.20% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::3 29422032 3.42% 65.62% # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::4 18933642 2.20% 67.83% # Number of instructions fetched each cycle (Total)
69system.cpu.fetch.rateDist::5 25065200 2.92% 70.74% # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.rateDist::6 31695568 3.69% 74.43% # Number of instructions fetched each cycle (Total)
71system.cpu.fetch.rateDist::7 30727505 3.58% 78.01% # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::8 188909040 21.99% 100.00% # Number of instructions fetched each cycle (Total)
|
73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
76system.cpu.fetch.rateDist::total 907193017 # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.branchRate 0.245217 # Number of branch fetches per cycle
78system.cpu.fetch.rate 1.372002 # Number of inst fetches per cycle
79system.cpu.decode.IdleCycles 253820361 # Number of cycles decode is idle
80system.cpu.decode.BlockedCycles 190155093 # Number of cycles decode is blocked
81system.cpu.decode.RunCycles 329181376 # Number of cycles decode is running
82system.cpu.decode.UnblockCycles 50007304 # Number of cycles decode is unblocking
83system.cpu.decode.SquashCycles 84028883 # Number of cycles decode is squashing
84system.cpu.decode.DecodedInsts 2290797520 # Number of instructions handled by decode
85system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
86system.cpu.rename.SquashCycles 84028883 # Number of cycles rename is squashing
87system.cpu.rename.IdleCycles 290488558 # Number of cycles rename is idle
88system.cpu.rename.BlockCycles 45108603 # Number of cycles rename is blocking
89system.cpu.rename.serializeStallCycles 15221 # count of cycles rename stalled for serializing inst
90system.cpu.rename.RunCycles 340002879 # Number of cycles rename is running
91system.cpu.rename.UnblockCycles 147548873 # Number of cycles rename is unblocking
92system.cpu.rename.RenamedInsts 2240764057 # Number of instructions processed by rename
93system.cpu.rename.ROBFullEvents 2605 # Number of times rename has blocked due to ROB full
94system.cpu.rename.IQFullEvents 24418127 # Number of times rename has blocked due to IQ full
95system.cpu.rename.LSQFullEvents 107087338 # Number of times rename has blocked due to LSQ full
96system.cpu.rename.FullRegisterEvents 11838 # Number of times there has been no free registers
97system.cpu.rename.RenamedOperands 2887342076 # Number of destination operands rename has renamed
98system.cpu.rename.RenameLookups 6494384791 # Number of register rename lookups that rename has made
99system.cpu.rename.int_rename_lookups 6493512354 # Number of integer rename lookups
100system.cpu.rename.fp_rename_lookups 872437 # Number of floating rename lookups
101system.cpu.rename.CommittedMaps 1993077392 # Number of HB maps that are committed
102system.cpu.rename.UndoneMaps 894264684 # Number of HB maps that are undone due to squashing
103system.cpu.rename.serializingInsts 1272 # count of serializing insts renamed
104system.cpu.rename.tempSerializingInsts 1264 # count of temporary serializing insts renamed
105system.cpu.rename.skidInsts 351172253 # count of insts added to the skid buffer
106system.cpu.memDep0.insertedLoads 540287564 # Number of loads inserted to the mem dependence unit.
107system.cpu.memDep0.insertedStores 217471494 # Number of stores inserted to the mem dependence unit.
108system.cpu.memDep0.conflictingLoads 211537272 # Number of conflicting loads.
109system.cpu.memDep0.conflictingStores 61160620 # Number of conflicting stores.
110system.cpu.iq.iqInstsAdded 2143475674 # Number of instructions added to the IQ (excludes non-spec)
111system.cpu.iq.iqNonSpecInstsAdded 68305 # Number of non-speculative instructions added to the IQ
112system.cpu.iq.iqInstsIssued 1846648177 # Number of instructions issued
113system.cpu.iq.iqSquashedInstsIssued 1590040 # Number of squashed instructions issued
114system.cpu.iq.iqSquashedInstsExamined 612877032 # Number of squashed instructions iterated over during squash; mainly for profiling
115system.cpu.iq.iqSquashedOperandsExamined 1231244444 # Number of squashed operands that are examined and possibly removed from graph
116system.cpu.iq.iqSquashedNonSpecRemoved 67752 # Number of squashed non-spec instructions that were removed
117system.cpu.iq.issued_per_cycle::samples 907193017 # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::mean 2.035563 # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::stdev 1.801610 # Number of insts issued each cycle
| 76system.cpu.fetch.rateDist::total 859080204 # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.branchRate 0.255386 # Number of branch fetches per cycle
78system.cpu.fetch.rate 1.421225 # Number of inst fetches per cycle
79system.cpu.decode.IdleCycles 243920658 # Number of cycles decode is idle
80system.cpu.decode.BlockedCycles 168382016 # Number of cycles decode is blocked
81system.cpu.decode.RunCycles 324921479 # Number of cycles decode is running
82system.cpu.decode.UnblockCycles 44403625 # Number of cycles decode is unblocking
83system.cpu.decode.SquashCycles 77452426 # Number of cycles decode is squashing
84system.cpu.decode.DecodedInsts 2234163398 # Number of instructions handled by decode
85system.cpu.rename.SquashCycles 77452426 # Number of cycles rename is squashing
86system.cpu.rename.IdleCycles 277622568 # Number of cycles rename is idle
87system.cpu.rename.BlockCycles 38425038 # Number of cycles rename is blocking
88system.cpu.rename.serializeStallCycles 15999 # count of cycles rename stalled for serializing inst
89system.cpu.rename.RunCycles 333490253 # Number of cycles rename is running
90system.cpu.rename.UnblockCycles 132073920 # Number of cycles rename is unblocking
91system.cpu.rename.RenamedInsts 2182629484 # Number of instructions processed by rename
92system.cpu.rename.ROBFullEvents 24122 # Number of times rename has blocked due to ROB full
93system.cpu.rename.IQFullEvents 19618394 # Number of times rename has blocked due to IQ full
94system.cpu.rename.LSQFullEvents 98320386 # Number of times rename has blocked due to LSQ full
95system.cpu.rename.FullRegisterEvents 151 # Number of times there has been no free registers
96system.cpu.rename.RenamedOperands 2282631567 # Number of destination operands rename has renamed
97system.cpu.rename.RenameLookups 5519360713 # Number of register rename lookups that rename has made
98system.cpu.rename.int_rename_lookups 5519123398 # Number of integer rename lookups
99system.cpu.rename.fp_rename_lookups 237315 # Number of floating rename lookups
100system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed
101system.cpu.rename.UndoneMaps 668590716 # Number of HB maps that are undone due to squashing
102system.cpu.rename.serializingInsts 1589 # count of serializing insts renamed
103system.cpu.rename.tempSerializingInsts 1547 # count of temporary serializing insts renamed
104system.cpu.rename.skidInsts 322287185 # count of insts added to the skid buffer
105system.cpu.memDep0.insertedLoads 528399687 # Number of loads inserted to the mem dependence unit.
106system.cpu.memDep0.insertedStores 210789135 # Number of stores inserted to the mem dependence unit.
107system.cpu.memDep0.conflictingLoads 202484637 # Number of conflicting loads.
108system.cpu.memDep0.conflictingStores 58642789 # Number of conflicting stores.
109system.cpu.iq.iqInstsAdded 2088380391 # Number of instructions added to the IQ (excludes non-spec)
110system.cpu.iq.iqNonSpecInstsAdded 24636 # Number of non-speculative instructions added to the IQ
111system.cpu.iq.iqInstsIssued 1835578469 # Number of instructions issued
112system.cpu.iq.iqSquashedInstsIssued 977153 # Number of squashed instructions issued
113system.cpu.iq.iqSquashedInstsExamined 553508636 # Number of squashed instructions iterated over during squash; mainly for profiling
114system.cpu.iq.iqSquashedOperandsExamined 915245477 # Number of squashed operands that are examined and possibly removed from graph
115system.cpu.iq.iqSquashedNonSpecRemoved 24083 # Number of squashed non-spec instructions that were removed
116system.cpu.iq.issued_per_cycle::samples 859080204 # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::mean 2.136679 # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::stdev 1.890485 # Number of insts issued each cycle
|
120system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 119system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
121system.cpu.iq.issued_per_cycle::0 248716450 27.42% 27.42% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::1 159225433 17.55% 44.97% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::2 153829003 16.96% 61.92% # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::3 148683388 16.39% 78.31% # Number of insts issued each cycle
125system.cpu.iq.issued_per_cycle::4 98997552 10.91% 89.23% # Number of insts issued each cycle
126system.cpu.iq.issued_per_cycle::5 59757299 6.59% 95.81% # Number of insts issued each cycle
127system.cpu.iq.issued_per_cycle::6 27989930 3.09% 98.90% # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::7 8953405 0.99% 99.89% # Number of insts issued each cycle
129system.cpu.iq.issued_per_cycle::8 1040557 0.11% 100.00% # Number of insts issued each cycle
| 120system.cpu.iq.issued_per_cycle::0 233267501 27.15% 27.15% # Number of insts issued each cycle
121system.cpu.iq.issued_per_cycle::1 144027396 16.77% 43.92% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::2 136780566 15.92% 59.84% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::3 136553598 15.90% 75.74% # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::4 99295309 11.56% 87.29% # Number of insts issued each cycle
125system.cpu.iq.issued_per_cycle::5 59689212 6.95% 94.24% # Number of insts issued each cycle
126system.cpu.iq.issued_per_cycle::6 35426860 4.12% 98.37% # Number of insts issued each cycle
127system.cpu.iq.issued_per_cycle::7 12177405 1.42% 99.78% # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::8 1862357 0.22% 100.00% # Number of insts issued each cycle
|
130system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
131system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
132system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 129system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
130system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
131system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
133system.cpu.iq.issued_per_cycle::total 907193017 # Number of insts issued each cycle
| 132system.cpu.iq.issued_per_cycle::total 859080204 # Number of insts issued each cycle
|
134system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 133system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
135system.cpu.iq.fu_full::IntAlu 2618041 18.27% 18.27% # attempts to use FU when none available
136system.cpu.iq.fu_full::IntMult 0 0.00% 18.27% # attempts to use FU when none available
137system.cpu.iq.fu_full::IntDiv 0 0.00% 18.27% # attempts to use FU when none available
138system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.27% # attempts to use FU when none available
139system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.27% # attempts to use FU when none available
140system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.27% # attempts to use FU when none available
141system.cpu.iq.fu_full::FloatMult 0 0.00% 18.27% # attempts to use FU when none available
142system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.27% # attempts to use FU when none available
143system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.27% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.27% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.27% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.27% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.27% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.27% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.27% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdMult 0 0.00% 18.27% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.27% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdShift 0 0.00% 18.27% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.27% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.27% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.27% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.27% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.27% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.27% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.27% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.27% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.27% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.27% # attempts to use FU when none available
163system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.27% # attempts to use FU when none available
164system.cpu.iq.fu_full::MemRead 8472648 59.14% 77.41% # attempts to use FU when none available
165system.cpu.iq.fu_full::MemWrite 3236053 22.59% 100.00% # attempts to use FU when none available
| 134system.cpu.iq.fu_full::IntAlu 5022876 32.65% 32.65% # attempts to use FU when none available
135system.cpu.iq.fu_full::IntMult 0 0.00% 32.65% # attempts to use FU when none available
136system.cpu.iq.fu_full::IntDiv 0 0.00% 32.65% # attempts to use FU when none available
137system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.65% # attempts to use FU when none available
138system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.65% # attempts to use FU when none available
139system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.65% # attempts to use FU when none available
140system.cpu.iq.fu_full::FloatMult 0 0.00% 32.65% # attempts to use FU when none available
141system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.65% # attempts to use FU when none available
142system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.65% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.65% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.65% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.65% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.65% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.65% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.65% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdMult 0 0.00% 32.65% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.65% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdShift 0 0.00% 32.65% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.65% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.65% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.65% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.65% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.65% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.65% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.65% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.65% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.65% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.65% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.65% # attempts to use FU when none available
163system.cpu.iq.fu_full::MemRead 7731976 50.26% 82.91% # attempts to use FU when none available
164system.cpu.iq.fu_full::MemWrite 2628669 17.09% 100.00% # attempts to use FU when none available
|
166system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
167system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
| 165system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
166system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
168system.cpu.iq.FU_type_0::No_OpClass 2706611 0.15% 0.15% # Type of FU issued
169system.cpu.iq.FU_type_0::IntAlu 1219512996 66.04% 66.19% # Type of FU issued
170system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued
171system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued
172system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued
173system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.19% # Type of FU issued
174system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.19% # Type of FU issued
175system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.19% # Type of FU issued
176system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.19% # Type of FU issued
177system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.19% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.19% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.19% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.19% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.19% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.19% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.19% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.19% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.19% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.19% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.19% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued
197system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued
198system.cpu.iq.FU_type_0::MemRead 447033831 24.21% 90.39% # Type of FU issued
199system.cpu.iq.FU_type_0::MemWrite 177394739 9.61% 100.00% # Type of FU issued
| 167system.cpu.iq.FU_type_0::No_OpClass 2701218 0.15% 0.15% # Type of FU issued
168system.cpu.iq.FU_type_0::IntAlu 1210723498 65.96% 66.11% # Type of FU issued
169system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued
170system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued
171system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued
172system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued
173system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued
174system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued
175system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued
176system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued
197system.cpu.iq.FU_type_0::MemRead 444235410 24.20% 90.31% # Type of FU issued
198system.cpu.iq.FU_type_0::MemWrite 177918343 9.69% 100.00% # Type of FU issued
|
200system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
201system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 199system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
200system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
202system.cpu.iq.FU_type_0::total 1846648177 # Type of FU issued
203system.cpu.iq.rate 2.005495 # Inst issue rate
204system.cpu.iq.fu_busy_cnt 14326742 # FU busy when requested
205system.cpu.iq.fu_busy_rate 0.007758 # FU busy rate (busy events/executed inst)
206system.cpu.iq.int_inst_queue_reads 4616398570 # Number of integer instruction queue reads
207system.cpu.iq.int_inst_queue_writes 2756384375 # Number of integer instruction queue writes
208system.cpu.iq.int_inst_queue_wakeup_accesses 1806263116 # Number of integer instruction queue wakeup accesses
209system.cpu.iq.fp_inst_queue_reads 7583 # Number of floating instruction queue reads
210system.cpu.iq.fp_inst_queue_writes 297698 # Number of floating instruction queue writes
211system.cpu.iq.fp_inst_queue_wakeup_accesses 240 # Number of floating instruction queue wakeup accesses
212system.cpu.iq.int_alu_accesses 1858265657 # Number of integer alu accesses
213system.cpu.iq.fp_alu_accesses 2651 # Number of floating point alu accesses
214system.cpu.iew.lsq.thread0.forwLoads 168095723 # Number of loads that had data forwarded from stores
| 201system.cpu.iq.FU_type_0::total 1835578469 # Type of FU issued
202system.cpu.iq.rate 2.116857 # Inst issue rate
203system.cpu.iq.fu_busy_cnt 15383521 # FU busy when requested
204system.cpu.iq.fu_busy_rate 0.008381 # FU busy rate (busy events/executed inst)
205system.cpu.iq.int_inst_queue_reads 4546556112 # Number of integer instruction queue reads
206system.cpu.iq.int_inst_queue_writes 2642088218 # Number of integer instruction queue writes
207system.cpu.iq.int_inst_queue_wakeup_accesses 1793025560 # Number of integer instruction queue wakeup accesses
208system.cpu.iq.fp_inst_queue_reads 41704 # Number of floating instruction queue reads
209system.cpu.iq.fp_inst_queue_writes 79014 # Number of floating instruction queue writes
210system.cpu.iq.fp_inst_queue_wakeup_accesses 9750 # Number of floating instruction queue wakeup accesses
211system.cpu.iq.int_alu_accesses 1848241436 # Number of integer alu accesses
212system.cpu.iq.fp_alu_accesses 19336 # Number of floating point alu accesses
213system.cpu.iew.lsq.thread0.forwLoads 170057316 # Number of loads that had data forwarded from stores
|
215system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 214system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
216system.cpu.iew.lsq.thread0.squashedLoads 156185408 # Number of loads squashed
217system.cpu.iew.lsq.thread0.ignoredResponses 429800 # Number of memory responses ignored because the instruction is squashed
218system.cpu.iew.lsq.thread0.memOrderViolation 272503 # Number of memory ordering violations
219system.cpu.iew.lsq.thread0.squashedStores 68311550 # Number of stores squashed
| 215system.cpu.iew.lsq.thread0.squashedLoads 144297531 # Number of loads squashed
216system.cpu.iew.lsq.thread0.ignoredResponses 517217 # Number of memory responses ignored because the instruction is squashed
217system.cpu.iew.lsq.thread0.memOrderViolation 266012 # Number of memory ordering violations
218system.cpu.iew.lsq.thread0.squashedStores 61629484 # Number of stores squashed
|
220system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
221system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
| 219system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
220system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
222system.cpu.iew.lsq.thread0.rescheduledLoads 6430 # Number of loads that were rescheduled
223system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
| 221system.cpu.iew.lsq.thread0.rescheduledLoads 10771 # Number of loads that were rescheduled
222system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
|
224system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 223system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
225system.cpu.iew.iewSquashCycles 84028883 # Number of cycles IEW is squashing
226system.cpu.iew.iewBlockCycles 6582029 # Number of cycles IEW is blocking
227system.cpu.iew.iewUnblockCycles 1299784 # Number of cycles IEW is unblocking
228system.cpu.iew.iewDispatchedInsts 2143543979 # Number of instructions dispatched to IQ
229system.cpu.iew.iewDispSquashedInsts 2844739 # Number of squashed instructions skipped by dispatch
230system.cpu.iew.iewDispLoadInsts 540287564 # Number of dispatched load instructions
231system.cpu.iew.iewDispStoreInsts 217471735 # Number of dispatched store instructions
232system.cpu.iew.iewDispNonSpecInsts 5098 # Number of dispatched non-speculative instructions
233system.cpu.iew.iewIQFullEvents 982320 # Number of times the IQ has become full, causing a stall
234system.cpu.iew.iewLSQFullEvents 66743 # Number of times the LSQ has become full, causing a stall
235system.cpu.iew.memOrderViolationEvents 272503 # Number of memory order violations
236system.cpu.iew.predictedTakenIncorrect 10083086 # Number of branches that were predicted taken incorrectly
237system.cpu.iew.predictedNotTakenIncorrect 5258850 # Number of branches that were predicted not taken incorrectly
238system.cpu.iew.branchMispredicts 15341936 # Number of branch mispredicts detected at execute
239system.cpu.iew.iewExecutedInsts 1818766036 # Number of executed instructions
240system.cpu.iew.iewExecLoadInsts 438618649 # Number of load instructions executed
241system.cpu.iew.iewExecSquashedInsts 27882141 # Number of squashed instructions skipped in execute
| 224system.cpu.iew.iewSquashCycles 77452426 # Number of cycles IEW is squashing
225system.cpu.iew.iewBlockCycles 5095399 # Number of cycles IEW is blocking
226system.cpu.iew.iewUnblockCycles 776506 # Number of cycles IEW is unblocking
227system.cpu.iew.iewDispatchedInsts 2088405027 # Number of instructions dispatched to IQ
228system.cpu.iew.iewDispSquashedInsts 2538461 # Number of squashed instructions skipped by dispatch
229system.cpu.iew.iewDispLoadInsts 528399687 # Number of dispatched load instructions
230system.cpu.iew.iewDispStoreInsts 210789669 # Number of dispatched store instructions
231system.cpu.iew.iewDispNonSpecInsts 5336 # Number of dispatched non-speculative instructions
232system.cpu.iew.iewIQFullEvents 420481 # Number of times the IQ has become full, causing a stall
233system.cpu.iew.iewLSQFullEvents 70453 # Number of times the LSQ has become full, causing a stall
234system.cpu.iew.memOrderViolationEvents 266012 # Number of memory order violations
235system.cpu.iew.predictedTakenIncorrect 10035135 # Number of branches that were predicted taken incorrectly
236system.cpu.iew.predictedNotTakenIncorrect 4886780 # Number of branches that were predicted not taken incorrectly
237system.cpu.iew.branchMispredicts 14921915 # Number of branch mispredicts detected at execute
238system.cpu.iew.iewExecutedInsts 1805657318 # Number of executed instructions
239system.cpu.iew.iewExecLoadInsts 435939313 # Number of load instructions executed
240system.cpu.iew.iewExecSquashedInsts 29921151 # Number of squashed instructions skipped in execute
|
242system.cpu.iew.exec_swp 0 # number of swp insts executed
243system.cpu.iew.exec_nop 0 # number of nop insts executed
| 241system.cpu.iew.exec_swp 0 # number of swp insts executed
242system.cpu.iew.exec_nop 0 # number of nop insts executed
|
244system.cpu.iew.exec_refs 610454199 # number of memory reference insts executed
245system.cpu.iew.exec_branches 170875981 # Number of branches executed
246system.cpu.iew.exec_stores 171835550 # Number of stores executed
247system.cpu.iew.exec_rate 1.975215 # Inst execution rate
248system.cpu.iew.wb_sent 1813520986 # cumulative count of insts sent to commit
249system.cpu.iew.wb_count 1806263356 # cumulative count of insts written-back
250system.cpu.iew.wb_producers 1378693447 # num instructions producing a value
251system.cpu.iew.wb_consumers 2933323666 # num instructions consuming a value
| 243system.cpu.iew.exec_refs 608546299 # number of memory reference insts executed
244system.cpu.iew.exec_branches 171183701 # Number of branches executed
245system.cpu.iew.exec_stores 172606986 # Number of stores executed
246system.cpu.iew.exec_rate 2.082351 # Inst execution rate
247system.cpu.iew.wb_sent 1800375599 # cumulative count of insts sent to commit
248system.cpu.iew.wb_count 1793035310 # cumulative count of insts written-back
249system.cpu.iew.wb_producers 1362115146 # num instructions producing a value
250system.cpu.iew.wb_consumers 1993206857 # num instructions consuming a value
|
252system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 251system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
253system.cpu.iew.wb_rate 1.961637 # insts written-back per cycle
254system.cpu.iew.wb_fanout 0.470011 # average fanout of values written-back
| 252system.cpu.iew.wb_rate 2.067795 # insts written-back per cycle
253system.cpu.iew.wb_fanout 0.683379 # average fanout of values written-back
|
255system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
256system.cpu.commit.commitCommittedInsts 826877109 # The number of committed instructions
257system.cpu.commit.commitCommittedOps 1528988699 # The number of committed instructions
| 254system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
255system.cpu.commit.commitCommittedInsts 826877109 # The number of committed instructions
256system.cpu.commit.commitCommittedOps 1528988699 # The number of committed instructions
|
258system.cpu.commit.commitSquashedInsts 614579352 # The number of squashed insts skipped by commit
| 257system.cpu.commit.commitSquashedInsts 559448088 # The number of squashed insts skipped by commit
|
259system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
| 258system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
260system.cpu.commit.branchMispredicts 14336742 # The number of times a branch was mispredicted
261system.cpu.commit.committed_per_cycle::samples 823164134 # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::mean 1.857453 # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::stdev 2.320209 # Number of insts commited each cycle
| 259system.cpu.commit.branchMispredicts 14421135 # The number of times a branch was mispredicted
260system.cpu.commit.committed_per_cycle::samples 781627778 # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::mean 1.956160 # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::stdev 2.445660 # Number of insts commited each cycle
|
264system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 263system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
265system.cpu.commit.committed_per_cycle::0 305087340 37.06% 37.06% # Number of insts commited each cycle
266system.cpu.commit.committed_per_cycle::1 205283379 24.94% 62.00% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::2 74494797 9.05% 71.05% # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::3 96404931 11.71% 82.76% # Number of insts commited each cycle
269system.cpu.commit.committed_per_cycle::4 29976642 3.64% 86.40% # Number of insts commited each cycle
270system.cpu.commit.committed_per_cycle::5 28775074 3.50% 89.90% # Number of insts commited each cycle
271system.cpu.commit.committed_per_cycle::6 15838255 1.92% 91.82% # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::7 11740263 1.43% 93.25% # Number of insts commited each cycle
273system.cpu.commit.committed_per_cycle::8 55563453 6.75% 100.00% # Number of insts commited each cycle
| 264system.cpu.commit.committed_per_cycle::0 285492936 36.53% 36.53% # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::1 197198069 25.23% 61.75% # Number of insts commited each cycle
266system.cpu.commit.committed_per_cycle::2 62579121 8.01% 69.76% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::3 91937051 11.76% 81.52% # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::4 26882169 3.44% 84.96% # Number of insts commited each cycle
269system.cpu.commit.committed_per_cycle::5 29023123 3.71% 88.68% # Number of insts commited each cycle
270system.cpu.commit.committed_per_cycle::6 9810981 1.26% 89.93% # Number of insts commited each cycle
271system.cpu.commit.committed_per_cycle::7 10323566 1.32% 91.25% # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::8 68380762 8.75% 100.00% # Number of insts commited each cycle
|
274system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
275system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
276system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 273system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
274system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
275system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
277system.cpu.commit.committed_per_cycle::total 823164134 # Number of insts commited each cycle
| 276system.cpu.commit.committed_per_cycle::total 781627778 # Number of insts commited each cycle
|
278system.cpu.commit.committedInsts 826877109 # Number of instructions committed
279system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed
280system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
281system.cpu.commit.refs 533262341 # Number of memory references committed
282system.cpu.commit.loads 384102156 # Number of loads committed
283system.cpu.commit.membars 0 # Number of memory barriers committed
284system.cpu.commit.branches 149758583 # Number of branches committed
285system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
286system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions.
287system.cpu.commit.function_calls 0 # Number of function calls committed.
| 277system.cpu.commit.committedInsts 826877109 # Number of instructions committed
278system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed
279system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
280system.cpu.commit.refs 533262341 # Number of memory references committed
281system.cpu.commit.loads 384102156 # Number of loads committed
282system.cpu.commit.membars 0 # Number of memory barriers committed
283system.cpu.commit.branches 149758583 # Number of branches committed
284system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
285system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions.
286system.cpu.commit.function_calls 0 # Number of function calls committed.
|
288system.cpu.commit.bw_lim_events 55563453 # number cycles where commit BW limit reached
| 287system.cpu.commit.bw_lim_events 68380762 # number cycles where commit BW limit reached
|
289system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 288system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
290system.cpu.rob.rob_reads 2911168732 # The number of ROB reads
291system.cpu.rob.rob_writes 4371280103 # The number of ROB writes
292system.cpu.timesIdled 309541 # Number of times that the entire CPU went into an idle state and unscheduled itself
293system.cpu.idleCycles 13600990 # Total number of cycles that the CPU has spent unscheduled due to idling
| 289system.cpu.rob.rob_reads 2801683803 # The number of ROB reads
290system.cpu.rob.rob_writes 4254544815 # The number of ROB writes
291system.cpu.timesIdled 198794 # Number of times that the entire CPU went into an idle state and unscheduled itself
292system.cpu.idleCycles 8044270 # Total number of cycles that the CPU has spent unscheduled due to idling
|
294system.cpu.committedInsts 826877109 # Number of Instructions Simulated
295system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated
296system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
| 293system.cpu.committedInsts 826877109 # Number of Instructions Simulated
294system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated
295system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
|
297system.cpu.cpi 1.113580 # CPI: Cycles Per Instruction
298system.cpu.cpi_total 1.113580 # CPI: Total CPI of All Threads
299system.cpu.ipc 0.898004 # IPC: Instructions Per Cycle
300system.cpu.ipc_total 0.898004 # IPC: Total IPC of All Threads
301system.cpu.int_regfile_reads 4004208844 # number of integer regfile reads
302system.cpu.int_regfile_writes 2286339718 # number of integer regfile writes
303system.cpu.fp_regfile_reads 238 # number of floating regfile reads
| 296system.cpu.cpi 1.048674 # CPI: Cycles Per Instruction
297system.cpu.cpi_total 1.048674 # CPI: Total CPI of All Threads
298system.cpu.ipc 0.953585 # IPC: Instructions Per Cycle
299system.cpu.ipc_total 0.953585 # IPC: Total IPC of All Threads
300system.cpu.int_regfile_reads 3391389205 # number of integer regfile reads
301system.cpu.int_regfile_writes 1872893526 # number of integer regfile writes
302system.cpu.fp_regfile_reads 9748 # number of floating regfile reads
|
304system.cpu.fp_regfile_writes 2 # number of floating regfile writes
| 303system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
305system.cpu.misc_regfile_reads 1001924846 # number of misc regfile reads
306system.cpu.icache.replacements 5564 # number of replacements
307system.cpu.icache.tagsinuse 1044.277661 # Cycle average of tags in use
308system.cpu.icache.total_refs 183360161 # Total number of references to valid blocks.
309system.cpu.icache.sampled_refs 7185 # Sample count of references to valid blocks.
310system.cpu.icache.avg_refs 25519.855393 # Average number of references to valid blocks.
| 304system.cpu.misc_regfile_reads 993246616 # number of misc regfile reads
305system.cpu.icache.replacements 5750 # number of replacements
306system.cpu.icache.tagsinuse 1040.901542 # Cycle average of tags in use
307system.cpu.icache.total_refs 179166863 # Total number of references to valid blocks.
308system.cpu.icache.sampled_refs 7354 # Sample count of references to valid blocks.
309system.cpu.icache.avg_refs 24363.185069 # Average number of references to valid blocks.
|
311system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 310system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
312system.cpu.icache.occ_blocks::cpu.inst 1044.277661 # Average occupied blocks per requestor
313system.cpu.icache.occ_percent::cpu.inst 0.509901 # Average percentage of cache occupancy
314system.cpu.icache.occ_percent::total 0.509901 # Average percentage of cache occupancy
315system.cpu.icache.ReadReq_hits::cpu.inst 183377049 # number of ReadReq hits
316system.cpu.icache.ReadReq_hits::total 183377049 # number of ReadReq hits
317system.cpu.icache.demand_hits::cpu.inst 183377049 # number of demand (read+write) hits
318system.cpu.icache.demand_hits::total 183377049 # number of demand (read+write) hits
319system.cpu.icache.overall_hits::cpu.inst 183377049 # number of overall hits
320system.cpu.icache.overall_hits::total 183377049 # number of overall hits
321system.cpu.icache.ReadReq_misses::cpu.inst 218701 # number of ReadReq misses
322system.cpu.icache.ReadReq_misses::total 218701 # number of ReadReq misses
323system.cpu.icache.demand_misses::cpu.inst 218701 # number of demand (read+write) misses
324system.cpu.icache.demand_misses::total 218701 # number of demand (read+write) misses
325system.cpu.icache.overall_misses::cpu.inst 218701 # number of overall misses
326system.cpu.icache.overall_misses::total 218701 # number of overall misses
327system.cpu.icache.ReadReq_miss_latency::cpu.inst 1530978500 # number of ReadReq miss cycles
328system.cpu.icache.ReadReq_miss_latency::total 1530978500 # number of ReadReq miss cycles
329system.cpu.icache.demand_miss_latency::cpu.inst 1530978500 # number of demand (read+write) miss cycles
330system.cpu.icache.demand_miss_latency::total 1530978500 # number of demand (read+write) miss cycles
331system.cpu.icache.overall_miss_latency::cpu.inst 1530978500 # number of overall miss cycles
332system.cpu.icache.overall_miss_latency::total 1530978500 # number of overall miss cycles
333system.cpu.icache.ReadReq_accesses::cpu.inst 183595750 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.ReadReq_accesses::total 183595750 # number of ReadReq accesses(hits+misses)
335system.cpu.icache.demand_accesses::cpu.inst 183595750 # number of demand (read+write) accesses
336system.cpu.icache.demand_accesses::total 183595750 # number of demand (read+write) accesses
337system.cpu.icache.overall_accesses::cpu.inst 183595750 # number of overall (read+write) accesses
338system.cpu.icache.overall_accesses::total 183595750 # number of overall (read+write) accesses
339system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001191 # miss rate for ReadReq accesses
340system.cpu.icache.ReadReq_miss_rate::total 0.001191 # miss rate for ReadReq accesses
341system.cpu.icache.demand_miss_rate::cpu.inst 0.001191 # miss rate for demand accesses
342system.cpu.icache.demand_miss_rate::total 0.001191 # miss rate for demand accesses
343system.cpu.icache.overall_miss_rate::cpu.inst 0.001191 # miss rate for overall accesses
344system.cpu.icache.overall_miss_rate::total 0.001191 # miss rate for overall accesses
345system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7000.326930 # average ReadReq miss latency
346system.cpu.icache.ReadReq_avg_miss_latency::total 7000.326930 # average ReadReq miss latency
347system.cpu.icache.demand_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency
348system.cpu.icache.demand_avg_miss_latency::total 7000.326930 # average overall miss latency
349system.cpu.icache.overall_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency
350system.cpu.icache.overall_avg_miss_latency::total 7000.326930 # average overall miss latency
| 311system.cpu.icache.occ_blocks::cpu.inst 1040.901542 # Average occupied blocks per requestor
312system.cpu.icache.occ_percent::cpu.inst 0.508253 # Average percentage of cache occupancy
313system.cpu.icache.occ_percent::total 0.508253 # Average percentage of cache occupancy
314system.cpu.icache.ReadReq_hits::cpu.inst 179183149 # number of ReadReq hits
315system.cpu.icache.ReadReq_hits::total 179183149 # number of ReadReq hits
316system.cpu.icache.demand_hits::cpu.inst 179183149 # number of demand (read+write) hits
317system.cpu.icache.demand_hits::total 179183149 # number of demand (read+write) hits
318system.cpu.icache.overall_hits::cpu.inst 179183149 # number of overall hits
319system.cpu.icache.overall_hits::total 179183149 # number of overall hits
320system.cpu.icache.ReadReq_misses::cpu.inst 197894 # number of ReadReq misses
321system.cpu.icache.ReadReq_misses::total 197894 # number of ReadReq misses
322system.cpu.icache.demand_misses::cpu.inst 197894 # number of demand (read+write) misses
323system.cpu.icache.demand_misses::total 197894 # number of demand (read+write) misses
324system.cpu.icache.overall_misses::cpu.inst 197894 # number of overall misses
325system.cpu.icache.overall_misses::total 197894 # number of overall misses
326system.cpu.icache.ReadReq_miss_latency::cpu.inst 1518962500 # number of ReadReq miss cycles
327system.cpu.icache.ReadReq_miss_latency::total 1518962500 # number of ReadReq miss cycles
328system.cpu.icache.demand_miss_latency::cpu.inst 1518962500 # number of demand (read+write) miss cycles
329system.cpu.icache.demand_miss_latency::total 1518962500 # number of demand (read+write) miss cycles
330system.cpu.icache.overall_miss_latency::cpu.inst 1518962500 # number of overall miss cycles
331system.cpu.icache.overall_miss_latency::total 1518962500 # number of overall miss cycles
332system.cpu.icache.ReadReq_accesses::cpu.inst 179381043 # number of ReadReq accesses(hits+misses)
333system.cpu.icache.ReadReq_accesses::total 179381043 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.demand_accesses::cpu.inst 179381043 # number of demand (read+write) accesses
335system.cpu.icache.demand_accesses::total 179381043 # number of demand (read+write) accesses
336system.cpu.icache.overall_accesses::cpu.inst 179381043 # number of overall (read+write) accesses
337system.cpu.icache.overall_accesses::total 179381043 # number of overall (read+write) accesses
338system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001103 # miss rate for ReadReq accesses
339system.cpu.icache.ReadReq_miss_rate::total 0.001103 # miss rate for ReadReq accesses
340system.cpu.icache.demand_miss_rate::cpu.inst 0.001103 # miss rate for demand accesses
341system.cpu.icache.demand_miss_rate::total 0.001103 # miss rate for demand accesses
342system.cpu.icache.overall_miss_rate::cpu.inst 0.001103 # miss rate for overall accesses
343system.cpu.icache.overall_miss_rate::total 0.001103 # miss rate for overall accesses
344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7675.636957 # average ReadReq miss latency
345system.cpu.icache.ReadReq_avg_miss_latency::total 7675.636957 # average ReadReq miss latency
346system.cpu.icache.demand_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency
347system.cpu.icache.demand_avg_miss_latency::total 7675.636957 # average overall miss latency
348system.cpu.icache.overall_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency
349system.cpu.icache.overall_avg_miss_latency::total 7675.636957 # average overall miss latency
|
351system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
352system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
353system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
354system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
355system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
356system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
357system.cpu.icache.fast_writes 0 # number of fast writes performed
358system.cpu.icache.cache_copies 0 # number of cache copies performed
| 350system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
351system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
352system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
353system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
354system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
355system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
356system.cpu.icache.fast_writes 0 # number of fast writes performed
357system.cpu.icache.cache_copies 0 # number of cache copies performed
|
359system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1667 # number of ReadReq MSHR hits
360system.cpu.icache.ReadReq_mshr_hits::total 1667 # number of ReadReq MSHR hits
361system.cpu.icache.demand_mshr_hits::cpu.inst 1667 # number of demand (read+write) MSHR hits
362system.cpu.icache.demand_mshr_hits::total 1667 # number of demand (read+write) MSHR hits
363system.cpu.icache.overall_mshr_hits::cpu.inst 1667 # number of overall MSHR hits
364system.cpu.icache.overall_mshr_hits::total 1667 # number of overall MSHR hits
365system.cpu.icache.ReadReq_mshr_misses::cpu.inst 217034 # number of ReadReq MSHR misses
366system.cpu.icache.ReadReq_mshr_misses::total 217034 # number of ReadReq MSHR misses
367system.cpu.icache.demand_mshr_misses::cpu.inst 217034 # number of demand (read+write) MSHR misses
368system.cpu.icache.demand_mshr_misses::total 217034 # number of demand (read+write) MSHR misses
369system.cpu.icache.overall_mshr_misses::cpu.inst 217034 # number of overall MSHR misses
370system.cpu.icache.overall_mshr_misses::total 217034 # number of overall MSHR misses
371system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 795818000 # number of ReadReq MSHR miss cycles
372system.cpu.icache.ReadReq_mshr_miss_latency::total 795818000 # number of ReadReq MSHR miss cycles
373system.cpu.icache.demand_mshr_miss_latency::cpu.inst 795818000 # number of demand (read+write) MSHR miss cycles
374system.cpu.icache.demand_mshr_miss_latency::total 795818000 # number of demand (read+write) MSHR miss cycles
375system.cpu.icache.overall_mshr_miss_latency::cpu.inst 795818000 # number of overall MSHR miss cycles
376system.cpu.icache.overall_mshr_miss_latency::total 795818000 # number of overall MSHR miss cycles
377system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for ReadReq accesses
378system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001182 # mshr miss rate for ReadReq accesses
379system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for demand accesses
380system.cpu.icache.demand_mshr_miss_rate::total 0.001182 # mshr miss rate for demand accesses
381system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for overall accesses
382system.cpu.icache.overall_mshr_miss_rate::total 0.001182 # mshr miss rate for overall accesses
383system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3666.789535 # average ReadReq mshr miss latency
384system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3666.789535 # average ReadReq mshr miss latency
385system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency
386system.cpu.icache.demand_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency
387system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency
388system.cpu.icache.overall_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency
| 358system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1612 # number of ReadReq MSHR hits
359system.cpu.icache.ReadReq_mshr_hits::total 1612 # number of ReadReq MSHR hits
360system.cpu.icache.demand_mshr_hits::cpu.inst 1612 # number of demand (read+write) MSHR hits
361system.cpu.icache.demand_mshr_hits::total 1612 # number of demand (read+write) MSHR hits
362system.cpu.icache.overall_mshr_hits::cpu.inst 1612 # number of overall MSHR hits
363system.cpu.icache.overall_mshr_hits::total 1612 # number of overall MSHR hits
364system.cpu.icache.ReadReq_mshr_misses::cpu.inst 196282 # number of ReadReq MSHR misses
365system.cpu.icache.ReadReq_mshr_misses::total 196282 # number of ReadReq MSHR misses
366system.cpu.icache.demand_mshr_misses::cpu.inst 196282 # number of demand (read+write) MSHR misses
367system.cpu.icache.demand_mshr_misses::total 196282 # number of demand (read+write) MSHR misses
368system.cpu.icache.overall_mshr_misses::cpu.inst 196282 # number of overall MSHR misses
369system.cpu.icache.overall_mshr_misses::total 196282 # number of overall MSHR misses
370system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 850572000 # number of ReadReq MSHR miss cycles
371system.cpu.icache.ReadReq_mshr_miss_latency::total 850572000 # number of ReadReq MSHR miss cycles
372system.cpu.icache.demand_mshr_miss_latency::cpu.inst 850572000 # number of demand (read+write) MSHR miss cycles
373system.cpu.icache.demand_mshr_miss_latency::total 850572000 # number of demand (read+write) MSHR miss cycles
374system.cpu.icache.overall_mshr_miss_latency::cpu.inst 850572000 # number of overall MSHR miss cycles
375system.cpu.icache.overall_mshr_miss_latency::total 850572000 # number of overall MSHR miss cycles
376system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for ReadReq accesses
377system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001094 # mshr miss rate for ReadReq accesses
378system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for demand accesses
379system.cpu.icache.demand_mshr_miss_rate::total 0.001094 # mshr miss rate for demand accesses
380system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for overall accesses
381system.cpu.icache.overall_mshr_miss_rate::total 0.001094 # mshr miss rate for overall accesses
382system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4333.418245 # average ReadReq mshr miss latency
383system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4333.418245 # average ReadReq mshr miss latency
384system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency
385system.cpu.icache.demand_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency
386system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency
387system.cpu.icache.overall_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency
|
389system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 388system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
390system.cpu.dcache.replacements 2526946 # number of replacements
391system.cpu.dcache.tagsinuse 4087.012033 # Cycle average of tags in use
392system.cpu.dcache.total_refs 415079459 # Total number of references to valid blocks.
393system.cpu.dcache.sampled_refs 2531042 # Sample count of references to valid blocks.
394system.cpu.dcache.avg_refs 163.995484 # Average number of references to valid blocks.
395system.cpu.dcache.warmup_cycle 2118352000 # Cycle when the warmup percentage was hit.
396system.cpu.dcache.occ_blocks::cpu.data 4087.012033 # Average occupied blocks per requestor
397system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy
398system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy
399system.cpu.dcache.ReadReq_hits::cpu.data 266229970 # number of ReadReq hits
400system.cpu.dcache.ReadReq_hits::total 266229970 # number of ReadReq hits
401system.cpu.dcache.WriteReq_hits::cpu.data 148176522 # number of WriteReq hits
402system.cpu.dcache.WriteReq_hits::total 148176522 # number of WriteReq hits
403system.cpu.dcache.demand_hits::cpu.data 414406492 # number of demand (read+write) hits
404system.cpu.dcache.demand_hits::total 414406492 # number of demand (read+write) hits
405system.cpu.dcache.overall_hits::cpu.data 414406492 # number of overall hits
406system.cpu.dcache.overall_hits::total 414406492 # number of overall hits
407system.cpu.dcache.ReadReq_misses::cpu.data 2652987 # number of ReadReq misses
408system.cpu.dcache.ReadReq_misses::total 2652987 # number of ReadReq misses
409system.cpu.dcache.WriteReq_misses::cpu.data 983679 # number of WriteReq misses
410system.cpu.dcache.WriteReq_misses::total 983679 # number of WriteReq misses
411system.cpu.dcache.demand_misses::cpu.data 3636666 # number of demand (read+write) misses
412system.cpu.dcache.demand_misses::total 3636666 # number of demand (read+write) misses
413system.cpu.dcache.overall_misses::cpu.data 3636666 # number of overall misses
414system.cpu.dcache.overall_misses::total 3636666 # number of overall misses
415system.cpu.dcache.ReadReq_miss_latency::cpu.data 36715559000 # number of ReadReq miss cycles
416system.cpu.dcache.ReadReq_miss_latency::total 36715559000 # number of ReadReq miss cycles
417system.cpu.dcache.WriteReq_miss_latency::cpu.data 18841751000 # number of WriteReq miss cycles
418system.cpu.dcache.WriteReq_miss_latency::total 18841751000 # number of WriteReq miss cycles
419system.cpu.dcache.demand_miss_latency::cpu.data 55557310000 # number of demand (read+write) miss cycles
420system.cpu.dcache.demand_miss_latency::total 55557310000 # number of demand (read+write) miss cycles
421system.cpu.dcache.overall_miss_latency::cpu.data 55557310000 # number of overall miss cycles
422system.cpu.dcache.overall_miss_latency::total 55557310000 # number of overall miss cycles
423system.cpu.dcache.ReadReq_accesses::cpu.data 268882957 # number of ReadReq accesses(hits+misses)
424system.cpu.dcache.ReadReq_accesses::total 268882957 # number of ReadReq accesses(hits+misses)
| 389system.cpu.dcache.replacements 2529239 # number of replacements
390system.cpu.dcache.tagsinuse 4087.824868 # Cycle average of tags in use
391system.cpu.dcache.total_refs 410277951 # Total number of references to valid blocks.
392system.cpu.dcache.sampled_refs 2533335 # Sample count of references to valid blocks.
393system.cpu.dcache.avg_refs 161.951716 # Average number of references to valid blocks.
394system.cpu.dcache.warmup_cycle 1779749000 # Cycle when the warmup percentage was hit.
395system.cpu.dcache.occ_blocks::cpu.data 4087.824868 # Average occupied blocks per requestor
396system.cpu.dcache.occ_percent::cpu.data 0.998004 # Average percentage of cache occupancy
397system.cpu.dcache.occ_percent::total 0.998004 # Average percentage of cache occupancy
398system.cpu.dcache.ReadReq_hits::cpu.data 261532697 # number of ReadReq hits
399system.cpu.dcache.ReadReq_hits::total 261532697 # number of ReadReq hits
400system.cpu.dcache.WriteReq_hits::cpu.data 148197019 # number of WriteReq hits
401system.cpu.dcache.WriteReq_hits::total 148197019 # number of WriteReq hits
402system.cpu.dcache.demand_hits::cpu.data 409729716 # number of demand (read+write) hits
403system.cpu.dcache.demand_hits::total 409729716 # number of demand (read+write) hits
404system.cpu.dcache.overall_hits::cpu.data 409729716 # number of overall hits
405system.cpu.dcache.overall_hits::total 409729716 # number of overall hits
406system.cpu.dcache.ReadReq_misses::cpu.data 2781068 # number of ReadReq misses
407system.cpu.dcache.ReadReq_misses::total 2781068 # number of ReadReq misses
408system.cpu.dcache.WriteReq_misses::cpu.data 963182 # number of WriteReq misses
409system.cpu.dcache.WriteReq_misses::total 963182 # number of WriteReq misses
410system.cpu.dcache.demand_misses::cpu.data 3744250 # number of demand (read+write) misses
411system.cpu.dcache.demand_misses::total 3744250 # number of demand (read+write) misses
412system.cpu.dcache.overall_misses::cpu.data 3744250 # number of overall misses
413system.cpu.dcache.overall_misses::total 3744250 # number of overall misses
414system.cpu.dcache.ReadReq_miss_latency::cpu.data 36062982500 # number of ReadReq miss cycles
415system.cpu.dcache.ReadReq_miss_latency::total 36062982500 # number of ReadReq miss cycles
416system.cpu.dcache.WriteReq_miss_latency::cpu.data 18107985000 # number of WriteReq miss cycles
417system.cpu.dcache.WriteReq_miss_latency::total 18107985000 # number of WriteReq miss cycles
418system.cpu.dcache.demand_miss_latency::cpu.data 54170967500 # number of demand (read+write) miss cycles
419system.cpu.dcache.demand_miss_latency::total 54170967500 # number of demand (read+write) miss cycles
420system.cpu.dcache.overall_miss_latency::cpu.data 54170967500 # number of overall miss cycles
421system.cpu.dcache.overall_miss_latency::total 54170967500 # number of overall miss cycles
422system.cpu.dcache.ReadReq_accesses::cpu.data 264313765 # number of ReadReq accesses(hits+misses)
423system.cpu.dcache.ReadReq_accesses::total 264313765 # number of ReadReq accesses(hits+misses)
|
425system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
426system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
| 424system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
425system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
427system.cpu.dcache.demand_accesses::cpu.data 418043158 # number of demand (read+write) accesses
428system.cpu.dcache.demand_accesses::total 418043158 # number of demand (read+write) accesses
429system.cpu.dcache.overall_accesses::cpu.data 418043158 # number of overall (read+write) accesses
430system.cpu.dcache.overall_accesses::total 418043158 # number of overall (read+write) accesses
431system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009867 # miss rate for ReadReq accesses
432system.cpu.dcache.ReadReq_miss_rate::total 0.009867 # miss rate for ReadReq accesses
433system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006595 # miss rate for WriteReq accesses
434system.cpu.dcache.WriteReq_miss_rate::total 0.006595 # miss rate for WriteReq accesses
435system.cpu.dcache.demand_miss_rate::cpu.data 0.008699 # miss rate for demand accesses
436system.cpu.dcache.demand_miss_rate::total 0.008699 # miss rate for demand accesses
437system.cpu.dcache.overall_miss_rate::cpu.data 0.008699 # miss rate for overall accesses
438system.cpu.dcache.overall_miss_rate::total 0.008699 # miss rate for overall accesses
439system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13839.328651 # average ReadReq miss latency
440system.cpu.dcache.ReadReq_avg_miss_latency::total 13839.328651 # average ReadReq miss latency
441system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19154.369464 # average WriteReq miss latency
442system.cpu.dcache.WriteReq_avg_miss_latency::total 19154.369464 # average WriteReq miss latency
443system.cpu.dcache.demand_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency
444system.cpu.dcache.demand_avg_miss_latency::total 15276.989968 # average overall miss latency
445system.cpu.dcache.overall_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency
446system.cpu.dcache.overall_avg_miss_latency::total 15276.989968 # average overall miss latency
| 426system.cpu.dcache.demand_accesses::cpu.data 413473966 # number of demand (read+write) accesses
427system.cpu.dcache.demand_accesses::total 413473966 # number of demand (read+write) accesses
428system.cpu.dcache.overall_accesses::cpu.data 413473966 # number of overall (read+write) accesses
429system.cpu.dcache.overall_accesses::total 413473966 # number of overall (read+write) accesses
430system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010522 # miss rate for ReadReq accesses
431system.cpu.dcache.ReadReq_miss_rate::total 0.010522 # miss rate for ReadReq accesses
432system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006457 # miss rate for WriteReq accesses
433system.cpu.dcache.WriteReq_miss_rate::total 0.006457 # miss rate for WriteReq accesses
434system.cpu.dcache.demand_miss_rate::cpu.data 0.009056 # miss rate for demand accesses
435system.cpu.dcache.demand_miss_rate::total 0.009056 # miss rate for demand accesses
436system.cpu.dcache.overall_miss_rate::cpu.data 0.009056 # miss rate for overall accesses
437system.cpu.dcache.overall_miss_rate::total 0.009056 # miss rate for overall accesses
438system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12967.314176 # average ReadReq miss latency
439system.cpu.dcache.ReadReq_avg_miss_latency::total 12967.314176 # average ReadReq miss latency
440system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18800.169646 # average WriteReq miss latency
441system.cpu.dcache.WriteReq_avg_miss_latency::total 18800.169646 # average WriteReq miss latency
442system.cpu.dcache.demand_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency
443system.cpu.dcache.demand_avg_miss_latency::total 14467.775255 # average overall miss latency
444system.cpu.dcache.overall_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency
445system.cpu.dcache.overall_avg_miss_latency::total 14467.775255 # average overall miss latency
|
447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
453system.cpu.dcache.fast_writes 0 # number of fast writes performed
454system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
450system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
452system.cpu.dcache.fast_writes 0 # number of fast writes performed
453system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
455system.cpu.dcache.writebacks::writebacks 2302737 # number of writebacks
456system.cpu.dcache.writebacks::total 2302737 # number of writebacks
457system.cpu.dcache.ReadReq_mshr_hits::cpu.data 892793 # number of ReadReq MSHR hits
458system.cpu.dcache.ReadReq_mshr_hits::total 892793 # number of ReadReq MSHR hits
459system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3022 # number of WriteReq MSHR hits
460system.cpu.dcache.WriteReq_mshr_hits::total 3022 # number of WriteReq MSHR hits
461system.cpu.dcache.demand_mshr_hits::cpu.data 895815 # number of demand (read+write) MSHR hits
462system.cpu.dcache.demand_mshr_hits::total 895815 # number of demand (read+write) MSHR hits
463system.cpu.dcache.overall_mshr_hits::cpu.data 895815 # number of overall MSHR hits
464system.cpu.dcache.overall_mshr_hits::total 895815 # number of overall MSHR hits
465system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760194 # number of ReadReq MSHR misses
466system.cpu.dcache.ReadReq_mshr_misses::total 1760194 # number of ReadReq MSHR misses
467system.cpu.dcache.WriteReq_mshr_misses::cpu.data 980657 # number of WriteReq MSHR misses
468system.cpu.dcache.WriteReq_mshr_misses::total 980657 # number of WriteReq MSHR misses
469system.cpu.dcache.demand_mshr_misses::cpu.data 2740851 # number of demand (read+write) MSHR misses
470system.cpu.dcache.demand_mshr_misses::total 2740851 # number of demand (read+write) MSHR misses
471system.cpu.dcache.overall_mshr_misses::cpu.data 2740851 # number of overall MSHR misses
472system.cpu.dcache.overall_mshr_misses::total 2740851 # number of overall MSHR misses
473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12492277176 # number of ReadReq MSHR miss cycles
474system.cpu.dcache.ReadReq_mshr_miss_latency::total 12492277176 # number of ReadReq MSHR miss cycles
475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15700711503 # number of WriteReq MSHR miss cycles
476system.cpu.dcache.WriteReq_mshr_miss_latency::total 15700711503 # number of WriteReq MSHR miss cycles
477system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28192988679 # number of demand (read+write) MSHR miss cycles
478system.cpu.dcache.demand_mshr_miss_latency::total 28192988679 # number of demand (read+write) MSHR miss cycles
479system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28192988679 # number of overall MSHR miss cycles
480system.cpu.dcache.overall_mshr_miss_latency::total 28192988679 # number of overall MSHR miss cycles
481system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006546 # mshr miss rate for ReadReq accesses
482system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006546 # mshr miss rate for ReadReq accesses
483system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006575 # mshr miss rate for WriteReq accesses
484system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006575 # mshr miss rate for WriteReq accesses
485system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
486system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses
487system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
488system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses
489system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7097.102465 # average ReadReq mshr miss latency
490system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7097.102465 # average ReadReq mshr miss latency
491system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16010.400683 # average WriteReq mshr miss latency
492system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16010.400683 # average WriteReq mshr miss latency
493system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10286.217193 # average overall mshr miss latency
494system.cpu.dcache.demand_avg_mshr_miss_latency::total 10286.217193 # average overall mshr miss latency
495system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10286.217193 # average overall mshr miss latency
496system.cpu.dcache.overall_avg_mshr_miss_latency::total 10286.217193 # average overall mshr miss latency
| 454system.cpu.dcache.writebacks::writebacks 2304434 # number of writebacks
455system.cpu.dcache.writebacks::total 2304434 # number of writebacks
456system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018833 # number of ReadReq MSHR hits
457system.cpu.dcache.ReadReq_mshr_hits::total 1018833 # number of ReadReq MSHR hits
458system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3201 # number of WriteReq MSHR hits
459system.cpu.dcache.WriteReq_mshr_hits::total 3201 # number of WriteReq MSHR hits
460system.cpu.dcache.demand_mshr_hits::cpu.data 1022034 # number of demand (read+write) MSHR hits
461system.cpu.dcache.demand_mshr_hits::total 1022034 # number of demand (read+write) MSHR hits
462system.cpu.dcache.overall_mshr_hits::cpu.data 1022034 # number of overall MSHR hits
463system.cpu.dcache.overall_mshr_hits::total 1022034 # number of overall MSHR hits
464system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762235 # number of ReadReq MSHR misses
465system.cpu.dcache.ReadReq_mshr_misses::total 1762235 # number of ReadReq MSHR misses
466system.cpu.dcache.WriteReq_mshr_misses::cpu.data 959981 # number of WriteReq MSHR misses
467system.cpu.dcache.WriteReq_mshr_misses::total 959981 # number of WriteReq MSHR misses
468system.cpu.dcache.demand_mshr_misses::cpu.data 2722216 # number of demand (read+write) MSHR misses
469system.cpu.dcache.demand_mshr_misses::total 2722216 # number of demand (read+write) MSHR misses
470system.cpu.dcache.overall_mshr_misses::cpu.data 2722216 # number of overall MSHR misses
471system.cpu.dcache.overall_mshr_misses::total 2722216 # number of overall MSHR misses
472system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12600404545 # number of ReadReq MSHR miss cycles
473system.cpu.dcache.ReadReq_mshr_miss_latency::total 12600404545 # number of ReadReq MSHR miss cycles
474system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15024414005 # number of WriteReq MSHR miss cycles
475system.cpu.dcache.WriteReq_mshr_miss_latency::total 15024414005 # number of WriteReq MSHR miss cycles
476system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27624818550 # number of demand (read+write) MSHR miss cycles
477system.cpu.dcache.demand_mshr_miss_latency::total 27624818550 # number of demand (read+write) MSHR miss cycles
478system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27624818550 # number of overall MSHR miss cycles
479system.cpu.dcache.overall_mshr_miss_latency::total 27624818550 # number of overall MSHR miss cycles
480system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006667 # mshr miss rate for ReadReq accesses
481system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006667 # mshr miss rate for ReadReq accesses
482system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006436 # mshr miss rate for WriteReq accesses
483system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006436 # mshr miss rate for WriteReq accesses
484system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for demand accesses
485system.cpu.dcache.demand_mshr_miss_rate::total 0.006584 # mshr miss rate for demand accesses
486system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for overall accesses
487system.cpu.dcache.overall_mshr_miss_rate::total 0.006584 # mshr miss rate for overall accesses
488system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7150.240771 # average ReadReq mshr miss latency
489system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7150.240771 # average ReadReq mshr miss latency
490system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15650.741009 # average WriteReq mshr miss latency
491system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15650.741009 # average WriteReq mshr miss latency
492system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency
493system.cpu.dcache.demand_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency
494system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency
495system.cpu.dcache.overall_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency
|
497system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 496system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
498system.cpu.l2cache.replacements 408579 # number of replacements
499system.cpu.l2cache.tagsinuse 29311.103059 # Cycle average of tags in use
500system.cpu.l2cache.total_refs 3608561 # Total number of references to valid blocks.
501system.cpu.l2cache.sampled_refs 440913 # Sample count of references to valid blocks.
502system.cpu.l2cache.avg_refs 8.184293 # Average number of references to valid blocks.
503system.cpu.l2cache.warmup_cycle 220580493000 # Cycle when the warmup percentage was hit.
504system.cpu.l2cache.occ_blocks::writebacks 21085.621991 # Average occupied blocks per requestor
505system.cpu.l2cache.occ_blocks::cpu.inst 148.428865 # Average occupied blocks per requestor
506system.cpu.l2cache.occ_blocks::cpu.data 8077.052203 # Average occupied blocks per requestor
507system.cpu.l2cache.occ_percent::writebacks 0.643482 # Average percentage of cache occupancy
508system.cpu.l2cache.occ_percent::cpu.inst 0.004530 # Average percentage of cache occupancy
509system.cpu.l2cache.occ_percent::cpu.data 0.246492 # Average percentage of cache occupancy
510system.cpu.l2cache.occ_percent::total 0.894504 # Average percentage of cache occupancy
511system.cpu.l2cache.ReadReq_hits::cpu.inst 3663 # number of ReadReq hits
512system.cpu.l2cache.ReadReq_hits::cpu.data 1537262 # number of ReadReq hits
513system.cpu.l2cache.ReadReq_hits::total 1540925 # number of ReadReq hits
514system.cpu.l2cache.Writeback_hits::writebacks 2302737 # number of Writeback hits
515system.cpu.l2cache.Writeback_hits::total 2302737 # number of Writeback hits
516system.cpu.l2cache.UpgradeReq_hits::cpu.data 1268 # number of UpgradeReq hits
517system.cpu.l2cache.UpgradeReq_hits::total 1268 # number of UpgradeReq hits
518system.cpu.l2cache.ReadExReq_hits::cpu.data 562455 # number of ReadExReq hits
519system.cpu.l2cache.ReadExReq_hits::total 562455 # number of ReadExReq hits
520system.cpu.l2cache.demand_hits::cpu.inst 3663 # number of demand (read+write) hits
521system.cpu.l2cache.demand_hits::cpu.data 2099717 # number of demand (read+write) hits
522system.cpu.l2cache.demand_hits::total 2103380 # number of demand (read+write) hits
523system.cpu.l2cache.overall_hits::cpu.inst 3663 # number of overall hits
524system.cpu.l2cache.overall_hits::cpu.data 2099717 # number of overall hits
525system.cpu.l2cache.overall_hits::total 2103380 # number of overall hits
526system.cpu.l2cache.ReadReq_misses::cpu.inst 3447 # number of ReadReq misses
527system.cpu.l2cache.ReadReq_misses::cpu.data 222139 # number of ReadReq misses
528system.cpu.l2cache.ReadReq_misses::total 225586 # number of ReadReq misses
529system.cpu.l2cache.UpgradeReq_misses::cpu.data 208539 # number of UpgradeReq misses
530system.cpu.l2cache.UpgradeReq_misses::total 208539 # number of UpgradeReq misses
531system.cpu.l2cache.ReadExReq_misses::cpu.data 209188 # number of ReadExReq misses
532system.cpu.l2cache.ReadExReq_misses::total 209188 # number of ReadExReq misses
533system.cpu.l2cache.demand_misses::cpu.inst 3447 # number of demand (read+write) misses
534system.cpu.l2cache.demand_misses::cpu.data 431327 # number of demand (read+write) misses
535system.cpu.l2cache.demand_misses::total 434774 # number of demand (read+write) misses
536system.cpu.l2cache.overall_misses::cpu.inst 3447 # number of overall misses
537system.cpu.l2cache.overall_misses::cpu.data 431327 # number of overall misses
538system.cpu.l2cache.overall_misses::total 434774 # number of overall misses
539system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120849500 # number of ReadReq miss cycles
540system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7624606932 # number of ReadReq miss cycles
541system.cpu.l2cache.ReadReq_miss_latency::total 7745456432 # number of ReadReq miss cycles
542system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10570500 # number of UpgradeReq miss cycles
543system.cpu.l2cache.UpgradeReq_miss_latency::total 10570500 # number of UpgradeReq miss cycles
544system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7166508500 # number of ReadExReq miss cycles
545system.cpu.l2cache.ReadExReq_miss_latency::total 7166508500 # number of ReadExReq miss cycles
546system.cpu.l2cache.demand_miss_latency::cpu.inst 120849500 # number of demand (read+write) miss cycles
547system.cpu.l2cache.demand_miss_latency::cpu.data 14791115432 # number of demand (read+write) miss cycles
548system.cpu.l2cache.demand_miss_latency::total 14911964932 # number of demand (read+write) miss cycles
549system.cpu.l2cache.overall_miss_latency::cpu.inst 120849500 # number of overall miss cycles
550system.cpu.l2cache.overall_miss_latency::cpu.data 14791115432 # number of overall miss cycles
551system.cpu.l2cache.overall_miss_latency::total 14911964932 # number of overall miss cycles
552system.cpu.l2cache.ReadReq_accesses::cpu.inst 7110 # number of ReadReq accesses(hits+misses)
553system.cpu.l2cache.ReadReq_accesses::cpu.data 1759401 # number of ReadReq accesses(hits+misses)
554system.cpu.l2cache.ReadReq_accesses::total 1766511 # number of ReadReq accesses(hits+misses)
555system.cpu.l2cache.Writeback_accesses::writebacks 2302737 # number of Writeback accesses(hits+misses)
556system.cpu.l2cache.Writeback_accesses::total 2302737 # number of Writeback accesses(hits+misses)
557system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209807 # number of UpgradeReq accesses(hits+misses)
558system.cpu.l2cache.UpgradeReq_accesses::total 209807 # number of UpgradeReq accesses(hits+misses)
559system.cpu.l2cache.ReadExReq_accesses::cpu.data 771643 # number of ReadExReq accesses(hits+misses)
560system.cpu.l2cache.ReadExReq_accesses::total 771643 # number of ReadExReq accesses(hits+misses)
561system.cpu.l2cache.demand_accesses::cpu.inst 7110 # number of demand (read+write) accesses
562system.cpu.l2cache.demand_accesses::cpu.data 2531044 # number of demand (read+write) accesses
563system.cpu.l2cache.demand_accesses::total 2538154 # number of demand (read+write) accesses
564system.cpu.l2cache.overall_accesses::cpu.inst 7110 # number of overall (read+write) accesses
565system.cpu.l2cache.overall_accesses::cpu.data 2531044 # number of overall (read+write) accesses
566system.cpu.l2cache.overall_accesses::total 2538154 # number of overall (read+write) accesses
567system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484810 # miss rate for ReadReq accesses
568system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126258 # miss rate for ReadReq accesses
569system.cpu.l2cache.ReadReq_miss_rate::total 0.127701 # miss rate for ReadReq accesses
570system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993956 # miss rate for UpgradeReq accesses
571system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993956 # miss rate for UpgradeReq accesses
572system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271094 # miss rate for ReadExReq accesses
573system.cpu.l2cache.ReadExReq_miss_rate::total 0.271094 # miss rate for ReadExReq accesses
574system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484810 # miss rate for demand accesses
575system.cpu.l2cache.demand_miss_rate::cpu.data 0.170415 # miss rate for demand accesses
576system.cpu.l2cache.demand_miss_rate::total 0.171295 # miss rate for demand accesses
577system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484810 # miss rate for overall accesses
578system.cpu.l2cache.overall_miss_rate::cpu.data 0.170415 # miss rate for overall accesses
579system.cpu.l2cache.overall_miss_rate::total 0.171295 # miss rate for overall accesses
580system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35059.326951 # average ReadReq miss latency
581system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34323.585377 # average ReadReq miss latency
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587system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35059.326951 # average overall miss latency
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591system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.115801 # average overall miss latency
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498system.cpu.l2cache.tagsinuse 29318.138904 # Cycle average of tags in use
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500system.cpu.l2cache.sampled_refs 441048 # Sample count of references to valid blocks.
501system.cpu.l2cache.avg_refs 8.190274 # Average number of references to valid blocks.
502system.cpu.l2cache.warmup_cycle 211122250000 # Cycle when the warmup percentage was hit.
503system.cpu.l2cache.occ_blocks::writebacks 21095.553590 # Average occupied blocks per requestor
504system.cpu.l2cache.occ_blocks::cpu.inst 147.717431 # Average occupied blocks per requestor
505system.cpu.l2cache.occ_blocks::cpu.data 8074.867883 # Average occupied blocks per requestor
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507system.cpu.l2cache.occ_percent::cpu.inst 0.004508 # Average percentage of cache occupancy
508system.cpu.l2cache.occ_percent::cpu.data 0.246425 # Average percentage of cache occupancy
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514system.cpu.l2cache.Writeback_hits::total 2304434 # number of Writeback hits
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523system.cpu.l2cache.overall_hits::cpu.data 2101802 # number of overall hits
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527system.cpu.l2cache.ReadReq_misses::total 225755 # number of ReadReq misses
528system.cpu.l2cache.UpgradeReq_misses::cpu.data 187429 # number of UpgradeReq misses
529system.cpu.l2cache.UpgradeReq_misses::total 187429 # number of UpgradeReq misses
530system.cpu.l2cache.ReadExReq_misses::cpu.data 209277 # number of ReadExReq misses
531system.cpu.l2cache.ReadExReq_misses::total 209277 # number of ReadExReq misses
532system.cpu.l2cache.demand_misses::cpu.inst 3497 # number of demand (read+write) misses
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539system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7630191458 # number of ReadReq miss cycles
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541system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10556000 # number of UpgradeReq miss cycles
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545system.cpu.l2cache.demand_miss_latency::cpu.inst 122603000 # number of demand (read+write) miss cycles
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548system.cpu.l2cache.overall_miss_latency::cpu.inst 122603000 # number of overall miss cycles
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552system.cpu.l2cache.ReadReq_accesses::cpu.data 1761339 # number of ReadReq accesses(hits+misses)
553system.cpu.l2cache.ReadReq_accesses::total 1768658 # number of ReadReq accesses(hits+misses)
554system.cpu.l2cache.Writeback_accesses::writebacks 2304434 # number of Writeback accesses(hits+misses)
555system.cpu.l2cache.Writeback_accesses::total 2304434 # number of Writeback accesses(hits+misses)
556system.cpu.l2cache.UpgradeReq_accesses::cpu.data 188879 # number of UpgradeReq accesses(hits+misses)
557system.cpu.l2cache.UpgradeReq_accesses::total 188879 # number of UpgradeReq accesses(hits+misses)
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559system.cpu.l2cache.ReadExReq_accesses::total 771998 # number of ReadExReq accesses(hits+misses)
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567system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126187 # miss rate for ReadReq accesses
568system.cpu.l2cache.ReadReq_miss_rate::total 0.127642 # miss rate for ReadReq accesses
569system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992323 # miss rate for UpgradeReq accesses
570system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992323 # miss rate for UpgradeReq accesses
571system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271085 # miss rate for ReadExReq accesses
572system.cpu.l2cache.ReadExReq_miss_rate::total 0.271085 # miss rate for ReadExReq accesses
573system.cpu.l2cache.demand_miss_rate::cpu.inst 0.477798 # miss rate for demand accesses
574system.cpu.l2cache.demand_miss_rate::cpu.data 0.170343 # miss rate for demand accesses
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577system.cpu.l2cache.overall_miss_rate::cpu.data 0.170343 # miss rate for overall accesses
578system.cpu.l2cache.overall_miss_rate::total 0.171228 # miss rate for overall accesses
579system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35059.479554 # average ReadReq miss latency
580system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34330.334377 # average ReadReq miss latency
581system.cpu.l2cache.ReadReq_avg_miss_latency::total 34341.629014 # average ReadReq miss latency
582system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 56.319993 # average UpgradeReq miss latency
583system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 56.319993 # average UpgradeReq miss latency
584system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34252.963775 # average ReadExReq miss latency
585system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34252.963775 # average ReadExReq miss latency
586system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35059.479554 # average overall miss latency
587system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.812768 # average overall miss latency
588system.cpu.l2cache.demand_avg_miss_latency::total 34298.975611 # average overall miss latency
589system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35059.479554 # average overall miss latency
590system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.812768 # average overall miss latency
591system.cpu.l2cache.overall_avg_miss_latency::total 34298.975611 # average overall miss latency
|
593system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
594system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
595system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
596system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
597system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
598system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
599system.cpu.l2cache.fast_writes 0 # number of fast writes performed
600system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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593system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
594system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
595system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
596system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
597system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
598system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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|
601system.cpu.l2cache.writebacks::writebacks 324894 # number of writebacks
602system.cpu.l2cache.writebacks::total 324894 # number of writebacks
603system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3447 # number of ReadReq MSHR misses
604system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222139 # number of ReadReq MSHR misses
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606system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208539 # number of UpgradeReq MSHR misses
607system.cpu.l2cache.UpgradeReq_mshr_misses::total 208539 # number of UpgradeReq MSHR misses
608system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209188 # number of ReadExReq MSHR misses
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620system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6467053500 # number of UpgradeReq MSHR miss cycles
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630system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126258 # mshr miss rate for ReadReq accesses
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632system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993956 # mshr miss rate for UpgradeReq accesses
633system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993956 # mshr miss rate for UpgradeReq accesses
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635system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271094 # mshr miss rate for ReadExReq accesses
636system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for demand accesses
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640system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170415 # mshr miss rate for overall accesses
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643system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31217.368400 # average ReadReq mshr miss latency
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645system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.242501 # average UpgradeReq mshr miss latency
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647system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.592749 # average ReadExReq mshr miss latency
648system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.592749 # average ReadExReq mshr miss latency
649system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency
650system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency
651system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.294569 # average overall mshr miss latency
652system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency
653system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency
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612system.cpu.l2cache.UpgradeReq_mshr_misses::total 187429 # number of UpgradeReq MSHR misses
613system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209277 # number of ReadExReq MSHR misses
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625system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5812216000 # number of UpgradeReq MSHR miss cycles
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637system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992323 # mshr miss rate for UpgradeReq accesses
638system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992323 # mshr miss rate for UpgradeReq accesses
639system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271085 # mshr miss rate for ReadExReq accesses
640system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271085 # mshr miss rate for ReadExReq accesses
641system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.477798 # mshr miss rate for demand accesses
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645system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170342 # mshr miss rate for overall accesses
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648system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31225.320233 # average ReadReq mshr miss latency
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652system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.314889 # average ReadExReq mshr miss latency
653system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.314889 # average ReadExReq mshr miss latency
654system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31887.474979 # average overall mshr miss latency
655system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31122.505988 # average overall mshr miss latency
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657system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31887.474979 # average overall mshr miss latency
658system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31122.505988 # average overall mshr miss latency
659system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31128.655197 # average overall mshr miss latency
|
655system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
656
657---------- End Simulation Statistics ----------
| 660system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
661
662---------- End Simulation Statistics ----------
|