1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.455813 # Number of seconds simulated
4sim_ticks 455813328500 # Number of ticks simulated
5final_tick 455813328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.460578 # Number of seconds simulated
4sim_ticks 460577560500 # Number of ticks simulated
5final_tick 460577560500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 110548 # Simulator instruction rate (inst/s)
8host_op_rate 204416 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 60939389 # Simulator tick rate (ticks/s)
10host_mem_usage 266636 # Number of bytes of host memory used
11host_seconds 7479.78 # Real time elapsed on the host
| 7host_inst_rate 104932 # Simulator instruction rate (inst/s)
8host_op_rate 194032 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 58448222 # Simulator tick rate (ticks/s)
10host_mem_usage 266596 # Number of bytes of host memory used
11host_seconds 7880.10 # Real time elapsed on the host
|
12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
| 12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read::cpu.inst 220672 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 27604992 # Number of bytes read from this memory
16system.physmem.bytes_read::total 27825664 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 220672 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 220672 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 20791296 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20791296 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3448 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 431328 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 434776 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 324864 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 324864 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 484128 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 60562055 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 61046183 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 484128 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 484128 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 45613620 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 45613620 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 45613620 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 484128 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 60562055 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 106659803 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu.inst 222400 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 27604032 # Number of bytes read from this memory
16system.physmem.bytes_read::total 27826432 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 222400 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 222400 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 20791104 # Number of bytes written to this memory
20system.physmem.bytes_written::total 20791104 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3475 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 431313 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 434788 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 324861 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 324861 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 482872 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 59933515 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 60416387 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 482872 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 482872 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 45141374 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 45141374 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 45141374 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 482872 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 59933515 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 105557761 # Total bandwidth to/from this memory (bytes/s)
|
37system.cpu.workload.num_syscalls 551 # Number of system calls
| 37system.cpu.workload.num_syscalls 551 # Number of system calls
|
38system.cpu.numCycles 911626658 # number of cpu cycles simulated
| 38system.cpu.numCycles 921155122 # number of cpu cycles simulated
|
39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
41system.cpu.BPredUnit.lookups 225614318 # Number of BP lookups
42system.cpu.BPredUnit.condPredicted 225614318 # Number of conditional branches predicted
43system.cpu.BPredUnit.condIncorrect 14285714 # Number of conditional branches incorrect
44system.cpu.BPredUnit.BTBLookups 160541063 # Number of BTB lookups
45system.cpu.BPredUnit.BTBHits 155870604 # Number of BTB hits
| 41system.cpu.BPredUnit.lookups 225826893 # Number of BP lookups
42system.cpu.BPredUnit.condPredicted 225826893 # Number of conditional branches predicted
43system.cpu.BPredUnit.condIncorrect 14312665 # Number of conditional branches incorrect
44system.cpu.BPredUnit.BTBLookups 160782597 # Number of BTB lookups
45system.cpu.BPredUnit.BTBHits 155982448 # Number of BTB hits
|
46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
| 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
49system.cpu.fetch.icacheStallCycles 191565109 # Number of cycles fetch is stalled on an Icache miss
50system.cpu.fetch.Insts 1263061891 # Number of instructions fetch has processed
51system.cpu.fetch.Branches 225614318 # Number of branches that fetch encountered
52system.cpu.fetch.predictedBranches 155870604 # Number of branches that fetch has predicted taken
53system.cpu.fetch.Cycles 392054994 # Number of cycles fetch has run and was not squashing or blocked
54system.cpu.fetch.SquashCycles 98473885 # Number of cycles fetch has spent squashing
55system.cpu.fetch.BlockedCycles 230412581 # Number of cycles fetch has spent blocked
56system.cpu.fetch.MiscStallCycles 25920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
57system.cpu.fetch.PendingTrapStallCycles 273577 # Number of stall cycles due to pending traps
58system.cpu.fetch.CacheLines 183478574 # Number of cache lines fetched
59system.cpu.fetch.IcacheSquashes 3652581 # Number of outstanding Icache misses that were squashed
60system.cpu.fetch.rateDist::samples 898267437 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::mean 2.606318 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::stdev 3.392133 # Number of instructions fetched each cycle (Total)
| 49system.cpu.fetch.icacheStallCycles 191746261 # Number of cycles fetch is stalled on an Icache miss
50system.cpu.fetch.Insts 1263371603 # Number of instructions fetch has processed
51system.cpu.fetch.Branches 225826893 # Number of branches that fetch encountered
52system.cpu.fetch.predictedBranches 155982448 # Number of branches that fetch has predicted taken
53system.cpu.fetch.Cycles 392161652 # Number of cycles fetch has run and was not squashing or blocked
54system.cpu.fetch.SquashCycles 98608350 # Number of cycles fetch has spent squashing
55system.cpu.fetch.BlockedCycles 239363044 # Number of cycles fetch has spent blocked
56system.cpu.fetch.MiscStallCycles 24915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
57system.cpu.fetch.PendingTrapStallCycles 235054 # Number of stall cycles due to pending traps
58system.cpu.fetch.CacheLines 183579479 # Number of cache lines fetched
59system.cpu.fetch.IcacheSquashes 3670479 # Number of outstanding Icache misses that were squashed
60system.cpu.fetch.rateDist::samples 907575951 # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::mean 2.580457 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::stdev 3.385202 # Number of instructions fetched each cycle (Total)
|
63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
64system.cpu.fetch.rateDist::0 510675527 56.85% 56.85% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::1 25992328 2.89% 59.74% # Number of instructions fetched each cycle (Total)
66system.cpu.fetch.rateDist::2 29100733 3.24% 62.98% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::3 30303597 3.37% 66.36% # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::4 19641643 2.19% 68.54% # Number of instructions fetched each cycle (Total)
69system.cpu.fetch.rateDist::5 25615145 2.85% 71.40% # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.rateDist::6 32617140 3.63% 75.03% # Number of instructions fetched each cycle (Total)
71system.cpu.fetch.rateDist::7 30849776 3.43% 78.46% # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::8 193471548 21.54% 100.00% # Number of instructions fetched each cycle (Total)
| 64system.cpu.fetch.rateDist::0 519878601 57.28% 57.28% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::1 25999906 2.86% 60.15% # Number of instructions fetched each cycle (Total)
66system.cpu.fetch.rateDist::2 29091750 3.21% 63.35% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::3 30316480 3.34% 66.69% # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::4 19610375 2.16% 68.85% # Number of instructions fetched each cycle (Total)
69system.cpu.fetch.rateDist::5 25620095 2.82% 71.68% # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.rateDist::6 32648944 3.60% 75.27% # Number of instructions fetched each cycle (Total)
71system.cpu.fetch.rateDist::7 30886362 3.40% 78.68% # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::8 193523438 21.32% 100.00% # Number of instructions fetched each cycle (Total)
|
73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
76system.cpu.fetch.rateDist::total 898267437 # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.branchRate 0.247485 # Number of branch fetches per cycle
78system.cpu.fetch.rate 1.385503 # Number of inst fetches per cycle
79system.cpu.decode.IdleCycles 252696641 # Number of cycles decode is idle
80system.cpu.decode.BlockedCycles 182534450 # Number of cycles decode is blocked
81system.cpu.decode.RunCycles 330171612 # Number of cycles decode is running
82system.cpu.decode.UnblockCycles 48929478 # Number of cycles decode is unblocking
83system.cpu.decode.SquashCycles 83935256 # Number of cycles decode is squashing
84system.cpu.decode.DecodedInsts 2290198570 # Number of instructions handled by decode
85system.cpu.decode.SquashedInsts 4 # Number of squashed instructions handled by decode
86system.cpu.rename.SquashCycles 83935256 # Number of cycles rename is squashing
87system.cpu.rename.IdleCycles 289311592 # Number of cycles rename is idle
88system.cpu.rename.BlockCycles 40780199 # Number of cycles rename is blocking
89system.cpu.rename.serializeStallCycles 14639 # count of cycles rename stalled for serializing inst
90system.cpu.rename.RunCycles 340344585 # Number of cycles rename is running
91system.cpu.rename.UnblockCycles 143881166 # Number of cycles rename is unblocking
92system.cpu.rename.RenamedInsts 2240282902 # Number of instructions processed by rename
93system.cpu.rename.ROBFullEvents 2186 # Number of times rename has blocked due to ROB full
94system.cpu.rename.IQFullEvents 22940117 # Number of times rename has blocked due to IQ full
95system.cpu.rename.LSQFullEvents 103602655 # Number of times rename has blocked due to LSQ full
96system.cpu.rename.FullRegisterEvents 11705 # Number of times there has been no free registers
97system.cpu.rename.RenamedOperands 2887046684 # Number of destination operands rename has renamed
98system.cpu.rename.RenameLookups 6493129070 # Number of register rename lookups that rename has made
99system.cpu.rename.int_rename_lookups 6492267923 # Number of integer rename lookups
100system.cpu.rename.fp_rename_lookups 861147 # Number of floating rename lookups
| 76system.cpu.fetch.rateDist::total 907575951 # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.branchRate 0.245156 # Number of branch fetches per cycle
78system.cpu.fetch.rate 1.371508 # Number of inst fetches per cycle
79system.cpu.decode.IdleCycles 253842060 # Number of cycles decode is idle
80system.cpu.decode.BlockedCycles 190511569 # Number of cycles decode is blocked
81system.cpu.decode.RunCycles 329127835 # Number of cycles decode is running
82system.cpu.decode.UnblockCycles 50049462 # Number of cycles decode is unblocking
83system.cpu.decode.SquashCycles 84045025 # Number of cycles decode is squashing
84system.cpu.decode.DecodedInsts 2290915196 # Number of instructions handled by decode
85system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
86system.cpu.rename.SquashCycles 84045025 # Number of cycles rename is squashing
87system.cpu.rename.IdleCycles 290488035 # Number of cycles rename is idle
88system.cpu.rename.BlockCycles 45203385 # Number of cycles rename is blocking
89system.cpu.rename.serializeStallCycles 15283 # count of cycles rename stalled for serializing inst
90system.cpu.rename.RunCycles 340026605 # Number of cycles rename is running
91system.cpu.rename.UnblockCycles 147797618 # Number of cycles rename is unblocking
92system.cpu.rename.RenamedInsts 2240907588 # Number of instructions processed by rename
93system.cpu.rename.ROBFullEvents 2049 # Number of times rename has blocked due to ROB full
94system.cpu.rename.IQFullEvents 24533767 # Number of times rename has blocked due to IQ full
95system.cpu.rename.LSQFullEvents 107236940 # Number of times rename has blocked due to LSQ full
96system.cpu.rename.FullRegisterEvents 12284 # Number of times there has been no free registers
97system.cpu.rename.RenamedOperands 2887565810 # Number of destination operands rename has renamed
98system.cpu.rename.RenameLookups 6495003002 # Number of register rename lookups that rename has made
99system.cpu.rename.int_rename_lookups 6494129328 # Number of integer rename lookups
100system.cpu.rename.fp_rename_lookups 873674 # Number of floating rename lookups
|
101system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed
| 101system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed
|
102system.cpu.rename.UndoneMaps 893969200 # Number of HB maps that are undone due to squashing
103system.cpu.rename.serializingInsts 1261 # count of serializing insts renamed
104system.cpu.rename.tempSerializingInsts 1244 # count of temporary serializing insts renamed
105system.cpu.rename.skidInsts 345524950 # count of insts added to the skid buffer
106system.cpu.memDep0.insertedLoads 540216674 # Number of loads inserted to the mem dependence unit.
107system.cpu.memDep0.insertedStores 217364695 # Number of stores inserted to the mem dependence unit.
108system.cpu.memDep0.conflictingLoads 216116185 # Number of conflicting loads.
109system.cpu.memDep0.conflictingStores 63552241 # Number of conflicting stores.
110system.cpu.iq.iqInstsAdded 2143188368 # Number of instructions added to the IQ (excludes non-spec)
111system.cpu.iq.iqNonSpecInstsAdded 61311 # Number of non-speculative instructions added to the IQ
112system.cpu.iq.iqInstsIssued 1846653007 # Number of instructions issued
113system.cpu.iq.iqSquashedInstsIssued 1596963 # Number of squashed instructions issued
114system.cpu.iq.iqSquashedInstsExamined 612532438 # Number of squashed instructions iterated over during squash; mainly for profiling
115system.cpu.iq.iqSquashedOperandsExamined 1230905034 # Number of squashed operands that are examined and possibly removed from graph
116system.cpu.iq.iqSquashedNonSpecRemoved 60758 # Number of squashed non-spec instructions that were removed
117system.cpu.iq.issued_per_cycle::samples 898267437 # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::mean 2.055794 # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::stdev 1.806511 # Number of insts issued each cycle
| 102system.cpu.rename.UndoneMaps 894488326 # Number of HB maps that are undone due to squashing
103system.cpu.rename.serializingInsts 1298 # count of serializing insts renamed
104system.cpu.rename.tempSerializingInsts 1285 # count of temporary serializing insts renamed
105system.cpu.rename.skidInsts 351684544 # count of insts added to the skid buffer
106system.cpu.memDep0.insertedLoads 540282589 # Number of loads inserted to the mem dependence unit.
107system.cpu.memDep0.insertedStores 217467537 # Number of stores inserted to the mem dependence unit.
108system.cpu.memDep0.conflictingLoads 211757951 # Number of conflicting loads.
109system.cpu.memDep0.conflictingStores 61365379 # Number of conflicting stores.
110system.cpu.iq.iqInstsAdded 2143556526 # Number of instructions added to the IQ (excludes non-spec)
111system.cpu.iq.iqNonSpecInstsAdded 68297 # Number of non-speculative instructions added to the IQ
112system.cpu.iq.iqInstsIssued 1846659599 # Number of instructions issued
113system.cpu.iq.iqSquashedInstsIssued 1592599 # Number of squashed instructions issued
114system.cpu.iq.iqSquashedInstsExamined 612964134 # Number of squashed instructions iterated over during squash; mainly for profiling
115system.cpu.iq.iqSquashedOperandsExamined 1231726867 # Number of squashed operands that are examined and possibly removed from graph
116system.cpu.iq.iqSquashedNonSpecRemoved 67744 # Number of squashed non-spec instructions that were removed
117system.cpu.iq.issued_per_cycle::samples 907575951 # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::mean 2.034716 # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::stdev 1.801175 # Number of insts issued each cycle
|
120system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 120system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
121system.cpu.iq.issued_per_cycle::0 244119309 27.18% 27.18% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::1 156083539 17.38% 44.55% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::2 150204364 16.72% 61.27% # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::3 147125554 16.38% 77.65% # Number of insts issued each cycle
125system.cpu.iq.issued_per_cycle::4 103909500 11.57% 89.22% # Number of insts issued each cycle
126system.cpu.iq.issued_per_cycle::5 58948328 6.56% 95.78% # Number of insts issued each cycle
127system.cpu.iq.issued_per_cycle::6 27781277 3.09% 98.88% # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::7 9047752 1.01% 99.88% # Number of insts issued each cycle
129system.cpu.iq.issued_per_cycle::8 1047814 0.12% 100.00% # Number of insts issued each cycle
| 121system.cpu.iq.issued_per_cycle::0 248881296 27.42% 27.42% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::1 159283558 17.55% 44.97% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::2 154019271 16.97% 61.94% # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::3 148934495 16.41% 78.35% # Number of insts issued each cycle
125system.cpu.iq.issued_per_cycle::4 98823398 10.89% 89.24% # Number of insts issued each cycle
126system.cpu.iq.issued_per_cycle::5 59633911 6.57% 95.81% # Number of insts issued each cycle
127system.cpu.iq.issued_per_cycle::6 27979654 3.08% 98.90% # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::7 8970001 0.99% 99.88% # Number of insts issued each cycle
129system.cpu.iq.issued_per_cycle::8 1050367 0.12% 100.00% # Number of insts issued each cycle
|
130system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
131system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
132system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 130system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
131system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
132system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
133system.cpu.iq.issued_per_cycle::total 898267437 # Number of insts issued each cycle
| 133system.cpu.iq.issued_per_cycle::total 907575951 # Number of insts issued each cycle
|
134system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 134system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
135system.cpu.iq.fu_full::IntAlu 2653512 16.69% 16.69% # attempts to use FU when none available
136system.cpu.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available
137system.cpu.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available
138system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available
139system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available
140system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available
141system.cpu.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available
142system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available
143system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available
163system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available
164system.cpu.iq.fu_full::MemRead 10033753 63.11% 79.79% # attempts to use FU when none available
165system.cpu.iq.fu_full::MemWrite 3212720 20.21% 100.00% # attempts to use FU when none available
| 135system.cpu.iq.fu_full::IntAlu 2635862 18.39% 18.39% # attempts to use FU when none available
136system.cpu.iq.fu_full::IntMult 0 0.00% 18.39% # attempts to use FU when none available
137system.cpu.iq.fu_full::IntDiv 0 0.00% 18.39% # attempts to use FU when none available
138system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.39% # attempts to use FU when none available
139system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.39% # attempts to use FU when none available
140system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.39% # attempts to use FU when none available
141system.cpu.iq.fu_full::FloatMult 0 0.00% 18.39% # attempts to use FU when none available
142system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.39% # attempts to use FU when none available
143system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.39% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.39% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.39% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.39% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.39% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.39% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.39% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdMult 0 0.00% 18.39% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.39% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdShift 0 0.00% 18.39% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.39% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.39% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.39% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.39% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.39% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.39% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.39% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.39% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.39% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.39% # attempts to use FU when none available
163system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.39% # attempts to use FU when none available
164system.cpu.iq.fu_full::MemRead 8471298 59.09% 77.48% # attempts to use FU when none available
165system.cpu.iq.fu_full::MemWrite 3228137 22.52% 100.00% # attempts to use FU when none available
|
166system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
167system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
| 166system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
167system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
168system.cpu.iq.FU_type_0::No_OpClass 2721869 0.15% 0.15% # Type of FU issued
169system.cpu.iq.FU_type_0::IntAlu 1219400147 66.03% 66.18% # Type of FU issued
170system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued
171system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued
172system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued
173system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
174system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
175system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
176system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
177system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
197system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
198system.cpu.iq.FU_type_0::MemRead 447092064 24.21% 90.39% # Type of FU issued
199system.cpu.iq.FU_type_0::MemWrite 177438927 9.61% 100.00% # Type of FU issued
| 168system.cpu.iq.FU_type_0::No_OpClass 2716270 0.15% 0.15% # Type of FU issued
169system.cpu.iq.FU_type_0::IntAlu 1219519641 66.04% 66.19% # Type of FU issued
170system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued
171system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued
172system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued
173system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.19% # Type of FU issued
174system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.19% # Type of FU issued
175system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.19% # Type of FU issued
176system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.19% # Type of FU issued
177system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.19% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.19% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.19% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.19% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.19% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.19% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.19% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.19% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.19% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.19% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.19% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued
197system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued
198system.cpu.iq.FU_type_0::MemRead 447028129 24.21% 90.39% # Type of FU issued
199system.cpu.iq.FU_type_0::MemWrite 177395559 9.61% 100.00% # Type of FU issued
|
200system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
201system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 200system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
201system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
202system.cpu.iq.FU_type_0::total 1846653007 # Type of FU issued
203system.cpu.iq.rate 2.025668 # Inst issue rate
204system.cpu.iq.fu_busy_cnt 15899985 # FU busy when requested
205system.cpu.iq.fu_busy_rate 0.008610 # FU busy rate (busy events/executed inst)
206system.cpu.iq.int_inst_queue_reads 4609062574 # Number of integer instruction queue reads
207system.cpu.iq.int_inst_queue_writes 2755747075 # Number of integer instruction queue writes
208system.cpu.iq.int_inst_queue_wakeup_accesses 1806129295 # Number of integer instruction queue wakeup accesses
209system.cpu.iq.fp_inst_queue_reads 7825 # Number of floating instruction queue reads
210system.cpu.iq.fp_inst_queue_writes 296338 # Number of floating instruction queue writes
211system.cpu.iq.fp_inst_queue_wakeup_accesses 285 # Number of floating instruction queue wakeup accesses
212system.cpu.iq.int_alu_accesses 1859828366 # Number of integer alu accesses
213system.cpu.iq.fp_alu_accesses 2757 # Number of floating point alu accesses
214system.cpu.iew.lsq.thread0.forwLoads 167960734 # Number of loads that had data forwarded from stores
| 202system.cpu.iq.FU_type_0::total 1846659599 # Type of FU issued
203system.cpu.iq.rate 2.004722 # Inst issue rate
204system.cpu.iq.fu_busy_cnt 14335297 # FU busy when requested
205system.cpu.iq.fu_busy_rate 0.007763 # FU busy rate (busy events/executed inst)
206system.cpu.iq.int_inst_queue_reads 4616815245 # Number of integer instruction queue reads
207system.cpu.iq.int_inst_queue_writes 2756549096 # Number of integer instruction queue writes
208system.cpu.iq.int_inst_queue_wakeup_accesses 1806310045 # Number of integer instruction queue wakeup accesses
209system.cpu.iq.fp_inst_queue_reads 7800 # Number of floating instruction queue reads
210system.cpu.iq.fp_inst_queue_writes 300622 # Number of floating instruction queue writes
211system.cpu.iq.fp_inst_queue_wakeup_accesses 277 # Number of floating instruction queue wakeup accesses
212system.cpu.iq.int_alu_accesses 1858275871 # Number of integer alu accesses
213system.cpu.iq.fp_alu_accesses 2755 # Number of floating point alu accesses
214system.cpu.iew.lsq.thread0.forwLoads 168023437 # Number of loads that had data forwarded from stores
|
215system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 215system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
216system.cpu.iew.lsq.thread0.squashedLoads 156114514 # Number of loads squashed
217system.cpu.iew.lsq.thread0.ignoredResponses 428176 # Number of memory responses ignored because the instruction is squashed
218system.cpu.iew.lsq.thread0.memOrderViolation 272950 # Number of memory ordering violations
219system.cpu.iew.lsq.thread0.squashedStores 68204770 # Number of stores squashed
| 216system.cpu.iew.lsq.thread0.squashedLoads 156180429 # Number of loads squashed
217system.cpu.iew.lsq.thread0.ignoredResponses 430384 # Number of memory responses ignored because the instruction is squashed
218system.cpu.iew.lsq.thread0.memOrderViolation 272150 # Number of memory ordering violations
219system.cpu.iew.lsq.thread0.squashedStores 68307598 # Number of stores squashed
|
220system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
221system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
| 220system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
221system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
222system.cpu.iew.lsq.thread0.rescheduledLoads 6724 # Number of loads that were rescheduled
223system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
| 222system.cpu.iew.lsq.thread0.rescheduledLoads 7189 # Number of loads that were rescheduled
223system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
224system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 224system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
225system.cpu.iew.iewSquashCycles 83935256 # Number of cycles IEW is squashing
226system.cpu.iew.iewBlockCycles 5705090 # Number of cycles IEW is blocking
227system.cpu.iew.iewUnblockCycles 1089193 # Number of cycles IEW is unblocking
228system.cpu.iew.iewDispatchedInsts 2143249679 # Number of instructions dispatched to IQ
229system.cpu.iew.iewDispSquashedInsts 2772043 # Number of squashed instructions skipped by dispatch
230system.cpu.iew.iewDispLoadInsts 540216674 # Number of dispatched load instructions
231system.cpu.iew.iewDispStoreInsts 217364955 # Number of dispatched store instructions
232system.cpu.iew.iewDispNonSpecInsts 5665 # Number of dispatched non-speculative instructions
233system.cpu.iew.iewIQFullEvents 876205 # Number of times the IQ has become full, causing a stall
234system.cpu.iew.iewLSQFullEvents 14852 # Number of times the LSQ has become full, causing a stall
235system.cpu.iew.memOrderViolationEvents 272950 # Number of memory order violations
236system.cpu.iew.predictedTakenIncorrect 10085276 # Number of branches that were predicted taken incorrectly
237system.cpu.iew.predictedNotTakenIncorrect 5239623 # Number of branches that were predicted not taken incorrectly
238system.cpu.iew.branchMispredicts 15324899 # Number of branch mispredicts detected at execute
239system.cpu.iew.iewExecutedInsts 1818663600 # Number of executed instructions
240system.cpu.iew.iewExecLoadInsts 438639718 # Number of load instructions executed
241system.cpu.iew.iewExecSquashedInsts 27989407 # Number of squashed instructions skipped in execute
| 225system.cpu.iew.iewSquashCycles 84045025 # Number of cycles IEW is squashing
226system.cpu.iew.iewBlockCycles 6572333 # Number of cycles IEW is blocking
227system.cpu.iew.iewUnblockCycles 1289879 # Number of cycles IEW is unblocking
228system.cpu.iew.iewDispatchedInsts 2143624823 # Number of instructions dispatched to IQ
229system.cpu.iew.iewDispSquashedInsts 2858157 # Number of squashed instructions skipped by dispatch
230system.cpu.iew.iewDispLoadInsts 540282589 # Number of dispatched load instructions
231system.cpu.iew.iewDispStoreInsts 217467783 # Number of dispatched store instructions
232system.cpu.iew.iewDispNonSpecInsts 5279 # Number of dispatched non-speculative instructions
233system.cpu.iew.iewIQFullEvents 972146 # Number of times the IQ has become full, causing a stall
234system.cpu.iew.iewLSQFullEvents 66800 # Number of times the LSQ has become full, causing a stall
235system.cpu.iew.memOrderViolationEvents 272150 # Number of memory order violations
236system.cpu.iew.predictedTakenIncorrect 10086391 # Number of branches that were predicted taken incorrectly
237system.cpu.iew.predictedNotTakenIncorrect 5256955 # Number of branches that were predicted not taken incorrectly
238system.cpu.iew.branchMispredicts 15343346 # Number of branch mispredicts detected at execute
239system.cpu.iew.iewExecutedInsts 1818812244 # Number of executed instructions
240system.cpu.iew.iewExecLoadInsts 438622961 # Number of load instructions executed
241system.cpu.iew.iewExecSquashedInsts 27847355 # Number of squashed instructions skipped in execute
|
242system.cpu.iew.exec_swp 0 # number of swp insts executed
243system.cpu.iew.exec_nop 0 # number of nop insts executed
| 242system.cpu.iew.exec_swp 0 # number of swp insts executed
243system.cpu.iew.exec_nop 0 # number of nop insts executed
|
244system.cpu.iew.exec_refs 610490535 # number of memory reference insts executed
245system.cpu.iew.exec_branches 170808194 # Number of branches executed
246system.cpu.iew.exec_stores 171850817 # Number of stores executed
247system.cpu.iew.exec_rate 1.994965 # Inst execution rate
248system.cpu.iew.wb_sent 1813450071 # cumulative count of insts sent to commit
249system.cpu.iew.wb_count 1806129580 # cumulative count of insts written-back
250system.cpu.iew.wb_producers 1379661197 # num instructions producing a value
251system.cpu.iew.wb_consumers 2939711936 # num instructions consuming a value
| 244system.cpu.iew.exec_refs 610455243 # number of memory reference insts executed
245system.cpu.iew.exec_branches 170879995 # Number of branches executed
246system.cpu.iew.exec_stores 171832282 # Number of stores executed
247system.cpu.iew.exec_rate 1.974491 # Inst execution rate
248system.cpu.iew.wb_sent 1813575376 # cumulative count of insts sent to commit
249system.cpu.iew.wb_count 1806310322 # cumulative count of insts written-back
250system.cpu.iew.wb_producers 1378798297 # num instructions producing a value
251system.cpu.iew.wb_consumers 2933608967 # num instructions consuming a value
|
252system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 252system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
253system.cpu.iew.wb_rate 1.981216 # insts written-back per cycle
254system.cpu.iew.wb_fanout 0.469319 # average fanout of values written-back
| 253system.cpu.iew.wb_rate 1.960919 # insts written-back per cycle
254system.cpu.iew.wb_fanout 0.470001 # average fanout of values written-back
|
255system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
256system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
257system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
| 255system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
256system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
257system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
|
258system.cpu.commit.commitSquashedInsts 614283465 # The number of squashed insts skipped by commit
| 258system.cpu.commit.commitSquashedInsts 614662287 # The number of squashed insts skipped by commit
|
259system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
| 259system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
260system.cpu.commit.branchMispredicts 14312346 # The number of times a branch was mispredicted
261system.cpu.commit.committed_per_cycle::samples 814332181 # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::mean 1.877598 # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::stdev 2.330573 # Number of insts commited each cycle
| 260system.cpu.commit.branchMispredicts 14337681 # The number of times a branch was mispredicted
261system.cpu.commit.committed_per_cycle::samples 823530926 # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::mean 1.856626 # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::stdev 2.319528 # Number of insts commited each cycle
|
264system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 264system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
265system.cpu.commit.committed_per_cycle::0 298731075 36.68% 36.68% # Number of insts commited each cycle
266system.cpu.commit.committed_per_cycle::1 203556250 25.00% 61.68% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::2 73630894 9.04% 70.72% # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::3 94876671 11.65% 82.37% # Number of insts commited each cycle
269system.cpu.commit.committed_per_cycle::4 30957165 3.80% 86.18% # Number of insts commited each cycle
270system.cpu.commit.committed_per_cycle::5 28752943 3.53% 89.71% # Number of insts commited each cycle
271system.cpu.commit.committed_per_cycle::6 16466236 2.02% 91.73% # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::7 11737662 1.44% 93.17% # Number of insts commited each cycle
273system.cpu.commit.committed_per_cycle::8 55623285 6.83% 100.00% # Number of insts commited each cycle
| 265system.cpu.commit.committed_per_cycle::0 305238213 37.06% 37.06% # Number of insts commited each cycle
266system.cpu.commit.committed_per_cycle::1 205541162 24.96% 62.02% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::2 74423413 9.04% 71.06% # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::3 96471007 11.71% 82.77% # Number of insts commited each cycle
269system.cpu.commit.committed_per_cycle::4 29999240 3.64% 86.42% # Number of insts commited each cycle
270system.cpu.commit.committed_per_cycle::5 28772955 3.49% 89.91% # Number of insts commited each cycle
271system.cpu.commit.committed_per_cycle::6 15805357 1.92% 91.83% # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::7 11742762 1.43% 93.26% # Number of insts commited each cycle
273system.cpu.commit.committed_per_cycle::8 55536817 6.74% 100.00% # Number of insts commited each cycle
|
274system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
275system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
276system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 274system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
275system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
276system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
277system.cpu.commit.committed_per_cycle::total 814332181 # Number of insts commited each cycle
| 277system.cpu.commit.committed_per_cycle::total 823530926 # Number of insts commited each cycle
|
278system.cpu.commit.committedInsts 826877144 # Number of instructions committed
279system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
280system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
281system.cpu.commit.refs 533262345 # Number of memory references committed
282system.cpu.commit.loads 384102160 # Number of loads committed
283system.cpu.commit.membars 0 # Number of memory barriers committed
284system.cpu.commit.branches 149758588 # Number of branches committed
285system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
286system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
287system.cpu.commit.function_calls 0 # Number of function calls committed.
| 278system.cpu.commit.committedInsts 826877144 # Number of instructions committed
279system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
280system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
281system.cpu.commit.refs 533262345 # Number of memory references committed
282system.cpu.commit.loads 384102160 # Number of loads committed
283system.cpu.commit.membars 0 # Number of memory barriers committed
284system.cpu.commit.branches 149758588 # Number of branches committed
285system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
286system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
287system.cpu.commit.function_calls 0 # Number of function calls committed.
|
288system.cpu.commit.bw_lim_events 55623285 # number cycles where commit BW limit reached
| 288system.cpu.commit.bw_lim_events 55536817 # number cycles where commit BW limit reached
|
289system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 289system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
290system.cpu.rob.rob_reads 2901981117 # The number of ROB reads
291system.cpu.rob.rob_writes 4370596606 # The number of ROB writes
292system.cpu.timesIdled 304669 # Number of times that the entire CPU went into an idle state and unscheduled itself
293system.cpu.idleCycles 13359221 # Total number of cycles that the CPU has spent unscheduled due to idling
| 290system.cpu.rob.rob_reads 2911645152 # The number of ROB reads
291system.cpu.rob.rob_writes 4371462099 # The number of ROB writes
292system.cpu.timesIdled 309415 # Number of times that the entire CPU went into an idle state and unscheduled itself
293system.cpu.idleCycles 13579171 # Total number of cycles that the CPU has spent unscheduled due to idling
|
294system.cpu.committedInsts 826877144 # Number of Instructions Simulated
295system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
296system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
| 294system.cpu.committedInsts 826877144 # Number of Instructions Simulated
295system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
296system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
|
297system.cpu.cpi 1.102493 # CPI: Cycles Per Instruction
298system.cpu.cpi_total 1.102493 # CPI: Total CPI of All Threads
299system.cpu.ipc 0.907035 # IPC: Instructions Per Cycle
300system.cpu.ipc_total 0.907035 # IPC: Total IPC of All Threads
301system.cpu.int_regfile_reads 4004133317 # number of integer regfile reads
302system.cpu.int_regfile_writes 2286262019 # number of integer regfile writes
303system.cpu.fp_regfile_reads 284 # number of floating regfile reads
304system.cpu.fp_regfile_writes 1 # number of floating regfile writes
305system.cpu.misc_regfile_reads 1001892809 # number of misc regfile reads
306system.cpu.icache.replacements 5521 # number of replacements
307system.cpu.icache.tagsinuse 1042.048866 # Cycle average of tags in use
308system.cpu.icache.total_refs 183243707 # Total number of references to valid blocks.
309system.cpu.icache.sampled_refs 7141 # Sample count of references to valid blocks.
310system.cpu.icache.avg_refs 25660.790786 # Average number of references to valid blocks.
| 297system.cpu.cpi 1.114017 # CPI: Cycles Per Instruction
298system.cpu.cpi_total 1.114017 # CPI: Total CPI of All Threads
299system.cpu.ipc 0.897652 # IPC: Instructions Per Cycle
300system.cpu.ipc_total 0.897652 # IPC: Total IPC of All Threads
301system.cpu.int_regfile_reads 4004251902 # number of integer regfile reads
302system.cpu.int_regfile_writes 2286361140 # number of integer regfile writes
303system.cpu.fp_regfile_reads 274 # number of floating regfile reads
304system.cpu.fp_regfile_writes 3 # number of floating regfile writes
305system.cpu.misc_regfile_reads 1001934144 # number of misc regfile reads
306system.cpu.icache.replacements 5528 # number of replacements
307system.cpu.icache.tagsinuse 1043.833365 # Cycle average of tags in use
308system.cpu.icache.total_refs 183339964 # Total number of references to valid blocks.
309system.cpu.icache.sampled_refs 7144 # Sample count of references to valid blocks.
310system.cpu.icache.avg_refs 25663.488802 # Average number of references to valid blocks.
|
311system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 311system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
312system.cpu.icache.occ_blocks::cpu.inst 1042.048866 # Average occupied blocks per requestor
313system.cpu.icache.occ_percent::cpu.inst 0.508813 # Average percentage of cache occupancy
314system.cpu.icache.occ_percent::total 0.508813 # Average percentage of cache occupancy
315system.cpu.icache.ReadReq_hits::cpu.inst 183260633 # number of ReadReq hits
316system.cpu.icache.ReadReq_hits::total 183260633 # number of ReadReq hits
317system.cpu.icache.demand_hits::cpu.inst 183260633 # number of demand (read+write) hits
318system.cpu.icache.demand_hits::total 183260633 # number of demand (read+write) hits
319system.cpu.icache.overall_hits::cpu.inst 183260633 # number of overall hits
320system.cpu.icache.overall_hits::total 183260633 # number of overall hits
321system.cpu.icache.ReadReq_misses::cpu.inst 217941 # number of ReadReq misses
322system.cpu.icache.ReadReq_misses::total 217941 # number of ReadReq misses
323system.cpu.icache.demand_misses::cpu.inst 217941 # number of demand (read+write) misses
324system.cpu.icache.demand_misses::total 217941 # number of demand (read+write) misses
325system.cpu.icache.overall_misses::cpu.inst 217941 # number of overall misses
326system.cpu.icache.overall_misses::total 217941 # number of overall misses
327system.cpu.icache.ReadReq_miss_latency::cpu.inst 1509664000 # number of ReadReq miss cycles
328system.cpu.icache.ReadReq_miss_latency::total 1509664000 # number of ReadReq miss cycles
329system.cpu.icache.demand_miss_latency::cpu.inst 1509664000 # number of demand (read+write) miss cycles
330system.cpu.icache.demand_miss_latency::total 1509664000 # number of demand (read+write) miss cycles
331system.cpu.icache.overall_miss_latency::cpu.inst 1509664000 # number of overall miss cycles
332system.cpu.icache.overall_miss_latency::total 1509664000 # number of overall miss cycles
333system.cpu.icache.ReadReq_accesses::cpu.inst 183478574 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.ReadReq_accesses::total 183478574 # number of ReadReq accesses(hits+misses)
335system.cpu.icache.demand_accesses::cpu.inst 183478574 # number of demand (read+write) accesses
336system.cpu.icache.demand_accesses::total 183478574 # number of demand (read+write) accesses
337system.cpu.icache.overall_accesses::cpu.inst 183478574 # number of overall (read+write) accesses
338system.cpu.icache.overall_accesses::total 183478574 # number of overall (read+write) accesses
339system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001188 # miss rate for ReadReq accesses
340system.cpu.icache.ReadReq_miss_rate::total 0.001188 # miss rate for ReadReq accesses
341system.cpu.icache.demand_miss_rate::cpu.inst 0.001188 # miss rate for demand accesses
342system.cpu.icache.demand_miss_rate::total 0.001188 # miss rate for demand accesses
343system.cpu.icache.overall_miss_rate::cpu.inst 0.001188 # miss rate for overall accesses
344system.cpu.icache.overall_miss_rate::total 0.001188 # miss rate for overall accesses
345system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6926.938942 # average ReadReq miss latency
346system.cpu.icache.ReadReq_avg_miss_latency::total 6926.938942 # average ReadReq miss latency
347system.cpu.icache.demand_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency
348system.cpu.icache.demand_avg_miss_latency::total 6926.938942 # average overall miss latency
349system.cpu.icache.overall_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency
350system.cpu.icache.overall_avg_miss_latency::total 6926.938942 # average overall miss latency
| 312system.cpu.icache.occ_blocks::cpu.inst 1043.833365 # Average occupied blocks per requestor
313system.cpu.icache.occ_percent::cpu.inst 0.509684 # Average percentage of cache occupancy
314system.cpu.icache.occ_percent::total 0.509684 # Average percentage of cache occupancy
315system.cpu.icache.ReadReq_hits::cpu.inst 183356988 # number of ReadReq hits
316system.cpu.icache.ReadReq_hits::total 183356988 # number of ReadReq hits
317system.cpu.icache.demand_hits::cpu.inst 183356988 # number of demand (read+write) hits
318system.cpu.icache.demand_hits::total 183356988 # number of demand (read+write) hits
319system.cpu.icache.overall_hits::cpu.inst 183356988 # number of overall hits
320system.cpu.icache.overall_hits::total 183356988 # number of overall hits
321system.cpu.icache.ReadReq_misses::cpu.inst 222491 # number of ReadReq misses
322system.cpu.icache.ReadReq_misses::total 222491 # number of ReadReq misses
323system.cpu.icache.demand_misses::cpu.inst 222491 # number of demand (read+write) misses
324system.cpu.icache.demand_misses::total 222491 # number of demand (read+write) misses
325system.cpu.icache.overall_misses::cpu.inst 222491 # number of overall misses
326system.cpu.icache.overall_misses::total 222491 # number of overall misses
327system.cpu.icache.ReadReq_miss_latency::cpu.inst 1555664000 # number of ReadReq miss cycles
328system.cpu.icache.ReadReq_miss_latency::total 1555664000 # number of ReadReq miss cycles
329system.cpu.icache.demand_miss_latency::cpu.inst 1555664000 # number of demand (read+write) miss cycles
330system.cpu.icache.demand_miss_latency::total 1555664000 # number of demand (read+write) miss cycles
331system.cpu.icache.overall_miss_latency::cpu.inst 1555664000 # number of overall miss cycles
332system.cpu.icache.overall_miss_latency::total 1555664000 # number of overall miss cycles
333system.cpu.icache.ReadReq_accesses::cpu.inst 183579479 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.ReadReq_accesses::total 183579479 # number of ReadReq accesses(hits+misses)
335system.cpu.icache.demand_accesses::cpu.inst 183579479 # number of demand (read+write) accesses
336system.cpu.icache.demand_accesses::total 183579479 # number of demand (read+write) accesses
337system.cpu.icache.overall_accesses::cpu.inst 183579479 # number of overall (read+write) accesses
338system.cpu.icache.overall_accesses::total 183579479 # number of overall (read+write) accesses
339system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001212 # miss rate for ReadReq accesses
340system.cpu.icache.ReadReq_miss_rate::total 0.001212 # miss rate for ReadReq accesses
341system.cpu.icache.demand_miss_rate::cpu.inst 0.001212 # miss rate for demand accesses
342system.cpu.icache.demand_miss_rate::total 0.001212 # miss rate for demand accesses
343system.cpu.icache.overall_miss_rate::cpu.inst 0.001212 # miss rate for overall accesses
344system.cpu.icache.overall_miss_rate::total 0.001212 # miss rate for overall accesses
345system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6992.031138 # average ReadReq miss latency
346system.cpu.icache.ReadReq_avg_miss_latency::total 6992.031138 # average ReadReq miss latency
347system.cpu.icache.demand_avg_miss_latency::cpu.inst 6992.031138 # average overall miss latency
348system.cpu.icache.demand_avg_miss_latency::total 6992.031138 # average overall miss latency
349system.cpu.icache.overall_avg_miss_latency::cpu.inst 6992.031138 # average overall miss latency
350system.cpu.icache.overall_avg_miss_latency::total 6992.031138 # average overall miss latency
|
351system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
352system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
353system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
354system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
355system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
356system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
357system.cpu.icache.fast_writes 0 # number of fast writes performed
358system.cpu.icache.cache_copies 0 # number of cache copies performed
359system.cpu.icache.writebacks::writebacks 8 # number of writebacks
360system.cpu.icache.writebacks::total 8 # number of writebacks
| 351system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
352system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
353system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
354system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
355system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
356system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
357system.cpu.icache.fast_writes 0 # number of fast writes performed
358system.cpu.icache.cache_copies 0 # number of cache copies performed
359system.cpu.icache.writebacks::writebacks 8 # number of writebacks
360system.cpu.icache.writebacks::total 8 # number of writebacks
|
361system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1622 # number of ReadReq MSHR hits
362system.cpu.icache.ReadReq_mshr_hits::total 1622 # number of ReadReq MSHR hits
363system.cpu.icache.demand_mshr_hits::cpu.inst 1622 # number of demand (read+write) MSHR hits
364system.cpu.icache.demand_mshr_hits::total 1622 # number of demand (read+write) MSHR hits
365system.cpu.icache.overall_mshr_hits::cpu.inst 1622 # number of overall MSHR hits
366system.cpu.icache.overall_mshr_hits::total 1622 # number of overall MSHR hits
367system.cpu.icache.ReadReq_mshr_misses::cpu.inst 216319 # number of ReadReq MSHR misses
368system.cpu.icache.ReadReq_mshr_misses::total 216319 # number of ReadReq MSHR misses
369system.cpu.icache.demand_mshr_misses::cpu.inst 216319 # number of demand (read+write) MSHR misses
370system.cpu.icache.demand_mshr_misses::total 216319 # number of demand (read+write) MSHR misses
371system.cpu.icache.overall_mshr_misses::cpu.inst 216319 # number of overall MSHR misses
372system.cpu.icache.overall_mshr_misses::total 216319 # number of overall MSHR misses
373system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 823021000 # number of ReadReq MSHR miss cycles
374system.cpu.icache.ReadReq_mshr_miss_latency::total 823021000 # number of ReadReq MSHR miss cycles
375system.cpu.icache.demand_mshr_miss_latency::cpu.inst 823021000 # number of demand (read+write) MSHR miss cycles
376system.cpu.icache.demand_mshr_miss_latency::total 823021000 # number of demand (read+write) MSHR miss cycles
377system.cpu.icache.overall_mshr_miss_latency::cpu.inst 823021000 # number of overall MSHR miss cycles
378system.cpu.icache.overall_mshr_miss_latency::total 823021000 # number of overall MSHR miss cycles
379system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for ReadReq accesses
380system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001179 # mshr miss rate for ReadReq accesses
381system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for demand accesses
382system.cpu.icache.demand_mshr_miss_rate::total 0.001179 # mshr miss rate for demand accesses
383system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for overall accesses
384system.cpu.icache.overall_mshr_miss_rate::total 0.001179 # mshr miss rate for overall accesses
385system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3804.663483 # average ReadReq mshr miss latency
386system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3804.663483 # average ReadReq mshr miss latency
387system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency
388system.cpu.icache.demand_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency
389system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency
390system.cpu.icache.overall_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency
| 361system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1714 # number of ReadReq MSHR hits
362system.cpu.icache.ReadReq_mshr_hits::total 1714 # number of ReadReq MSHR hits
363system.cpu.icache.demand_mshr_hits::cpu.inst 1714 # number of demand (read+write) MSHR hits
364system.cpu.icache.demand_mshr_hits::total 1714 # number of demand (read+write) MSHR hits
365system.cpu.icache.overall_mshr_hits::cpu.inst 1714 # number of overall MSHR hits
366system.cpu.icache.overall_mshr_hits::total 1714 # number of overall MSHR hits
367system.cpu.icache.ReadReq_mshr_misses::cpu.inst 220777 # number of ReadReq MSHR misses
368system.cpu.icache.ReadReq_mshr_misses::total 220777 # number of ReadReq MSHR misses
369system.cpu.icache.demand_mshr_misses::cpu.inst 220777 # number of demand (read+write) MSHR misses
370system.cpu.icache.demand_mshr_misses::total 220777 # number of demand (read+write) MSHR misses
371system.cpu.icache.overall_mshr_misses::cpu.inst 220777 # number of overall MSHR misses
372system.cpu.icache.overall_mshr_misses::total 220777 # number of overall MSHR misses
373system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 807311500 # number of ReadReq MSHR miss cycles
374system.cpu.icache.ReadReq_mshr_miss_latency::total 807311500 # number of ReadReq MSHR miss cycles
375system.cpu.icache.demand_mshr_miss_latency::cpu.inst 807311500 # number of demand (read+write) MSHR miss cycles
376system.cpu.icache.demand_mshr_miss_latency::total 807311500 # number of demand (read+write) MSHR miss cycles
377system.cpu.icache.overall_mshr_miss_latency::cpu.inst 807311500 # number of overall MSHR miss cycles
378system.cpu.icache.overall_mshr_miss_latency::total 807311500 # number of overall MSHR miss cycles
379system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses
380system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses
381system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses
382system.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses
383system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses
384system.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses
385system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3656.682988 # average ReadReq mshr miss latency
386system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3656.682988 # average ReadReq mshr miss latency
387system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3656.682988 # average overall mshr miss latency
388system.cpu.icache.demand_avg_mshr_miss_latency::total 3656.682988 # average overall mshr miss latency
389system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3656.682988 # average overall mshr miss latency
390system.cpu.icache.overall_avg_mshr_miss_latency::total 3656.682988 # average overall mshr miss latency
|
391system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 391system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
392system.cpu.dcache.replacements 2527069 # number of replacements
393system.cpu.dcache.tagsinuse 4086.938445 # Cycle average of tags in use
394system.cpu.dcache.total_refs 415239447 # Total number of references to valid blocks.
395system.cpu.dcache.sampled_refs 2531165 # Sample count of references to valid blocks.
396system.cpu.dcache.avg_refs 164.050722 # Average number of references to valid blocks.
397system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit.
398system.cpu.dcache.occ_blocks::cpu.data 4086.938445 # Average occupied blocks per requestor
399system.cpu.dcache.occ_percent::cpu.data 0.997788 # Average percentage of cache occupancy
400system.cpu.dcache.occ_percent::total 0.997788 # Average percentage of cache occupancy
401system.cpu.dcache.ReadReq_hits::cpu.data 266396251 # number of ReadReq hits
402system.cpu.dcache.ReadReq_hits::total 266396251 # number of ReadReq hits
403system.cpu.dcache.WriteReq_hits::cpu.data 148172005 # number of WriteReq hits
404system.cpu.dcache.WriteReq_hits::total 148172005 # number of WriteReq hits
405system.cpu.dcache.demand_hits::cpu.data 414568256 # number of demand (read+write) hits
406system.cpu.dcache.demand_hits::total 414568256 # number of demand (read+write) hits
407system.cpu.dcache.overall_hits::cpu.data 414568256 # number of overall hits
408system.cpu.dcache.overall_hits::total 414568256 # number of overall hits
409system.cpu.dcache.ReadReq_misses::cpu.data 2642162 # number of ReadReq misses
410system.cpu.dcache.ReadReq_misses::total 2642162 # number of ReadReq misses
411system.cpu.dcache.WriteReq_misses::cpu.data 988196 # number of WriteReq misses
412system.cpu.dcache.WriteReq_misses::total 988196 # number of WriteReq misses
413system.cpu.dcache.demand_misses::cpu.data 3630358 # number of demand (read+write) misses
414system.cpu.dcache.demand_misses::total 3630358 # number of demand (read+write) misses
415system.cpu.dcache.overall_misses::cpu.data 3630358 # number of overall misses
416system.cpu.dcache.overall_misses::total 3630358 # number of overall misses
417system.cpu.dcache.ReadReq_miss_latency::cpu.data 33785416000 # number of ReadReq miss cycles
418system.cpu.dcache.ReadReq_miss_latency::total 33785416000 # number of ReadReq miss cycles
419system.cpu.dcache.WriteReq_miss_latency::cpu.data 18850913500 # number of WriteReq miss cycles
420system.cpu.dcache.WriteReq_miss_latency::total 18850913500 # number of WriteReq miss cycles
421system.cpu.dcache.demand_miss_latency::cpu.data 52636329500 # number of demand (read+write) miss cycles
422system.cpu.dcache.demand_miss_latency::total 52636329500 # number of demand (read+write) miss cycles
423system.cpu.dcache.overall_miss_latency::cpu.data 52636329500 # number of overall miss cycles
424system.cpu.dcache.overall_miss_latency::total 52636329500 # number of overall miss cycles
425system.cpu.dcache.ReadReq_accesses::cpu.data 269038413 # number of ReadReq accesses(hits+misses)
426system.cpu.dcache.ReadReq_accesses::total 269038413 # number of ReadReq accesses(hits+misses)
| 392system.cpu.dcache.replacements 2526932 # number of replacements
393system.cpu.dcache.tagsinuse 4087.002869 # Cycle average of tags in use
394system.cpu.dcache.total_refs 415155555 # Total number of references to valid blocks.
395system.cpu.dcache.sampled_refs 2531028 # Sample count of references to valid blocks.
396system.cpu.dcache.avg_refs 164.026457 # Average number of references to valid blocks.
397system.cpu.dcache.warmup_cycle 2119650000 # Cycle when the warmup percentage was hit.
398system.cpu.dcache.occ_blocks::cpu.data 4087.002869 # Average occupied blocks per requestor
399system.cpu.dcache.occ_percent::cpu.data 0.997803 # Average percentage of cache occupancy
400system.cpu.dcache.occ_percent::total 0.997803 # Average percentage of cache occupancy
401system.cpu.dcache.ReadReq_hits::cpu.data 266306304 # number of ReadReq hits
402system.cpu.dcache.ReadReq_hits::total 266306304 # number of ReadReq hits
403system.cpu.dcache.WriteReq_hits::cpu.data 148172784 # number of WriteReq hits
404system.cpu.dcache.WriteReq_hits::total 148172784 # number of WriteReq hits
405system.cpu.dcache.demand_hits::cpu.data 414479088 # number of demand (read+write) hits
406system.cpu.dcache.demand_hits::total 414479088 # number of demand (read+write) hits
407system.cpu.dcache.overall_hits::cpu.data 414479088 # number of overall hits
408system.cpu.dcache.overall_hits::total 414479088 # number of overall hits
409system.cpu.dcache.ReadReq_misses::cpu.data 2652001 # number of ReadReq misses
410system.cpu.dcache.ReadReq_misses::total 2652001 # number of ReadReq misses
411system.cpu.dcache.WriteReq_misses::cpu.data 987417 # number of WriteReq misses
412system.cpu.dcache.WriteReq_misses::total 987417 # number of WriteReq misses
413system.cpu.dcache.demand_misses::cpu.data 3639418 # number of demand (read+write) misses
414system.cpu.dcache.demand_misses::total 3639418 # number of demand (read+write) misses
415system.cpu.dcache.overall_misses::cpu.data 3639418 # number of overall misses
416system.cpu.dcache.overall_misses::total 3639418 # number of overall misses
417system.cpu.dcache.ReadReq_miss_latency::cpu.data 36687997500 # number of ReadReq miss cycles
418system.cpu.dcache.ReadReq_miss_latency::total 36687997500 # number of ReadReq miss cycles
419system.cpu.dcache.WriteReq_miss_latency::cpu.data 18991122500 # number of WriteReq miss cycles
420system.cpu.dcache.WriteReq_miss_latency::total 18991122500 # number of WriteReq miss cycles
421system.cpu.dcache.demand_miss_latency::cpu.data 55679120000 # number of demand (read+write) miss cycles
422system.cpu.dcache.demand_miss_latency::total 55679120000 # number of demand (read+write) miss cycles
423system.cpu.dcache.overall_miss_latency::cpu.data 55679120000 # number of overall miss cycles
424system.cpu.dcache.overall_miss_latency::total 55679120000 # number of overall miss cycles
425system.cpu.dcache.ReadReq_accesses::cpu.data 268958305 # number of ReadReq accesses(hits+misses)
426system.cpu.dcache.ReadReq_accesses::total 268958305 # number of ReadReq accesses(hits+misses)
|
427system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
428system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
| 427system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
428system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
429system.cpu.dcache.demand_accesses::cpu.data 418198614 # number of demand (read+write) accesses
430system.cpu.dcache.demand_accesses::total 418198614 # number of demand (read+write) accesses
431system.cpu.dcache.overall_accesses::cpu.data 418198614 # number of overall (read+write) accesses
432system.cpu.dcache.overall_accesses::total 418198614 # number of overall (read+write) accesses
433system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009821 # miss rate for ReadReq accesses
434system.cpu.dcache.ReadReq_miss_rate::total 0.009821 # miss rate for ReadReq accesses
435system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006625 # miss rate for WriteReq accesses
436system.cpu.dcache.WriteReq_miss_rate::total 0.006625 # miss rate for WriteReq accesses
437system.cpu.dcache.demand_miss_rate::cpu.data 0.008681 # miss rate for demand accesses
438system.cpu.dcache.demand_miss_rate::total 0.008681 # miss rate for demand accesses
439system.cpu.dcache.overall_miss_rate::cpu.data 0.008681 # miss rate for overall accesses
440system.cpu.dcache.overall_miss_rate::total 0.008681 # miss rate for overall accesses
441system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12787.034255 # average ReadReq miss latency
442system.cpu.dcache.ReadReq_avg_miss_latency::total 12787.034255 # average ReadReq miss latency
443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19076.087638 # average WriteReq miss latency
444system.cpu.dcache.WriteReq_avg_miss_latency::total 19076.087638 # average WriteReq miss latency
445system.cpu.dcache.demand_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency
446system.cpu.dcache.demand_avg_miss_latency::total 14498.936331 # average overall miss latency
447system.cpu.dcache.overall_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency
448system.cpu.dcache.overall_avg_miss_latency::total 14498.936331 # average overall miss latency
| 429system.cpu.dcache.demand_accesses::cpu.data 418118506 # number of demand (read+write) accesses
430system.cpu.dcache.demand_accesses::total 418118506 # number of demand (read+write) accesses
431system.cpu.dcache.overall_accesses::cpu.data 418118506 # number of overall (read+write) accesses
432system.cpu.dcache.overall_accesses::total 418118506 # number of overall (read+write) accesses
433system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009860 # miss rate for ReadReq accesses
434system.cpu.dcache.ReadReq_miss_rate::total 0.009860 # miss rate for ReadReq accesses
435system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses
436system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses
437system.cpu.dcache.demand_miss_rate::cpu.data 0.008704 # miss rate for demand accesses
438system.cpu.dcache.demand_miss_rate::total 0.008704 # miss rate for demand accesses
439system.cpu.dcache.overall_miss_rate::cpu.data 0.008704 # miss rate for overall accesses
440system.cpu.dcache.overall_miss_rate::total 0.008704 # miss rate for overall accesses
441system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13834.081322 # average ReadReq miss latency
442system.cpu.dcache.ReadReq_avg_miss_latency::total 13834.081322 # average ReadReq miss latency
443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19233.133013 # average WriteReq miss latency
444system.cpu.dcache.WriteReq_avg_miss_latency::total 19233.133013 # average WriteReq miss latency
445system.cpu.dcache.demand_avg_miss_latency::cpu.data 15298.907682 # average overall miss latency
446system.cpu.dcache.demand_avg_miss_latency::total 15298.907682 # average overall miss latency
447system.cpu.dcache.overall_avg_miss_latency::cpu.data 15298.907682 # average overall miss latency
448system.cpu.dcache.overall_avg_miss_latency::total 15298.907682 # average overall miss latency
|
449system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
450system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
451system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
452system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
453system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
454system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
455system.cpu.dcache.fast_writes 0 # number of fast writes performed
456system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 449system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
450system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
451system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
452system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
453system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
454system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
455system.cpu.dcache.fast_writes 0 # number of fast writes performed
456system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
457system.cpu.dcache.writebacks::writebacks 2302786 # number of writebacks
458system.cpu.dcache.writebacks::total 2302786 # number of writebacks
459system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881124 # number of ReadReq MSHR hits
460system.cpu.dcache.ReadReq_mshr_hits::total 881124 # number of ReadReq MSHR hits
461system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8927 # number of WriteReq MSHR hits
462system.cpu.dcache.WriteReq_mshr_hits::total 8927 # number of WriteReq MSHR hits
463system.cpu.dcache.demand_mshr_hits::cpu.data 890051 # number of demand (read+write) MSHR hits
464system.cpu.dcache.demand_mshr_hits::total 890051 # number of demand (read+write) MSHR hits
465system.cpu.dcache.overall_mshr_hits::cpu.data 890051 # number of overall MSHR hits
466system.cpu.dcache.overall_mshr_hits::total 890051 # number of overall MSHR hits
467system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761038 # number of ReadReq MSHR misses
468system.cpu.dcache.ReadReq_mshr_misses::total 1761038 # number of ReadReq MSHR misses
469system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979269 # number of WriteReq MSHR misses
470system.cpu.dcache.WriteReq_mshr_misses::total 979269 # number of WriteReq MSHR misses
471system.cpu.dcache.demand_mshr_misses::cpu.data 2740307 # number of demand (read+write) MSHR misses
472system.cpu.dcache.demand_mshr_misses::total 2740307 # number of demand (read+write) MSHR misses
473system.cpu.dcache.overall_mshr_misses::cpu.data 2740307 # number of overall MSHR misses
474system.cpu.dcache.overall_mshr_misses::total 2740307 # number of overall MSHR misses
475system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11264952000 # number of ReadReq MSHR miss cycles
476system.cpu.dcache.ReadReq_mshr_miss_latency::total 11264952000 # number of ReadReq MSHR miss cycles
477system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15850782000 # number of WriteReq MSHR miss cycles
478system.cpu.dcache.WriteReq_mshr_miss_latency::total 15850782000 # number of WriteReq MSHR miss cycles
479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27115734000 # number of demand (read+write) MSHR miss cycles
480system.cpu.dcache.demand_mshr_miss_latency::total 27115734000 # number of demand (read+write) MSHR miss cycles
481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27115734000 # number of overall MSHR miss cycles
482system.cpu.dcache.overall_mshr_miss_latency::total 27115734000 # number of overall MSHR miss cycles
483system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006546 # mshr miss rate for ReadReq accesses
484system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006546 # mshr miss rate for ReadReq accesses
485system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006565 # mshr miss rate for WriteReq accesses
486system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006565 # mshr miss rate for WriteReq accesses
487system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006553 # mshr miss rate for demand accesses
488system.cpu.dcache.demand_mshr_miss_rate::total 0.006553 # mshr miss rate for demand accesses
489system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006553 # mshr miss rate for overall accesses
490system.cpu.dcache.overall_mshr_miss_rate::total 0.006553 # mshr miss rate for overall accesses
491system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6396.768270 # average ReadReq mshr miss latency
492system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6396.768270 # average ReadReq mshr miss latency
493system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16186.341036 # average WriteReq mshr miss latency
494system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16186.341036 # average WriteReq mshr miss latency
495system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9895.144595 # average overall mshr miss latency
496system.cpu.dcache.demand_avg_mshr_miss_latency::total 9895.144595 # average overall mshr miss latency
497system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9895.144595 # average overall mshr miss latency
498system.cpu.dcache.overall_avg_mshr_miss_latency::total 9895.144595 # average overall mshr miss latency
| 457system.cpu.dcache.writebacks::writebacks 2302590 # number of writebacks
458system.cpu.dcache.writebacks::total 2302590 # number of writebacks
459system.cpu.dcache.ReadReq_mshr_hits::cpu.data 891786 # number of ReadReq MSHR hits
460system.cpu.dcache.ReadReq_mshr_hits::total 891786 # number of ReadReq MSHR hits
461system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3028 # number of WriteReq MSHR hits
462system.cpu.dcache.WriteReq_mshr_hits::total 3028 # number of WriteReq MSHR hits
463system.cpu.dcache.demand_mshr_hits::cpu.data 894814 # number of demand (read+write) MSHR hits
464system.cpu.dcache.demand_mshr_hits::total 894814 # number of demand (read+write) MSHR hits
465system.cpu.dcache.overall_mshr_hits::cpu.data 894814 # number of overall MSHR hits
466system.cpu.dcache.overall_mshr_hits::total 894814 # number of overall MSHR hits
467system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760215 # number of ReadReq MSHR misses
468system.cpu.dcache.ReadReq_mshr_misses::total 1760215 # number of ReadReq MSHR misses
469system.cpu.dcache.WriteReq_mshr_misses::cpu.data 984389 # number of WriteReq MSHR misses
470system.cpu.dcache.WriteReq_mshr_misses::total 984389 # number of WriteReq MSHR misses
471system.cpu.dcache.demand_mshr_misses::cpu.data 2744604 # number of demand (read+write) MSHR misses
472system.cpu.dcache.demand_mshr_misses::total 2744604 # number of demand (read+write) MSHR misses
473system.cpu.dcache.overall_mshr_misses::cpu.data 2744604 # number of overall MSHR misses
474system.cpu.dcache.overall_mshr_misses::total 2744604 # number of overall MSHR misses
475system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12497957644 # number of ReadReq MSHR miss cycles
476system.cpu.dcache.ReadReq_mshr_miss_latency::total 12497957644 # number of ReadReq MSHR miss cycles
477system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15832587002 # number of WriteReq MSHR miss cycles
478system.cpu.dcache.WriteReq_mshr_miss_latency::total 15832587002 # number of WriteReq MSHR miss cycles
479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28330544646 # number of demand (read+write) MSHR miss cycles
480system.cpu.dcache.demand_mshr_miss_latency::total 28330544646 # number of demand (read+write) MSHR miss cycles
481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28330544646 # number of overall MSHR miss cycles
482system.cpu.dcache.overall_mshr_miss_latency::total 28330544646 # number of overall MSHR miss cycles
483system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006545 # mshr miss rate for ReadReq accesses
484system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006545 # mshr miss rate for ReadReq accesses
485system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006600 # mshr miss rate for WriteReq accesses
486system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006600 # mshr miss rate for WriteReq accesses
487system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006564 # mshr miss rate for demand accesses
488system.cpu.dcache.demand_mshr_miss_rate::total 0.006564 # mshr miss rate for demand accesses
489system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006564 # mshr miss rate for overall accesses
490system.cpu.dcache.overall_mshr_miss_rate::total 0.006564 # mshr miss rate for overall accesses
491system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7100.244938 # average ReadReq mshr miss latency
492system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7100.244938 # average ReadReq mshr miss latency
493system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16083.669161 # average WriteReq mshr miss latency
494system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.669161 # average WriteReq mshr miss latency
495system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10322.270406 # average overall mshr miss latency
496system.cpu.dcache.demand_avg_mshr_miss_latency::total 10322.270406 # average overall mshr miss latency
497system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10322.270406 # average overall mshr miss latency
498system.cpu.dcache.overall_avg_mshr_miss_latency::total 10322.270406 # average overall mshr miss latency
|
499system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 499system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
500system.cpu.l2cache.replacements 408621 # number of replacements
501system.cpu.l2cache.tagsinuse 29300.466705 # Cycle average of tags in use
502system.cpu.l2cache.total_refs 3609267 # Total number of references to valid blocks.
503system.cpu.l2cache.sampled_refs 440961 # Sample count of references to valid blocks.
504system.cpu.l2cache.avg_refs 8.185003 # Average number of references to valid blocks.
505system.cpu.l2cache.warmup_cycle 219912062000 # Cycle when the warmup percentage was hit.
506system.cpu.l2cache.occ_blocks::writebacks 21087.117194 # Average occupied blocks per requestor
507system.cpu.l2cache.occ_blocks::cpu.inst 148.252410 # Average occupied blocks per requestor
508system.cpu.l2cache.occ_blocks::cpu.data 8065.097101 # Average occupied blocks per requestor
509system.cpu.l2cache.occ_percent::writebacks 0.643528 # Average percentage of cache occupancy
510system.cpu.l2cache.occ_percent::cpu.inst 0.004524 # Average percentage of cache occupancy
511system.cpu.l2cache.occ_percent::cpu.data 0.246127 # Average percentage of cache occupancy
512system.cpu.l2cache.occ_percent::total 0.894179 # Average percentage of cache occupancy
513system.cpu.l2cache.ReadReq_hits::cpu.inst 3623 # number of ReadReq hits
514system.cpu.l2cache.ReadReq_hits::cpu.data 1537767 # number of ReadReq hits
515system.cpu.l2cache.ReadReq_hits::total 1541390 # number of ReadReq hits
516system.cpu.l2cache.Writeback_hits::writebacks 2302794 # number of Writeback hits
517system.cpu.l2cache.Writeback_hits::total 2302794 # number of Writeback hits
518system.cpu.l2cache.UpgradeReq_hits::cpu.data 1289 # number of UpgradeReq hits
519system.cpu.l2cache.UpgradeReq_hits::total 1289 # number of UpgradeReq hits
520system.cpu.l2cache.ReadExReq_hits::cpu.data 561962 # number of ReadExReq hits
521system.cpu.l2cache.ReadExReq_hits::total 561962 # number of ReadExReq hits
522system.cpu.l2cache.demand_hits::cpu.inst 3623 # number of demand (read+write) hits
523system.cpu.l2cache.demand_hits::cpu.data 2099729 # number of demand (read+write) hits
524system.cpu.l2cache.demand_hits::total 2103352 # number of demand (read+write) hits
525system.cpu.l2cache.overall_hits::cpu.inst 3623 # number of overall hits
526system.cpu.l2cache.overall_hits::cpu.data 2099729 # number of overall hits
527system.cpu.l2cache.overall_hits::total 2103352 # number of overall hits
528system.cpu.l2cache.ReadReq_misses::cpu.inst 3448 # number of ReadReq misses
529system.cpu.l2cache.ReadReq_misses::cpu.data 222182 # number of ReadReq misses
530system.cpu.l2cache.ReadReq_misses::total 225630 # number of ReadReq misses
531system.cpu.l2cache.UpgradeReq_misses::cpu.data 207844 # number of UpgradeReq misses
532system.cpu.l2cache.UpgradeReq_misses::total 207844 # number of UpgradeReq misses
533system.cpu.l2cache.ReadExReq_misses::cpu.data 209183 # number of ReadExReq misses
534system.cpu.l2cache.ReadExReq_misses::total 209183 # number of ReadExReq misses
535system.cpu.l2cache.demand_misses::cpu.inst 3448 # number of demand (read+write) misses
536system.cpu.l2cache.demand_misses::cpu.data 431365 # number of demand (read+write) misses
537system.cpu.l2cache.demand_misses::total 434813 # number of demand (read+write) misses
538system.cpu.l2cache.overall_misses::cpu.inst 3448 # number of overall misses
539system.cpu.l2cache.overall_misses::cpu.data 431365 # number of overall misses
540system.cpu.l2cache.overall_misses::total 434813 # number of overall misses
541system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 118183500 # number of ReadReq miss cycles
542system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7588288000 # number of ReadReq miss cycles
543system.cpu.l2cache.ReadReq_miss_latency::total 7706471500 # number of ReadReq miss cycles
544system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10472000 # number of UpgradeReq miss cycles
545system.cpu.l2cache.UpgradeReq_miss_latency::total 10472000 # number of UpgradeReq miss cycles
546system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7166759500 # number of ReadExReq miss cycles
547system.cpu.l2cache.ReadExReq_miss_latency::total 7166759500 # number of ReadExReq miss cycles
548system.cpu.l2cache.demand_miss_latency::cpu.inst 118183500 # number of demand (read+write) miss cycles
549system.cpu.l2cache.demand_miss_latency::cpu.data 14755047500 # number of demand (read+write) miss cycles
550system.cpu.l2cache.demand_miss_latency::total 14873231000 # number of demand (read+write) miss cycles
551system.cpu.l2cache.overall_miss_latency::cpu.inst 118183500 # number of overall miss cycles
552system.cpu.l2cache.overall_miss_latency::cpu.data 14755047500 # number of overall miss cycles
553system.cpu.l2cache.overall_miss_latency::total 14873231000 # number of overall miss cycles
554system.cpu.l2cache.ReadReq_accesses::cpu.inst 7071 # number of ReadReq accesses(hits+misses)
555system.cpu.l2cache.ReadReq_accesses::cpu.data 1759949 # number of ReadReq accesses(hits+misses)
556system.cpu.l2cache.ReadReq_accesses::total 1767020 # number of ReadReq accesses(hits+misses)
557system.cpu.l2cache.Writeback_accesses::writebacks 2302794 # number of Writeback accesses(hits+misses)
558system.cpu.l2cache.Writeback_accesses::total 2302794 # number of Writeback accesses(hits+misses)
559system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209133 # number of UpgradeReq accesses(hits+misses)
560system.cpu.l2cache.UpgradeReq_accesses::total 209133 # number of UpgradeReq accesses(hits+misses)
561system.cpu.l2cache.ReadExReq_accesses::cpu.data 771145 # number of ReadExReq accesses(hits+misses)
562system.cpu.l2cache.ReadExReq_accesses::total 771145 # number of ReadExReq accesses(hits+misses)
563system.cpu.l2cache.demand_accesses::cpu.inst 7071 # number of demand (read+write) accesses
564system.cpu.l2cache.demand_accesses::cpu.data 2531094 # number of demand (read+write) accesses
565system.cpu.l2cache.demand_accesses::total 2538165 # number of demand (read+write) accesses
566system.cpu.l2cache.overall_accesses::cpu.inst 7071 # number of overall (read+write) accesses
567system.cpu.l2cache.overall_accesses::cpu.data 2531094 # number of overall (read+write) accesses
568system.cpu.l2cache.overall_accesses::total 2538165 # number of overall (read+write) accesses
569system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.487626 # miss rate for ReadReq accesses
570system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126243 # miss rate for ReadReq accesses
571system.cpu.l2cache.ReadReq_miss_rate::total 0.127690 # miss rate for ReadReq accesses
572system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993836 # miss rate for UpgradeReq accesses
573system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993836 # miss rate for UpgradeReq accesses
574system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271263 # miss rate for ReadExReq accesses
575system.cpu.l2cache.ReadExReq_miss_rate::total 0.271263 # miss rate for ReadExReq accesses
576system.cpu.l2cache.demand_miss_rate::cpu.inst 0.487626 # miss rate for demand accesses
577system.cpu.l2cache.demand_miss_rate::cpu.data 0.170426 # miss rate for demand accesses
578system.cpu.l2cache.demand_miss_rate::total 0.171310 # miss rate for demand accesses
579system.cpu.l2cache.overall_miss_rate::cpu.inst 0.487626 # miss rate for overall accesses
580system.cpu.l2cache.overall_miss_rate::cpu.data 0.170426 # miss rate for overall accesses
581system.cpu.l2cache.overall_miss_rate::total 0.171310 # miss rate for overall accesses
582system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34275.957077 # average ReadReq miss latency
583system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.477779 # average ReadReq miss latency
584system.cpu.l2cache.ReadReq_avg_miss_latency::total 34155.349466 # average ReadReq miss latency
585system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.383942 # average UpgradeReq miss latency
586system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.383942 # average UpgradeReq miss latency
587system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34260.716693 # average ReadExReq miss latency
588system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34260.716693 # average ReadExReq miss latency
589system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34275.957077 # average overall miss latency
590system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34205.481437 # average overall miss latency
591system.cpu.l2cache.demand_avg_miss_latency::total 34206.040298 # average overall miss latency
592system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34275.957077 # average overall miss latency
593system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34205.481437 # average overall miss latency
594system.cpu.l2cache.overall_avg_miss_latency::total 34206.040298 # average overall miss latency
| 500system.cpu.l2cache.replacements 408624 # number of replacements
501system.cpu.l2cache.tagsinuse 29310.882366 # Cycle average of tags in use
502system.cpu.l2cache.total_refs 3608909 # Total number of references to valid blocks.
503system.cpu.l2cache.sampled_refs 440968 # Sample count of references to valid blocks.
504system.cpu.l2cache.avg_refs 8.184061 # Average number of references to valid blocks.
505system.cpu.l2cache.warmup_cycle 220647003000 # Cycle when the warmup percentage was hit.
506system.cpu.l2cache.occ_blocks::writebacks 21083.148834 # Average occupied blocks per requestor
507system.cpu.l2cache.occ_blocks::cpu.inst 149.403214 # Average occupied blocks per requestor
508system.cpu.l2cache.occ_blocks::cpu.data 8078.330317 # Average occupied blocks per requestor
509system.cpu.l2cache.occ_percent::writebacks 0.643407 # Average percentage of cache occupancy
510system.cpu.l2cache.occ_percent::cpu.inst 0.004559 # Average percentage of cache occupancy
511system.cpu.l2cache.occ_percent::cpu.data 0.246531 # Average percentage of cache occupancy
512system.cpu.l2cache.occ_percent::total 0.894497 # Average percentage of cache occupancy
513system.cpu.l2cache.ReadReq_hits::cpu.inst 3622 # number of ReadReq hits
514system.cpu.l2cache.ReadReq_hits::cpu.data 1537243 # number of ReadReq hits
515system.cpu.l2cache.ReadReq_hits::total 1540865 # number of ReadReq hits
516system.cpu.l2cache.Writeback_hits::writebacks 2302598 # number of Writeback hits
517system.cpu.l2cache.Writeback_hits::total 2302598 # number of Writeback hits
518system.cpu.l2cache.UpgradeReq_hits::cpu.data 1280 # number of UpgradeReq hits
519system.cpu.l2cache.UpgradeReq_hits::total 1280 # number of UpgradeReq hits
520system.cpu.l2cache.ReadExReq_hits::cpu.data 562350 # number of ReadExReq hits
521system.cpu.l2cache.ReadExReq_hits::total 562350 # number of ReadExReq hits
522system.cpu.l2cache.demand_hits::cpu.inst 3622 # number of demand (read+write) hits
523system.cpu.l2cache.demand_hits::cpu.data 2099593 # number of demand (read+write) hits
524system.cpu.l2cache.demand_hits::total 2103215 # number of demand (read+write) hits
525system.cpu.l2cache.overall_hits::cpu.inst 3622 # number of overall hits
526system.cpu.l2cache.overall_hits::cpu.data 2099593 # number of overall hits
527system.cpu.l2cache.overall_hits::total 2103215 # number of overall hits
528system.cpu.l2cache.ReadReq_misses::cpu.inst 3475 # number of ReadReq misses
529system.cpu.l2cache.ReadReq_misses::cpu.data 222140 # number of ReadReq misses
530system.cpu.l2cache.ReadReq_misses::total 225615 # number of ReadReq misses
531system.cpu.l2cache.UpgradeReq_misses::cpu.data 212287 # number of UpgradeReq misses
532system.cpu.l2cache.UpgradeReq_misses::total 212287 # number of UpgradeReq misses
533system.cpu.l2cache.ReadExReq_misses::cpu.data 209207 # number of ReadExReq misses
534system.cpu.l2cache.ReadExReq_misses::total 209207 # number of ReadExReq misses
535system.cpu.l2cache.demand_misses::cpu.inst 3475 # number of demand (read+write) misses
536system.cpu.l2cache.demand_misses::cpu.data 431347 # number of demand (read+write) misses
537system.cpu.l2cache.demand_misses::total 434822 # number of demand (read+write) misses
538system.cpu.l2cache.overall_misses::cpu.inst 3475 # number of overall misses
539system.cpu.l2cache.overall_misses::cpu.data 431347 # number of overall misses
540system.cpu.l2cache.overall_misses::total 434822 # number of overall misses
541system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121950500 # number of ReadReq miss cycles
542system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7624838921 # number of ReadReq miss cycles
543system.cpu.l2cache.ReadReq_miss_latency::total 7746789421 # number of ReadReq miss cycles
544system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10608500 # number of UpgradeReq miss cycles
545system.cpu.l2cache.UpgradeReq_miss_latency::total 10608500 # number of UpgradeReq miss cycles
546system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7167281000 # number of ReadExReq miss cycles
547system.cpu.l2cache.ReadExReq_miss_latency::total 7167281000 # number of ReadExReq miss cycles
548system.cpu.l2cache.demand_miss_latency::cpu.inst 121950500 # number of demand (read+write) miss cycles
549system.cpu.l2cache.demand_miss_latency::cpu.data 14792119921 # number of demand (read+write) miss cycles
550system.cpu.l2cache.demand_miss_latency::total 14914070421 # number of demand (read+write) miss cycles
551system.cpu.l2cache.overall_miss_latency::cpu.inst 121950500 # number of overall miss cycles
552system.cpu.l2cache.overall_miss_latency::cpu.data 14792119921 # number of overall miss cycles
553system.cpu.l2cache.overall_miss_latency::total 14914070421 # number of overall miss cycles
554system.cpu.l2cache.ReadReq_accesses::cpu.inst 7097 # number of ReadReq accesses(hits+misses)
555system.cpu.l2cache.ReadReq_accesses::cpu.data 1759383 # number of ReadReq accesses(hits+misses)
556system.cpu.l2cache.ReadReq_accesses::total 1766480 # number of ReadReq accesses(hits+misses)
557system.cpu.l2cache.Writeback_accesses::writebacks 2302598 # number of Writeback accesses(hits+misses)
558system.cpu.l2cache.Writeback_accesses::total 2302598 # number of Writeback accesses(hits+misses)
559system.cpu.l2cache.UpgradeReq_accesses::cpu.data 213567 # number of UpgradeReq accesses(hits+misses)
560system.cpu.l2cache.UpgradeReq_accesses::total 213567 # number of UpgradeReq accesses(hits+misses)
561system.cpu.l2cache.ReadExReq_accesses::cpu.data 771557 # number of ReadExReq accesses(hits+misses)
562system.cpu.l2cache.ReadExReq_accesses::total 771557 # number of ReadExReq accesses(hits+misses)
563system.cpu.l2cache.demand_accesses::cpu.inst 7097 # number of demand (read+write) accesses
564system.cpu.l2cache.demand_accesses::cpu.data 2530940 # number of demand (read+write) accesses
565system.cpu.l2cache.demand_accesses::total 2538037 # number of demand (read+write) accesses
566system.cpu.l2cache.overall_accesses::cpu.inst 7097 # number of overall (read+write) accesses
567system.cpu.l2cache.overall_accesses::cpu.data 2530940 # number of overall (read+write) accesses
568system.cpu.l2cache.overall_accesses::total 2538037 # number of overall (read+write) accesses
569system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.489644 # miss rate for ReadReq accesses
570system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126260 # miss rate for ReadReq accesses
571system.cpu.l2cache.ReadReq_miss_rate::total 0.127720 # miss rate for ReadReq accesses
572system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994007 # miss rate for UpgradeReq accesses
573system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994007 # miss rate for UpgradeReq accesses
574system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271149 # miss rate for ReadExReq accesses
575system.cpu.l2cache.ReadExReq_miss_rate::total 0.271149 # miss rate for ReadExReq accesses
576system.cpu.l2cache.demand_miss_rate::cpu.inst 0.489644 # miss rate for demand accesses
577system.cpu.l2cache.demand_miss_rate::cpu.data 0.170430 # miss rate for demand accesses
578system.cpu.l2cache.demand_miss_rate::total 0.171322 # miss rate for demand accesses
579system.cpu.l2cache.overall_miss_rate::cpu.inst 0.489644 # miss rate for overall accesses
580system.cpu.l2cache.overall_miss_rate::cpu.data 0.170430 # miss rate for overall accesses
581system.cpu.l2cache.overall_miss_rate::total 0.171322 # miss rate for overall accesses
582system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35093.669065 # average ReadReq miss latency
583system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34324.475200 # average ReadReq miss latency
584system.cpu.l2cache.ReadReq_avg_miss_latency::total 34336.322589 # average ReadReq miss latency
585system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.972443 # average UpgradeReq miss latency
586system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.972443 # average UpgradeReq miss latency
587system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34259.279087 # average ReadExReq miss latency
588system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34259.279087 # average ReadExReq miss latency
589system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35093.669065 # average overall miss latency
590system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.854525 # average overall miss latency
591system.cpu.l2cache.demand_avg_miss_latency::total 34299.254456 # average overall miss latency
592system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35093.669065 # average overall miss latency
593system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.854525 # average overall miss latency
594system.cpu.l2cache.overall_avg_miss_latency::total 34299.254456 # average overall miss latency
|
595system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
596system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
597system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
598system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
599system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
600system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
601system.cpu.l2cache.fast_writes 0 # number of fast writes performed
602system.cpu.l2cache.cache_copies 0 # number of cache copies performed
| 595system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
596system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
597system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
598system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
599system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
600system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
601system.cpu.l2cache.fast_writes 0 # number of fast writes performed
602system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
603system.cpu.l2cache.writebacks::writebacks 324864 # number of writebacks
604system.cpu.l2cache.writebacks::total 324864 # number of writebacks
605system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3448 # number of ReadReq MSHR misses
606system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222182 # number of ReadReq MSHR misses
607system.cpu.l2cache.ReadReq_mshr_misses::total 225630 # number of ReadReq MSHR misses
608system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 207844 # number of UpgradeReq MSHR misses
609system.cpu.l2cache.UpgradeReq_mshr_misses::total 207844 # number of UpgradeReq MSHR misses
610system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209183 # number of ReadExReq MSHR misses
611system.cpu.l2cache.ReadExReq_mshr_misses::total 209183 # number of ReadExReq MSHR misses
612system.cpu.l2cache.demand_mshr_misses::cpu.inst 3448 # number of demand (read+write) MSHR misses
613system.cpu.l2cache.demand_mshr_misses::cpu.data 431365 # number of demand (read+write) MSHR misses
614system.cpu.l2cache.demand_mshr_misses::total 434813 # number of demand (read+write) MSHR misses
615system.cpu.l2cache.overall_mshr_misses::cpu.inst 3448 # number of overall MSHR misses
616system.cpu.l2cache.overall_mshr_misses::cpu.data 431365 # number of overall MSHR misses
617system.cpu.l2cache.overall_mshr_misses::total 434813 # number of overall MSHR misses
618system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107086500 # number of ReadReq MSHR miss cycles
619system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6894107000 # number of ReadReq MSHR miss cycles
620system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7001193500 # number of ReadReq MSHR miss cycles
621system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6443438500 # number of UpgradeReq MSHR miss cycles
622system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6443438500 # number of UpgradeReq MSHR miss cycles
623system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6484873000 # number of ReadExReq MSHR miss cycles
624system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6484873000 # number of ReadExReq MSHR miss cycles
625system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107086500 # number of demand (read+write) MSHR miss cycles
626system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13378980000 # number of demand (read+write) MSHR miss cycles
627system.cpu.l2cache.demand_mshr_miss_latency::total 13486066500 # number of demand (read+write) MSHR miss cycles
628system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107086500 # number of overall MSHR miss cycles
629system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13378980000 # number of overall MSHR miss cycles
630system.cpu.l2cache.overall_mshr_miss_latency::total 13486066500 # number of overall MSHR miss cycles
631system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for ReadReq accesses
632system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126243 # mshr miss rate for ReadReq accesses
633system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127690 # mshr miss rate for ReadReq accesses
634system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993836 # mshr miss rate for UpgradeReq accesses
635system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993836 # mshr miss rate for UpgradeReq accesses
636system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271263 # mshr miss rate for ReadExReq accesses
637system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271263 # mshr miss rate for ReadExReq accesses
638system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for demand accesses
639system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170426 # mshr miss rate for demand accesses
640system.cpu.l2cache.demand_mshr_miss_rate::total 0.171310 # mshr miss rate for demand accesses
641system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for overall accesses
642system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170426 # mshr miss rate for overall accesses
643system.cpu.l2cache.overall_mshr_miss_rate::total 0.171310 # mshr miss rate for overall accesses
644system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.569606 # average ReadReq mshr miss latency
645system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31029.097767 # average ReadReq mshr miss latency
646system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31029.532864 # average ReadReq mshr miss latency
647system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.320702 # average UpgradeReq mshr miss latency
648system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.320702 # average UpgradeReq mshr miss latency
649system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.956101 # average ReadExReq mshr miss latency
650system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.956101 # average ReadExReq mshr miss latency
651system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.569606 # average overall mshr miss latency
652system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31015.450952 # average overall mshr miss latency
653system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31015.784947 # average overall mshr miss latency
654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.569606 # average overall mshr miss latency
655system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31015.450952 # average overall mshr miss latency
656system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31015.784947 # average overall mshr miss latency
| 603system.cpu.l2cache.writebacks::writebacks 324861 # number of writebacks
604system.cpu.l2cache.writebacks::total 324861 # number of writebacks
605system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3475 # number of ReadReq MSHR misses
606system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222140 # number of ReadReq MSHR misses
607system.cpu.l2cache.ReadReq_mshr_misses::total 225615 # number of ReadReq MSHR misses
608system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 212287 # number of UpgradeReq MSHR misses
609system.cpu.l2cache.UpgradeReq_mshr_misses::total 212287 # number of UpgradeReq MSHR misses
610system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209207 # number of ReadExReq MSHR misses
611system.cpu.l2cache.ReadExReq_mshr_misses::total 209207 # number of ReadExReq MSHR misses
612system.cpu.l2cache.demand_mshr_misses::cpu.inst 3475 # number of demand (read+write) MSHR misses
613system.cpu.l2cache.demand_mshr_misses::cpu.data 431347 # number of demand (read+write) MSHR misses
614system.cpu.l2cache.demand_mshr_misses::total 434822 # number of demand (read+write) MSHR misses
615system.cpu.l2cache.overall_mshr_misses::cpu.inst 3475 # number of overall MSHR misses
616system.cpu.l2cache.overall_mshr_misses::cpu.data 431347 # number of overall MSHR misses
617system.cpu.l2cache.overall_mshr_misses::total 434822 # number of overall MSHR misses
618system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110937500 # number of ReadReq MSHR miss cycles
619system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934880499 # number of ReadReq MSHR miss cycles
620system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7045817999 # number of ReadReq MSHR miss cycles
621system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6582250000 # number of UpgradeReq MSHR miss cycles
622system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6582250000 # number of UpgradeReq MSHR miss cycles
623system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6487010500 # number of ReadExReq MSHR miss cycles
624system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6487010500 # number of ReadExReq MSHR miss cycles
625system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110937500 # number of demand (read+write) MSHR miss cycles
626system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421890999 # number of demand (read+write) MSHR miss cycles
627system.cpu.l2cache.demand_mshr_miss_latency::total 13532828499 # number of demand (read+write) MSHR miss cycles
628system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110937500 # number of overall MSHR miss cycles
629system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421890999 # number of overall MSHR miss cycles
630system.cpu.l2cache.overall_mshr_miss_latency::total 13532828499 # number of overall MSHR miss cycles
631system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.489644 # mshr miss rate for ReadReq accesses
632system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126260 # mshr miss rate for ReadReq accesses
633system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127720 # mshr miss rate for ReadReq accesses
634system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994007 # mshr miss rate for UpgradeReq accesses
635system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994007 # mshr miss rate for UpgradeReq accesses
636system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271149 # mshr miss rate for ReadExReq accesses
637system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271149 # mshr miss rate for ReadExReq accesses
638system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489644 # mshr miss rate for demand accesses
639system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170430 # mshr miss rate for demand accesses
640system.cpu.l2cache.demand_mshr_miss_rate::total 0.171322 # mshr miss rate for demand accesses
641system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489644 # mshr miss rate for overall accesses
642system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170430 # mshr miss rate for overall accesses
643system.cpu.l2cache.overall_mshr_miss_rate::total 0.171322 # mshr miss rate for overall accesses
644system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31924.460432 # average ReadReq mshr miss latency
645system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.513095 # average ReadReq mshr miss latency
646system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.386340 # average ReadReq mshr miss latency
647system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.373447 # average UpgradeReq mshr miss latency
648system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.373447 # average UpgradeReq mshr miss latency
649system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.616858 # average ReadExReq mshr miss latency
650system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.616858 # average ReadExReq mshr miss latency
651system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31924.460432 # average overall mshr miss latency
652system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.226609 # average overall mshr miss latency
653system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.685832 # average overall mshr miss latency
654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31924.460432 # average overall mshr miss latency
655system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.226609 # average overall mshr miss latency
656system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.685832 # average overall mshr miss latency
|
657system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
658
659---------- End Simulation Statistics ----------
| 657system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
658
659---------- End Simulation Statistics ----------
|