| stats.txt (9039:9a22621c741c) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.459938 # Number of seconds simulated 4sim_ticks 459937575500 # Number of ticks simulated 5final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.459938 # Number of seconds simulated 4sim_ticks 459937575500 # Number of ticks simulated 5final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 75971 # Simulator instruction rate (inst/s) 8host_op_rate 140479 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 42257715 # Simulator tick rate (ticks/s) 10host_mem_usage 287264 # Number of bytes of host memory used 11host_seconds 10884.11 # Real time elapsed on the host | 7host_inst_rate 70939 # Simulator instruction rate (inst/s) 8host_op_rate 131174 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39458742 # Simulator tick rate (ticks/s) 10host_mem_usage 264492 # Number of bytes of host memory used 11host_seconds 11656.16 # Real time elapsed on the host |
| 12sim_insts 826877144 # Number of instructions simulated 13sim_ops 1528988756 # Number of ops (including micro ops) simulated | 12sim_insts 826877144 # Number of instructions simulated 13sim_ops 1528988756 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 37483008 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 26316864 # Number of bytes written to this memory 17system.physmem.num_reads 585672 # Number of read requests responded to by this memory 18system.physmem.num_writes 411201 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory 16system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory 20system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s) |
| 24system.cpu.workload.num_syscalls 551 # Number of system calls 25system.cpu.numCycles 919875152 # number of cpu cycles simulated 26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups 29system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted 30system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect 31system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups --- 286 unchanged lines hidden (view full) --- 318system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles 319system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses) 320system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses) 321system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses 322system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses 323system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses 324system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses 325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses | 37system.cpu.workload.num_syscalls 551 # Number of system calls 38system.cpu.numCycles 919875152 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups 42system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted 43system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect 44system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups --- 286 unchanged lines hidden (view full) --- 331system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles 332system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses) 333system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses) 334system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses 335system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses 336system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses 337system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses 338system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses |
| 339system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses |
|
| 326system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses | 340system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses |
| 341system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses |
|
| 327system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses | 342system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses |
| 343system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses |
|
| 328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency | 344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency |
| 345system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency |
|
| 329system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency | 346system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency |
| 347system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency |
|
| 330system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency | 348system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency |
| 349system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency |
|
| 331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 337system.cpu.icache.fast_writes 0 # number of fast writes performed 338system.cpu.icache.cache_copies 0 # number of cache copies performed --- 13 unchanged lines hidden (view full) --- 352system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses 353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles 354system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles 355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles 356system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles 357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles 358system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles 359system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses | 350system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 353system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 354system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 355system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 356system.cpu.icache.fast_writes 0 # number of fast writes performed 357system.cpu.icache.cache_copies 0 # number of cache copies performed --- 13 unchanged lines hidden (view full) --- 371system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses 372system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles 373system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles 374system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles 375system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles 376system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles 377system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles 378system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses |
| 379system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses |
|
| 360system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses | 380system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses |
| 381system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses |
|
| 361system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses | 382system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses |
| 383system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses |
|
| 362system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency | 384system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency |
| 385system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency |
|
| 363system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency | 386system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency |
| 387system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency |
|
| 364system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency | 388system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency |
| 389system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency |
|
| 365system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 366system.cpu.dcache.replacements 2527239 # number of replacements 367system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use 368system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks. 369system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks. 370system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks. 371system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit. 372system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 400system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses) 401system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 402system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 403system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses 404system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses 405system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses 406system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses 407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses | 390system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 391system.cpu.dcache.replacements 2527239 # number of replacements 392system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use 393system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks. 394system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks. 395system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks. 396system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit. 397system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 425system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses) 426system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 427system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 428system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses 429system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses 430system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses 431system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses 432system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses |
| 433system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses |
|
| 408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses | 434system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses |
| 435system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses |
|
| 409system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses | 436system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses |
| 437system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses |
|
| 410system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses | 438system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses |
| 439system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses |
|
| 411system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency | 440system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency |
| 441system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency |
|
| 412system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency | 442system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency |
| 443system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency |
|
| 413system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency | 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency |
| 445system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency |
|
| 414system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency | 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency |
| 447system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency |
|
| 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.fast_writes 0 # number of fast writes performed 422system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 19 unchanged lines hidden (view full) --- 442system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles 443system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles 444system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles 445system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles 446system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles 447system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles 448system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles 449system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses | 448system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 454system.cpu.dcache.fast_writes 0 # number of fast writes performed 455system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 19 unchanged lines hidden (view full) --- 475system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles 476system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles 477system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles 478system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles 479system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles 480system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles 481system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles 482system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses |
| 483system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses |
|
| 450system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses | 484system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses |
| 485system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses |
|
| 451system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses | 486system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses |
| 487system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses |
|
| 452system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses | 488system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses |
| 489system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses |
|
| 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency | 490system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency |
| 491system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency |
|
| 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency | 492system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency |
| 493system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency |
|
| 455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency | 494system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency |
| 495system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency |
|
| 456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency | 496system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency |
| 497system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency |
|
| 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.l2cache.replacements 574865 # number of replacements 459system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use 460system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks. 461system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks. 462system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks. 463system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit. 464system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor --- 56 unchanged lines hidden (view full) --- 521system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses 522system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses 523system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses 524system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses 525system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses 526system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses 527system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses 528system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses | 498system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 499system.cpu.l2cache.replacements 574865 # number of replacements 500system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use 501system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks. 502system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks. 503system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks. 504system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit. 505system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor --- 56 unchanged lines hidden (view full) --- 562system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses 563system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses 564system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses 565system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses 566system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses 567system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses 568system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses 569system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses |
| 570system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses |
|
| 529system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses | 571system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses |
| 572system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses |
|
| 530system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses | 573system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses |
| 574system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses |
|
| 531system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses 532system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses | 575system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses 576system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses |
| 577system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses |
|
| 533system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses 534system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses | 578system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses 579system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses |
| 580system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses |
|
| 535system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency 536system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency | 581system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency 582system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency |
| 583system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency |
|
| 537system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency | 584system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency |
| 585system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency |
|
| 538system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency | 586system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency |
| 587system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency |
|
| 539system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency 540system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency | 588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency 589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency |
| 590system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency |
|
| 541system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency 542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency | 591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency 592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency |
| 593system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency |
|
| 543system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 544system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 545system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 546system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 547system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 548system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 549system.cpu.l2cache.fast_writes 0 # number of fast writes performed 550system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 22 unchanged lines hidden (view full) --- 573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles 574system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles 575system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles 576system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles 577system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles 578system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles 579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses 580system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses | 594system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 596system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 597system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 598system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 599system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 600system.cpu.l2cache.fast_writes 0 # number of fast writes performed 601system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 22 unchanged lines hidden (view full) --- 624system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles 625system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles 626system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles 627system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles 628system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles 629system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles 630system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses 631system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses |
| 632system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses |
|
| 581system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses | 633system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses |
| 634system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses |
|
| 582system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses | 635system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses |
| 636system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses |
|
| 583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses 584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses | 637system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses 638system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses |
| 639system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses |
|
| 585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses 586system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses | 640system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses 641system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses |
| 642system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses |
|
| 587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency 588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency | 643system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency 644system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency |
| 645system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency |
|
| 589system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency | 646system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency |
| 647system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency |
|
| 590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency | 648system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency |
| 649system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency |
|
| 591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency | 650system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency 651system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency |
| 652system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency |
|
| 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency | 653system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency 654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency |
| 655system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency |
|
| 595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 596 597---------- End Simulation Statistics ---------- | 656system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 657 658---------- End Simulation Statistics ---------- |