| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.460108 # Number of seconds simulated 4sim_ticks 460107924500 # Number of ticks simulated 5final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.460108 # Number of seconds simulated 4sim_ticks 460107924500 # Number of ticks simulated 5final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 106471 # Simulator instruction rate (inst/s) 8host_op_rate 196876 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59244607 # Simulator tick rate (ticks/s) 10host_mem_usage 257468 # Number of bytes of host memory used 11host_seconds 7766.24 # Real time elapsed on the host | 7host_inst_rate 59697 # Simulator instruction rate (inst/s) 8host_op_rate 110386 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33217787 # Simulator tick rate (ticks/s) 10host_mem_usage 263000 # Number of bytes of host memory used 11host_seconds 13851.25 # Real time elapsed on the host |
| 12sim_insts 826877144 # Number of instructions simulated 13sim_ops 1528988756 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 37486912 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 378624 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 26317760 # Number of bytes written to this memory 17system.physmem.num_reads 585733 # Number of read requests responded to by this memory 18system.physmem.num_writes 411215 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 306 unchanged lines hidden (view full) --- 326system.cpu.icache.overall_miss_rate::cpu.inst 0.001224 # miss rate for overall accesses 327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7309.394738 # average ReadReq miss latency 328system.cpu.icache.demand_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency 329system.cpu.icache.overall_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency 330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 826877144 # Number of instructions simulated 13sim_ops 1528988756 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 37486912 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 378624 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 26317760 # Number of bytes written to this memory 17system.physmem.num_reads 585733 # Number of read requests responded to by this memory 18system.physmem.num_writes 411215 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 306 unchanged lines hidden (view full) --- 326system.cpu.icache.overall_miss_rate::cpu.inst 0.001224 # miss rate for overall accesses 327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7309.394738 # average ReadReq miss latency 328system.cpu.icache.demand_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency 329system.cpu.icache.overall_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency 330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 334system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 335system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 334system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 335system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 336system.cpu.icache.fast_writes 0 # number of fast writes performed 337system.cpu.icache.cache_copies 0 # number of cache copies performed 338system.cpu.icache.writebacks::writebacks 8 # number of writebacks 339system.cpu.icache.writebacks::total 8 # number of writebacks 340system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2528 # number of ReadReq MSHR hits 341system.cpu.icache.ReadReq_mshr_hits::total 2528 # number of ReadReq MSHR hits 342system.cpu.icache.demand_mshr_hits::cpu.inst 2528 # number of demand (read+write) MSHR hits 343system.cpu.icache.demand_mshr_hits::total 2528 # number of demand (read+write) MSHR hits --- 66 unchanged lines hidden (view full) --- 410system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822 # average ReadReq miss latency 411system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500 # average WriteReq miss latency 412system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 336system.cpu.icache.fast_writes 0 # number of fast writes performed 337system.cpu.icache.cache_copies 0 # number of cache copies performed 338system.cpu.icache.writebacks::writebacks 8 # number of writebacks 339system.cpu.icache.writebacks::total 8 # number of writebacks 340system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2528 # number of ReadReq MSHR hits 341system.cpu.icache.ReadReq_mshr_hits::total 2528 # number of ReadReq MSHR hits 342system.cpu.icache.demand_mshr_hits::cpu.inst 2528 # number of demand (read+write) MSHR hits 343system.cpu.icache.demand_mshr_hits::total 2528 # number of demand (read+write) MSHR hits --- 66 unchanged lines hidden (view full) --- 410system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822 # average ReadReq miss latency 411system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500 # average WriteReq miss latency 412system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 418system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 418system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed 422system.cpu.dcache.writebacks::writebacks 2228961 # number of writebacks 423system.cpu.dcache.writebacks::total 2228961 # number of writebacks 424system.cpu.dcache.ReadReq_mshr_hits::cpu.data 905583 # number of ReadReq MSHR hits 425system.cpu.dcache.ReadReq_mshr_hits::total 905583 # number of ReadReq MSHR hits 426system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9205 # number of WriteReq MSHR hits 427system.cpu.dcache.WriteReq_mshr_hits::total 9205 # number of WriteReq MSHR hits --- 110 unchanged lines hidden (view full) --- 538system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency 539system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency 540system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency 541system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency 542system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 543system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 544system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 545system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed 422system.cpu.dcache.writebacks::writebacks 2228961 # number of writebacks 423system.cpu.dcache.writebacks::total 2228961 # number of writebacks 424system.cpu.dcache.ReadReq_mshr_hits::cpu.data 905583 # number of ReadReq MSHR hits 425system.cpu.dcache.ReadReq_mshr_hits::total 905583 # number of ReadReq MSHR hits 426system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9205 # number of WriteReq MSHR hits 427system.cpu.dcache.WriteReq_mshr_hits::total 9205 # number of WriteReq MSHR hits --- 110 unchanged lines hidden (view full) --- 538system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency 539system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency 540system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency 541system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency 542system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 543system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 544system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 545system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 546system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 547system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 546system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 547system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 548system.cpu.l2cache.fast_writes 0 # number of fast writes performed 549system.cpu.l2cache.cache_copies 0 # number of cache copies performed 550system.cpu.l2cache.writebacks::writebacks 411215 # number of writebacks 551system.cpu.l2cache.writebacks::total 411215 # number of writebacks 552system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5916 # number of ReadReq MSHR misses 553system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332816 # number of ReadReq MSHR misses 554system.cpu.l2cache.ReadReq_mshr_misses::total 338732 # number of ReadReq MSHR misses 555system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208530 # number of UpgradeReq MSHR misses --- 41 unchanged lines hidden --- | 548system.cpu.l2cache.fast_writes 0 # number of fast writes performed 549system.cpu.l2cache.cache_copies 0 # number of cache copies performed 550system.cpu.l2cache.writebacks::writebacks 411215 # number of writebacks 551system.cpu.l2cache.writebacks::total 411215 # number of writebacks 552system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5916 # number of ReadReq MSHR misses 553system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332816 # number of ReadReq MSHR misses 554system.cpu.l2cache.ReadReq_mshr_misses::total 338732 # number of ReadReq MSHR misses 555system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208530 # number of UpgradeReq MSHR misses --- 41 unchanged lines hidden --- |