1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.488026 # Number of seconds simulated
4sim_ticks 488026375000 # Number of ticks simulated
5final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.460108 # Number of seconds simulated
4sim_ticks 460107924500 # Number of ticks simulated
5final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 101458 # Simulator instruction rate (inst/s)
8host_op_rate 187607 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 59880945 # Simulator tick rate (ticks/s)
10host_mem_usage 257144 # Number of bytes of host memory used
11host_seconds 8149.94 # Real time elapsed on the host
| 7host_inst_rate 106471 # Simulator instruction rate (inst/s)
8host_op_rate 196876 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 59244607 # Simulator tick rate (ticks/s)
10host_mem_usage 257468 # Number of bytes of host memory used
11host_seconds 7766.24 # Real time elapsed on the host
|
12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
| 12sim_insts 826877144 # Number of instructions simulated
13sim_ops 1528988756 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read 37539712 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 26338560 # Number of bytes written to this memory
17system.physmem.num_reads 586558 # Number of read requests responded to by this memory
18system.physmem.num_writes 411540 # Number of write requests responded to by this memory
| 14system.physmem.bytes_read 37486912 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 378624 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 26317760 # Number of bytes written to this memory
17system.physmem.num_reads 585733 # Number of read requests responded to by this memory
18system.physmem.num_writes 411215 # Number of write requests responded to by this memory
|
19system.physmem.num_other 0 # Number of other requests responded to by this memory
| 19system.physmem.num_other 0 # Number of other requests responded to by this memory
|
20system.physmem.bw_read 76921482 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 711306 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 53969542 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 130891024 # Total bandwidth to/from this memory (bytes/s)
| 20system.physmem.bw_read 81474172 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 822903 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 57199102 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 138673273 # Total bandwidth to/from this memory (bytes/s)
|
24system.cpu.workload.num_syscalls 551 # Number of system calls
| 24system.cpu.workload.num_syscalls 551 # Number of system calls
|
25system.cpu.numCycles 976052751 # number of cpu cycles simulated
| 25system.cpu.numCycles 920215850 # number of cpu cycles simulated
|
26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
28system.cpu.BPredUnit.lookups 244909233 # Number of BP lookups
29system.cpu.BPredUnit.condPredicted 244909233 # Number of conditional branches predicted
30system.cpu.BPredUnit.condIncorrect 16551670 # Number of conditional branches incorrect
31system.cpu.BPredUnit.BTBLookups 235577670 # Number of BTB lookups
32system.cpu.BPredUnit.BTBHits 217623896 # Number of BTB hits
| 28system.cpu.BPredUnit.lookups 225637815 # Number of BP lookups
29system.cpu.BPredUnit.condPredicted 225637815 # Number of conditional branches predicted
30system.cpu.BPredUnit.condIncorrect 14289291 # Number of conditional branches incorrect
31system.cpu.BPredUnit.BTBLookups 160516526 # Number of BTB lookups
32system.cpu.BPredUnit.BTBHits 155855542 # Number of BTB hits
|
33system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
34system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
35system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
| 33system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
34system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
35system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
36system.cpu.fetch.icacheStallCycles 203635164 # Number of cycles fetch is stalled on an Icache miss
37system.cpu.fetch.Insts 1335786629 # Number of instructions fetch has processed
38system.cpu.fetch.Branches 244909233 # Number of branches that fetch encountered
39system.cpu.fetch.predictedBranches 217623896 # Number of branches that fetch has predicted taken
40system.cpu.fetch.Cycles 434745893 # Number of cycles fetch has run and was not squashing or blocked
41system.cpu.fetch.SquashCycles 118311552 # Number of cycles fetch has spent squashing
42system.cpu.fetch.BlockedCycles 217882141 # Number of cycles fetch has spent blocked
43system.cpu.fetch.MiscStallCycles 29891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
44system.cpu.fetch.PendingTrapStallCycles 232496 # Number of stall cycles due to pending traps
45system.cpu.fetch.CacheLines 193900404 # Number of cache lines fetched
46system.cpu.fetch.IcacheSquashes 4295951 # Number of outstanding Icache misses that were squashed
47system.cpu.fetch.rateDist::samples 958022628 # Number of instructions fetched each cycle (Total)
48system.cpu.fetch.rateDist::mean 2.604337 # Number of instructions fetched each cycle (Total)
49system.cpu.fetch.rateDist::stdev 3.317097 # Number of instructions fetched each cycle (Total)
| 36system.cpu.fetch.icacheStallCycles 191547382 # Number of cycles fetch is stalled on an Icache miss
37system.cpu.fetch.Insts 1262992642 # Number of instructions fetch has processed
38system.cpu.fetch.Branches 225637815 # Number of branches that fetch encountered
39system.cpu.fetch.predictedBranches 155855542 # Number of branches that fetch has predicted taken
40system.cpu.fetch.Cycles 392021264 # Number of cycles fetch has run and was not squashing or blocked
41system.cpu.fetch.SquashCycles 98465808 # Number of cycles fetch has spent squashing
42system.cpu.fetch.BlockedCycles 234027765 # Number of cycles fetch has spent blocked
43system.cpu.fetch.MiscStallCycles 26184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
44system.cpu.fetch.PendingTrapStallCycles 270251 # Number of stall cycles due to pending traps
45system.cpu.fetch.CacheLines 183405801 # Number of cache lines fetched
46system.cpu.fetch.IcacheSquashes 3663632 # Number of outstanding Icache misses that were squashed
47system.cpu.fetch.rateDist::samples 901816172 # Number of instructions fetched each cycle (Total)
48system.cpu.fetch.rateDist::mean 2.595997 # Number of instructions fetched each cycle (Total)
49system.cpu.fetch.rateDist::stdev 3.389419 # Number of instructions fetched each cycle (Total)
|
50system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 50system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
51system.cpu.fetch.rateDist::0 527271952 55.04% 55.04% # Number of instructions fetched each cycle (Total)
52system.cpu.fetch.rateDist::1 32005205 3.34% 58.38% # Number of instructions fetched each cycle (Total)
53system.cpu.fetch.rateDist::2 38652146 4.03% 62.41% # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::3 32799855 3.42% 65.84% # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::4 21637734 2.26% 68.10% # Number of instructions fetched each cycle (Total)
56system.cpu.fetch.rateDist::5 36320351 3.79% 71.89% # Number of instructions fetched each cycle (Total)
57system.cpu.fetch.rateDist::6 49291435 5.15% 77.03% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::7 36948107 3.86% 80.89% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::8 183095843 19.11% 100.00% # Number of instructions fetched each cycle (Total)
| 51system.cpu.fetch.rateDist::0 514254997 57.02% 57.02% # Number of instructions fetched each cycle (Total)
52system.cpu.fetch.rateDist::1 25968939 2.88% 59.90% # Number of instructions fetched each cycle (Total)
53system.cpu.fetch.rateDist::2 29098594 3.23% 63.13% # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::3 30321386 3.36% 66.49% # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::4 19622378 2.18% 68.67% # Number of instructions fetched each cycle (Total)
56system.cpu.fetch.rateDist::5 25616419 2.84% 71.51% # Number of instructions fetched each cycle (Total)
57system.cpu.fetch.rateDist::6 32613002 3.62% 75.13% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::7 30831455 3.42% 78.54% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::8 193489002 21.46% 100.00% # Number of instructions fetched each cycle (Total)
|
60system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 60system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
63system.cpu.fetch.rateDist::total 958022628 # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.branchRate 0.250918 # Number of branch fetches per cycle
65system.cpu.fetch.rate 1.368560 # Number of inst fetches per cycle
66system.cpu.decode.IdleCycles 263275556 # Number of cycles decode is idle
67system.cpu.decode.BlockedCycles 173167084 # Number of cycles decode is blocked
68system.cpu.decode.RunCycles 371540300 # Number of cycles decode is running
69system.cpu.decode.UnblockCycles 48542645 # Number of cycles decode is unblocking
70system.cpu.decode.SquashCycles 101497043 # Number of cycles decode is squashing
71system.cpu.decode.DecodedInsts 2434504159 # Number of instructions handled by decode
72system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
73system.cpu.rename.SquashCycles 101497043 # Number of cycles rename is squashing
74system.cpu.rename.IdleCycles 300930740 # Number of cycles rename is idle
75system.cpu.rename.BlockCycles 38821666 # Number of cycles rename is blocking
76system.cpu.rename.serializeStallCycles 14830 # count of cycles rename stalled for serializing inst
77system.cpu.rename.RunCycles 381234584 # Number of cycles rename is running
78system.cpu.rename.UnblockCycles 135523765 # Number of cycles rename is unblocking
79system.cpu.rename.RenamedInsts 2382098494 # Number of instructions processed by rename
80system.cpu.rename.ROBFullEvents 2610 # Number of times rename has blocked due to ROB full
81system.cpu.rename.IQFullEvents 23187923 # Number of times rename has blocked due to IQ full
82system.cpu.rename.LSQFullEvents 93850518 # Number of times rename has blocked due to LSQ full
83system.cpu.rename.FullRegisterEvents 43 # Number of times there has been no free registers
84system.cpu.rename.RenamedOperands 2215803805 # Number of destination operands rename has renamed
85system.cpu.rename.RenameLookups 5602953970 # Number of register rename lookups that rename has made
86system.cpu.rename.int_rename_lookups 5602704256 # Number of integer rename lookups
87system.cpu.rename.fp_rename_lookups 249714 # Number of floating rename lookups
| 63system.cpu.fetch.rateDist::total 901816172 # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.branchRate 0.245201 # Number of branch fetches per cycle
65system.cpu.fetch.rate 1.372496 # Number of inst fetches per cycle
66system.cpu.decode.IdleCycles 252794809 # Number of cycles decode is idle
67system.cpu.decode.BlockedCycles 186036258 # Number of cycles decode is blocked
68system.cpu.decode.RunCycles 330006285 # Number of cycles decode is running
69system.cpu.decode.UnblockCycles 49055494 # Number of cycles decode is unblocking
70system.cpu.decode.SquashCycles 83923326 # Number of cycles decode is squashing
71system.cpu.decode.DecodedInsts 2290111824 # Number of instructions handled by decode
72system.cpu.rename.SquashCycles 83923326 # Number of cycles rename is squashing
73system.cpu.rename.IdleCycles 289463344 # Number of cycles rename is idle
74system.cpu.rename.BlockCycles 42750657 # Number of cycles rename is blocking
75system.cpu.rename.serializeStallCycles 14592 # count of cycles rename stalled for serializing inst
76system.cpu.rename.RunCycles 340217218 # Number of cycles rename is running
77system.cpu.rename.UnblockCycles 145447035 # Number of cycles rename is unblocking
78system.cpu.rename.RenamedInsts 2240140505 # Number of instructions processed by rename
79system.cpu.rename.ROBFullEvents 3227 # Number of times rename has blocked due to ROB full
80system.cpu.rename.IQFullEvents 23735126 # Number of times rename has blocked due to IQ full
81system.cpu.rename.LSQFullEvents 104491412 # Number of times rename has blocked due to LSQ full
82system.cpu.rename.RenamedOperands 2078098051 # Number of destination operands rename has renamed
83system.cpu.rename.RenameLookups 5261736827 # Number of register rename lookups that rename has made
84system.cpu.rename.int_rename_lookups 5260872310 # Number of integer rename lookups
85system.cpu.rename.fp_rename_lookups 864517 # Number of floating rename lookups
|
88system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
| 86system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
|
89system.cpu.rename.UndoneMaps 788504778 # Number of HB maps that are undone due to squashing
90system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed
91system.cpu.rename.tempSerializingInsts 1415 # count of temporary serializing insts renamed
92system.cpu.rename.skidInsts 315035024 # count of insts added to the skid buffer
93system.cpu.memDep0.insertedLoads 575221657 # Number of loads inserted to the mem dependence unit.
94system.cpu.memDep0.insertedStores 225407627 # Number of stores inserted to the mem dependence unit.
95system.cpu.memDep0.conflictingLoads 224840659 # Number of conflicting loads.
96system.cpu.memDep0.conflictingStores 66447324 # Number of conflicting stores.
97system.cpu.iq.iqInstsAdded 2274732306 # Number of instructions added to the IQ (excludes non-spec)
98system.cpu.iq.iqNonSpecInstsAdded 12754 # Number of non-speculative instructions added to the IQ
99system.cpu.iq.iqInstsIssued 1918512611 # Number of instructions issued
100system.cpu.iq.iqSquashedInstsIssued 1302000 # Number of squashed instructions issued
101system.cpu.iq.iqSquashedInstsExamined 743201845 # Number of squashed instructions iterated over during squash; mainly for profiling
102system.cpu.iq.iqSquashedOperandsExamined 1165991477 # Number of squashed operands that are examined and possibly removed from graph
103system.cpu.iq.iqSquashedNonSpecRemoved 12201 # Number of squashed non-spec instructions that were removed
104system.cpu.iq.issued_per_cycle::samples 958022628 # Number of insts issued each cycle
105system.cpu.iq.issued_per_cycle::mean 2.002575 # Number of insts issued each cycle
106system.cpu.iq.issued_per_cycle::stdev 1.809760 # Number of insts issued each cycle
| 87system.cpu.rename.UndoneMaps 650799024 # Number of HB maps that are undone due to squashing
88system.cpu.rename.serializingInsts 1282 # count of serializing insts renamed
89system.cpu.rename.tempSerializingInsts 1271 # count of temporary serializing insts renamed
90system.cpu.rename.skidInsts 348171673 # count of insts added to the skid buffer
91system.cpu.memDep0.insertedLoads 540080847 # Number of loads inserted to the mem dependence unit.
92system.cpu.memDep0.insertedStores 217272434 # Number of stores inserted to the mem dependence unit.
93system.cpu.memDep0.conflictingLoads 215393524 # Number of conflicting loads.
94system.cpu.memDep0.conflictingStores 63213343 # Number of conflicting stores.
95system.cpu.iq.iqInstsAdded 2142982647 # Number of instructions added to the IQ (excludes non-spec)
96system.cpu.iq.iqNonSpecInstsAdded 62293 # Number of non-speculative instructions added to the IQ
97system.cpu.iq.iqInstsIssued 1846789239 # Number of instructions issued
98system.cpu.iq.iqSquashedInstsIssued 1603792 # Number of squashed instructions issued
99system.cpu.iq.iqSquashedInstsExamined 612307626 # Number of squashed instructions iterated over during squash; mainly for profiling
100system.cpu.iq.iqSquashedOperandsExamined 971971651 # Number of squashed operands that are examined and possibly removed from graph
101system.cpu.iq.iqSquashedNonSpecRemoved 61740 # Number of squashed non-spec instructions that were removed
102system.cpu.iq.issued_per_cycle::samples 901816172 # Number of insts issued each cycle
103system.cpu.iq.issued_per_cycle::mean 2.047856 # Number of insts issued each cycle
104system.cpu.iq.issued_per_cycle::stdev 1.805282 # Number of insts issued each cycle
|
107system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 105system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
108system.cpu.iq.issued_per_cycle::0 277706841 28.99% 28.99% # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::1 160285139 16.73% 45.72% # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::2 161386173 16.85% 62.56% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::3 150309706 15.69% 78.25% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::4 108022954 11.28% 89.53% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::5 60994203 6.37% 95.90% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::6 28856033 3.01% 98.91% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::7 9365653 0.98% 99.89% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::8 1095926 0.11% 100.00% # Number of insts issued each cycle
| 106system.cpu.iq.issued_per_cycle::0 246447632 27.33% 27.33% # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::1 157137359 17.42% 44.75% # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::2 150782303 16.72% 61.47% # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::3 147402025 16.35% 77.82% # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::4 103278327 11.45% 89.27% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::5 58944184 6.54% 95.81% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::6 27765839 3.08% 98.88% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::7 9016087 1.00% 99.88% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::8 1042416 0.12% 100.00% # Number of insts issued each cycle
|
117system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 115system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
120system.cpu.iq.issued_per_cycle::total 958022628 # Number of insts issued each cycle
| 118system.cpu.iq.issued_per_cycle::total 901816172 # Number of insts issued each cycle
|
121system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 119system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
122system.cpu.iq.fu_full::IntAlu 2261253 14.71% 14.71% # attempts to use FU when none available
123system.cpu.iq.fu_full::IntMult 0 0.00% 14.71% # attempts to use FU when none available
124system.cpu.iq.fu_full::IntDiv 0 0.00% 14.71% # attempts to use FU when none available
125system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.71% # attempts to use FU when none available
126system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.71% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.71% # attempts to use FU when none available
128system.cpu.iq.fu_full::FloatMult 0 0.00% 14.71% # attempts to use FU when none available
129system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.71% # attempts to use FU when none available
130system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.71% # attempts to use FU when none available
131system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.71% # attempts to use FU when none available
132system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.71% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.71% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.71% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.71% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.71% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdMult 0 0.00% 14.71% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.71% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdShift 0 0.00% 14.71% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.71% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.71% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.71% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.71% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.71% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.71% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.71% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.71% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.71% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.71% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.71% # attempts to use FU when none available
151system.cpu.iq.fu_full::MemRead 10108961 65.75% 80.46% # attempts to use FU when none available
152system.cpu.iq.fu_full::MemWrite 3003496 19.54% 100.00% # attempts to use FU when none available
| 120system.cpu.iq.fu_full::IntAlu 2649753 16.80% 16.80% # attempts to use FU when none available
121system.cpu.iq.fu_full::IntMult 0 0.00% 16.80% # attempts to use FU when none available
122system.cpu.iq.fu_full::IntDiv 0 0.00% 16.80% # attempts to use FU when none available
123system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.80% # attempts to use FU when none available
124system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.80% # attempts to use FU when none available
125system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.80% # attempts to use FU when none available
126system.cpu.iq.fu_full::FloatMult 0 0.00% 16.80% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.80% # attempts to use FU when none available
128system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.80% # attempts to use FU when none available
129system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.80% # attempts to use FU when none available
130system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.80% # attempts to use FU when none available
131system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.80% # attempts to use FU when none available
132system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.80% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.80% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.80% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdMult 0 0.00% 16.80% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.80% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdShift 0 0.00% 16.80% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.80% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.80% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.80% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.80% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.80% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.80% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.80% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.80% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.80% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.80% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.80% # attempts to use FU when none available
149system.cpu.iq.fu_full::MemRead 9923154 62.91% 79.71% # attempts to use FU when none available
150system.cpu.iq.fu_full::MemWrite 3201078 20.29% 100.00% # attempts to use FU when none available
|
153system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
154system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
| 151system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
152system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
155system.cpu.iq.FU_type_0::No_OpClass 2434143 0.13% 0.13% # Type of FU issued
156system.cpu.iq.FU_type_0::IntAlu 1271908482 66.30% 66.42% # Type of FU issued
157system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.42% # Type of FU issued
158system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.42% # Type of FU issued
159system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.42% # Type of FU issued
160system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.42% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.42% # Type of FU issued
162system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.42% # Type of FU issued
163system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.42% # Type of FU issued
164system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.42% # Type of FU issued
165system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.42% # Type of FU issued
166system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.42% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.42% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.42% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.42% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.42% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.42% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.42% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.42% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.42% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.42% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.42% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.42% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.42% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.42% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.42% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.42% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.42% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.42% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.42% # Type of FU issued
185system.cpu.iq.FU_type_0::MemRead 462991606 24.13% 90.56% # Type of FU issued
186system.cpu.iq.FU_type_0::MemWrite 181178380 9.44% 100.00% # Type of FU issued
| 153system.cpu.iq.FU_type_0::No_OpClass 2725633 0.15% 0.15% # Type of FU issued
154system.cpu.iq.FU_type_0::IntAlu 1219452054 66.03% 66.18% # Type of FU issued
155system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued
156system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued
157system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued
158system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
159system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
160system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
162system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
163system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
164system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
165system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
166system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
183system.cpu.iq.FU_type_0::MemRead 447143707 24.21% 90.39% # Type of FU issued
184system.cpu.iq.FU_type_0::MemWrite 177467845 9.61% 100.00% # Type of FU issued
|
187system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
188system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 185system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
186system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
189system.cpu.iq.FU_type_0::total 1918512611 # Type of FU issued
190system.cpu.iq.rate 1.965583 # Inst issue rate
191system.cpu.iq.fu_busy_cnt 15373710 # FU busy when requested
192system.cpu.iq.fu_busy_rate 0.008013 # FU busy rate (busy events/executed inst)
193system.cpu.iq.int_inst_queue_reads 4811718392 # Number of integer instruction queue reads
194system.cpu.iq.int_inst_queue_writes 3018136915 # Number of integer instruction queue writes
195system.cpu.iq.int_inst_queue_wakeup_accesses 1871298739 # Number of integer instruction queue wakeup accesses
196system.cpu.iq.fp_inst_queue_reads 5168 # Number of floating instruction queue reads
197system.cpu.iq.fp_inst_queue_writes 82228 # Number of floating instruction queue writes
198system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses
199system.cpu.iq.int_alu_accesses 1931450456 # Number of integer alu accesses
200system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses
201system.cpu.iew.lsq.thread0.forwLoads 171083363 # Number of loads that had data forwarded from stores
| 187system.cpu.iq.FU_type_0::total 1846789239 # Type of FU issued
188system.cpu.iq.rate 2.006909 # Inst issue rate
189system.cpu.iq.fu_busy_cnt 15773985 # FU busy when requested
190system.cpu.iq.fu_busy_rate 0.008541 # FU busy rate (busy events/executed inst)
191system.cpu.iq.int_inst_queue_reads 4612764501 # Number of integer instruction queue reads
192system.cpu.iq.int_inst_queue_writes 2755319104 # Number of integer instruction queue writes
193system.cpu.iq.int_inst_queue_wakeup_accesses 1806286815 # Number of integer instruction queue wakeup accesses
194system.cpu.iq.fp_inst_queue_reads 7926 # Number of floating instruction queue reads
195system.cpu.iq.fp_inst_queue_writes 295108 # Number of floating instruction queue writes
196system.cpu.iq.fp_inst_queue_wakeup_accesses 254 # Number of floating instruction queue wakeup accesses
197system.cpu.iq.int_alu_accesses 1859834785 # Number of integer alu accesses
198system.cpu.iq.fp_alu_accesses 2806 # Number of floating point alu accesses
199system.cpu.iew.lsq.thread0.forwLoads 168142861 # Number of loads that had data forwarded from stores
|
202system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 200system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
203system.cpu.iew.lsq.thread0.squashedLoads 191119497 # Number of loads squashed
204system.cpu.iew.lsq.thread0.ignoredResponses 436651 # Number of memory responses ignored because the instruction is squashed
205system.cpu.iew.lsq.thread0.memOrderViolation 282394 # Number of memory ordering violations
206system.cpu.iew.lsq.thread0.squashedStores 76247769 # Number of stores squashed
| 201system.cpu.iew.lsq.thread0.squashedLoads 155978687 # Number of loads squashed
202system.cpu.iew.lsq.thread0.ignoredResponses 426493 # Number of memory responses ignored because the instruction is squashed
203system.cpu.iew.lsq.thread0.memOrderViolation 273307 # Number of memory ordering violations
204system.cpu.iew.lsq.thread0.squashedStores 68112538 # Number of stores squashed
|
207system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
208system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
| 205system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
206system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
209system.cpu.iew.lsq.thread0.rescheduledLoads 6215 # Number of loads that were rescheduled
| 207system.cpu.iew.lsq.thread0.rescheduledLoads 6604 # Number of loads that were rescheduled
|
210system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
211system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 208system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
209system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
212system.cpu.iew.iewSquashCycles 101497043 # Number of cycles IEW is squashing
213system.cpu.iew.iewBlockCycles 7669372 # Number of cycles IEW is blocking
214system.cpu.iew.iewUnblockCycles 1230820 # Number of cycles IEW is unblocking
215system.cpu.iew.iewDispatchedInsts 2274745060 # Number of instructions dispatched to IQ
216system.cpu.iew.iewDispSquashedInsts 1222472 # Number of squashed instructions skipped by dispatch
217system.cpu.iew.iewDispLoadInsts 575221657 # Number of dispatched load instructions
218system.cpu.iew.iewDispStoreInsts 225407954 # Number of dispatched store instructions
219system.cpu.iew.iewDispNonSpecInsts 6105 # Number of dispatched non-speculative instructions
220system.cpu.iew.iewIQFullEvents 878634 # Number of times the IQ has become full, causing a stall
221system.cpu.iew.iewLSQFullEvents 17249 # Number of times the LSQ has become full, causing a stall
222system.cpu.iew.memOrderViolationEvents 282394 # Number of memory order violations
223system.cpu.iew.predictedTakenIncorrect 15676996 # Number of branches that were predicted taken incorrectly
224system.cpu.iew.predictedNotTakenIncorrect 2334571 # Number of branches that were predicted not taken incorrectly
225system.cpu.iew.branchMispredicts 18011567 # Number of branch mispredicts detected at execute
226system.cpu.iew.iewExecutedInsts 1885150488 # Number of executed instructions
227system.cpu.iew.iewExecLoadInsts 454035777 # Number of load instructions executed
228system.cpu.iew.iewExecSquashedInsts 33362123 # Number of squashed instructions skipped in execute
| 210system.cpu.iew.iewSquashCycles 83923326 # Number of cycles IEW is squashing
211system.cpu.iew.iewBlockCycles 7067341 # Number of cycles IEW is blocking
212system.cpu.iew.iewUnblockCycles 1165909 # Number of cycles IEW is unblocking
213system.cpu.iew.iewDispatchedInsts 2143044940 # Number of instructions dispatched to IQ
214system.cpu.iew.iewDispSquashedInsts 2779083 # Number of squashed instructions skipped by dispatch
215system.cpu.iew.iewDispLoadInsts 540080847 # Number of dispatched load instructions
216system.cpu.iew.iewDispStoreInsts 217272723 # Number of dispatched store instructions
217system.cpu.iew.iewDispNonSpecInsts 5880 # Number of dispatched non-speculative instructions
218system.cpu.iew.iewIQFullEvents 921481 # Number of times the IQ has become full, causing a stall
219system.cpu.iew.iewLSQFullEvents 15876 # Number of times the LSQ has become full, causing a stall
220system.cpu.iew.memOrderViolationEvents 273307 # Number of memory order violations
221system.cpu.iew.predictedTakenIncorrect 10083404 # Number of branches that were predicted taken incorrectly
222system.cpu.iew.predictedNotTakenIncorrect 5246002 # Number of branches that were predicted not taken incorrectly
223system.cpu.iew.branchMispredicts 15329406 # Number of branch mispredicts detected at execute
224system.cpu.iew.iewExecutedInsts 1818781271 # Number of executed instructions
225system.cpu.iew.iewExecLoadInsts 438673892 # Number of load instructions executed
226system.cpu.iew.iewExecSquashedInsts 28007968 # Number of squashed instructions skipped in execute
|
229system.cpu.iew.exec_swp 0 # number of swp insts executed
230system.cpu.iew.exec_nop 0 # number of nop insts executed
| 227system.cpu.iew.exec_swp 0 # number of swp insts executed
228system.cpu.iew.exec_nop 0 # number of nop insts executed
|
231system.cpu.iew.exec_refs 627868559 # number of memory reference insts executed
232system.cpu.iew.exec_branches 176458351 # Number of branches executed
233system.cpu.iew.exec_stores 173832782 # Number of stores executed
234system.cpu.iew.exec_rate 1.931402 # Inst execution rate
235system.cpu.iew.wb_sent 1879040223 # cumulative count of insts sent to commit
236system.cpu.iew.wb_count 1871298858 # cumulative count of insts written-back
237system.cpu.iew.wb_producers 1436941600 # num instructions producing a value
238system.cpu.iew.wb_consumers 2126368380 # num instructions consuming a value
| 229system.cpu.iew.exec_refs 610552632 # number of memory reference insts executed
230system.cpu.iew.exec_branches 170822936 # Number of branches executed
231system.cpu.iew.exec_stores 171878740 # Number of stores executed
232system.cpu.iew.exec_rate 1.976472 # Inst execution rate
233system.cpu.iew.wb_sent 1813583044 # cumulative count of insts sent to commit
234system.cpu.iew.wb_count 1806287069 # cumulative count of insts written-back
235system.cpu.iew.wb_producers 1379599827 # num instructions producing a value
236system.cpu.iew.wb_consumers 2050187147 # num instructions consuming a value
|
239system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 237system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
240system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle
241system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back
| 238system.cpu.iew.wb_rate 1.962895 # insts written-back per cycle
239system.cpu.iew.wb_fanout 0.672914 # average fanout of values written-back
|
242system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
243system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
244system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
| 240system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
241system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
242system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
|
245system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit
| 243system.cpu.commit.commitSquashedInsts 614080092 # The number of squashed insts skipped by commit
|
246system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
| 244system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
247system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted
248system.cpu.commit.committed_per_cycle::samples 856525585 # Number of insts commited each cycle
249system.cpu.commit.committed_per_cycle::mean 1.785106 # Number of insts commited each cycle
250system.cpu.commit.committed_per_cycle::stdev 2.285139 # Number of insts commited each cycle
| 245system.cpu.commit.branchMispredicts 14315856 # The number of times a branch was mispredicted
246system.cpu.commit.committed_per_cycle::samples 817892846 # Number of insts commited each cycle
247system.cpu.commit.committed_per_cycle::mean 1.869424 # Number of insts commited each cycle
248system.cpu.commit.committed_per_cycle::stdev 2.327438 # Number of insts commited each cycle
|
251system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 249system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
252system.cpu.commit.committed_per_cycle::0 331592690 38.71% 38.71% # Number of insts commited each cycle
253system.cpu.commit.committed_per_cycle::1 211839945 24.73% 63.45% # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::2 76804588 8.97% 72.41% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::3 92775414 10.83% 83.24% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::4 33678704 3.93% 87.18% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::5 28505123 3.33% 90.50% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::6 15688691 1.83% 92.34% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::7 11282624 1.32% 93.65% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::8 54357806 6.35% 100.00% # Number of insts commited each cycle
| 250system.cpu.commit.committed_per_cycle::0 301647537 36.88% 36.88% # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::1 204220955 24.97% 61.85% # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::2 73668560 9.01% 70.86% # Number of insts commited each cycle
253system.cpu.commit.committed_per_cycle::3 95020529 11.62% 82.48% # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::4 30882746 3.78% 86.25% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::5 28791442 3.52% 89.77% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::6 16321974 2.00% 91.77% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::7 11763768 1.44% 93.21% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::8 55575335 6.79% 100.00% # Number of insts commited each cycle
|
261system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 259system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
264system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle
| 262system.cpu.commit.committed_per_cycle::total 817892846 # Number of insts commited each cycle
|
265system.cpu.commit.committedInsts 826877144 # Number of instructions committed
266system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
267system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
268system.cpu.commit.refs 533262345 # Number of memory references committed
269system.cpu.commit.loads 384102160 # Number of loads committed
270system.cpu.commit.membars 0 # Number of memory barriers committed
271system.cpu.commit.branches 149758588 # Number of branches committed
272system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
273system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
274system.cpu.commit.function_calls 0 # Number of function calls committed.
| 263system.cpu.commit.committedInsts 826877144 # Number of instructions committed
264system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
265system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
266system.cpu.commit.refs 533262345 # Number of memory references committed
267system.cpu.commit.loads 384102160 # Number of loads committed
268system.cpu.commit.membars 0 # Number of memory barriers committed
269system.cpu.commit.branches 149758588 # Number of branches committed
270system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
271system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
272system.cpu.commit.function_calls 0 # Number of function calls committed.
|
275system.cpu.commit.bw_lim_events 54357806 # number cycles where commit BW limit reached
| 273system.cpu.commit.bw_lim_events 55575335 # number cycles where commit BW limit reached
|
276system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 274system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
277system.cpu.rob.rob_reads 3076935822 # The number of ROB reads
278system.cpu.rob.rob_writes 4651204201 # The number of ROB writes
279system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself
280system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling
| 275system.cpu.rob.rob_reads 2905386359 # The number of ROB reads
276system.cpu.rob.rob_writes 4370176424 # The number of ROB writes
277system.cpu.timesIdled 410524 # Number of times that the entire CPU went into an idle state and unscheduled itself
278system.cpu.idleCycles 18399678 # Total number of cycles that the CPU has spent unscheduled due to idling
|
281system.cpu.committedInsts 826877144 # Number of Instructions Simulated
282system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
283system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
| 279system.cpu.committedInsts 826877144 # Number of Instructions Simulated
280system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
281system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
|
284system.cpu.cpi 1.180408 # CPI: Cycles Per Instruction
285system.cpu.cpi_total 1.180408 # CPI: Total CPI of All Threads
286system.cpu.ipc 0.847164 # IPC: Instructions Per Cycle
287system.cpu.ipc_total 0.847164 # IPC: Total IPC of All Threads
288system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads
289system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes
290system.cpu.fp_regfile_reads 120 # number of floating regfile reads
291system.cpu.misc_regfile_reads 1036377940 # number of misc regfile reads
292system.cpu.icache.replacements 10111 # number of replacements
293system.cpu.icache.tagsinuse 973.820201 # Cycle average of tags in use
294system.cpu.icache.total_refs 193659156 # Total number of references to valid blocks.
295system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks.
296system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks.
| 282system.cpu.cpi 1.112881 # CPI: Cycles Per Instruction
283system.cpu.cpi_total 1.112881 # CPI: Total CPI of All Threads
284system.cpu.ipc 0.898569 # IPC: Instructions Per Cycle
285system.cpu.ipc_total 0.898569 # IPC: Total IPC of All Threads
286system.cpu.int_regfile_reads 3086863683 # number of integer regfile reads
287system.cpu.int_regfile_writes 1679046201 # number of integer regfile writes
288system.cpu.fp_regfile_reads 253 # number of floating regfile reads
289system.cpu.fp_regfile_writes 1 # number of floating regfile writes
290system.cpu.misc_regfile_reads 1001956200 # number of misc regfile reads
291system.cpu.icache.replacements 10582 # number of replacements
292system.cpu.icache.tagsinuse 994.041407 # Cycle average of tags in use
293system.cpu.icache.total_refs 183174422 # Total number of references to valid blocks.
294system.cpu.icache.sampled_refs 12099 # Sample count of references to valid blocks.
295system.cpu.icache.avg_refs 15139.633193 # Average number of references to valid blocks.
|
297system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 296system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
298system.cpu.icache.occ_blocks::cpu.inst 973.820201 # Average occupied blocks per requestor
299system.cpu.icache.occ_percent::cpu.inst 0.475498 # Average percentage of cache occupancy
300system.cpu.icache.occ_percent::total 0.475498 # Average percentage of cache occupancy
301system.cpu.icache.ReadReq_hits::cpu.inst 193665655 # number of ReadReq hits
302system.cpu.icache.ReadReq_hits::total 193665655 # number of ReadReq hits
303system.cpu.icache.demand_hits::cpu.inst 193665655 # number of demand (read+write) hits
304system.cpu.icache.demand_hits::total 193665655 # number of demand (read+write) hits
305system.cpu.icache.overall_hits::cpu.inst 193665655 # number of overall hits
306system.cpu.icache.overall_hits::total 193665655 # number of overall hits
307system.cpu.icache.ReadReq_misses::cpu.inst 234749 # number of ReadReq misses
308system.cpu.icache.ReadReq_misses::total 234749 # number of ReadReq misses
309system.cpu.icache.demand_misses::cpu.inst 234749 # number of demand (read+write) misses
310system.cpu.icache.demand_misses::total 234749 # number of demand (read+write) misses
311system.cpu.icache.overall_misses::cpu.inst 234749 # number of overall misses
312system.cpu.icache.overall_misses::total 234749 # number of overall misses
313system.cpu.icache.ReadReq_miss_latency::cpu.inst 1699920500 # number of ReadReq miss cycles
314system.cpu.icache.ReadReq_miss_latency::total 1699920500 # number of ReadReq miss cycles
315system.cpu.icache.demand_miss_latency::cpu.inst 1699920500 # number of demand (read+write) miss cycles
316system.cpu.icache.demand_miss_latency::total 1699920500 # number of demand (read+write) miss cycles
317system.cpu.icache.overall_miss_latency::cpu.inst 1699920500 # number of overall miss cycles
318system.cpu.icache.overall_miss_latency::total 1699920500 # number of overall miss cycles
319system.cpu.icache.ReadReq_accesses::cpu.inst 193900404 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.ReadReq_accesses::total 193900404 # number of ReadReq accesses(hits+misses)
321system.cpu.icache.demand_accesses::cpu.inst 193900404 # number of demand (read+write) accesses
322system.cpu.icache.demand_accesses::total 193900404 # number of demand (read+write) accesses
323system.cpu.icache.overall_accesses::cpu.inst 193900404 # number of overall (read+write) accesses
324system.cpu.icache.overall_accesses::total 193900404 # number of overall (read+write) accesses
325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001211 # miss rate for ReadReq accesses
326system.cpu.icache.demand_miss_rate::cpu.inst 0.001211 # miss rate for demand accesses
327system.cpu.icache.overall_miss_rate::cpu.inst 0.001211 # miss rate for overall accesses
328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7241.438728 # average ReadReq miss latency
329system.cpu.icache.demand_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency
330system.cpu.icache.overall_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency
| 297system.cpu.icache.occ_blocks::cpu.inst 994.041407 # Average occupied blocks per requestor
298system.cpu.icache.occ_percent::cpu.inst 0.485372 # Average percentage of cache occupancy
299system.cpu.icache.occ_percent::total 0.485372 # Average percentage of cache occupancy
300system.cpu.icache.ReadReq_hits::cpu.inst 183181303 # number of ReadReq hits
301system.cpu.icache.ReadReq_hits::total 183181303 # number of ReadReq hits
302system.cpu.icache.demand_hits::cpu.inst 183181303 # number of demand (read+write) hits
303system.cpu.icache.demand_hits::total 183181303 # number of demand (read+write) hits
304system.cpu.icache.overall_hits::cpu.inst 183181303 # number of overall hits
305system.cpu.icache.overall_hits::total 183181303 # number of overall hits
306system.cpu.icache.ReadReq_misses::cpu.inst 224498 # number of ReadReq misses
307system.cpu.icache.ReadReq_misses::total 224498 # number of ReadReq misses
308system.cpu.icache.demand_misses::cpu.inst 224498 # number of demand (read+write) misses
309system.cpu.icache.demand_misses::total 224498 # number of demand (read+write) misses
310system.cpu.icache.overall_misses::cpu.inst 224498 # number of overall misses
311system.cpu.icache.overall_misses::total 224498 # number of overall misses
312system.cpu.icache.ReadReq_miss_latency::cpu.inst 1640944500 # number of ReadReq miss cycles
313system.cpu.icache.ReadReq_miss_latency::total 1640944500 # number of ReadReq miss cycles
314system.cpu.icache.demand_miss_latency::cpu.inst 1640944500 # number of demand (read+write) miss cycles
315system.cpu.icache.demand_miss_latency::total 1640944500 # number of demand (read+write) miss cycles
316system.cpu.icache.overall_miss_latency::cpu.inst 1640944500 # number of overall miss cycles
317system.cpu.icache.overall_miss_latency::total 1640944500 # number of overall miss cycles
318system.cpu.icache.ReadReq_accesses::cpu.inst 183405801 # number of ReadReq accesses(hits+misses)
319system.cpu.icache.ReadReq_accesses::total 183405801 # number of ReadReq accesses(hits+misses)
320system.cpu.icache.demand_accesses::cpu.inst 183405801 # number of demand (read+write) accesses
321system.cpu.icache.demand_accesses::total 183405801 # number of demand (read+write) accesses
322system.cpu.icache.overall_accesses::cpu.inst 183405801 # number of overall (read+write) accesses
323system.cpu.icache.overall_accesses::total 183405801 # number of overall (read+write) accesses
324system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001224 # miss rate for ReadReq accesses
325system.cpu.icache.demand_miss_rate::cpu.inst 0.001224 # miss rate for demand accesses
326system.cpu.icache.overall_miss_rate::cpu.inst 0.001224 # miss rate for overall accesses
327system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7309.394738 # average ReadReq miss latency
328system.cpu.icache.demand_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency
329system.cpu.icache.overall_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency
|
331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
335system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
336system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
337system.cpu.icache.fast_writes 0 # number of fast writes performed
338system.cpu.icache.cache_copies 0 # number of cache copies performed
| 330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
334system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
335system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
336system.cpu.icache.fast_writes 0 # number of fast writes performed
337system.cpu.icache.cache_copies 0 # number of cache copies performed
|
339system.cpu.icache.writebacks::writebacks 4 # number of writebacks
340system.cpu.icache.writebacks::total 4 # number of writebacks
341system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2040 # number of ReadReq MSHR hits
342system.cpu.icache.ReadReq_mshr_hits::total 2040 # number of ReadReq MSHR hits
343system.cpu.icache.demand_mshr_hits::cpu.inst 2040 # number of demand (read+write) MSHR hits
344system.cpu.icache.demand_mshr_hits::total 2040 # number of demand (read+write) MSHR hits
345system.cpu.icache.overall_mshr_hits::cpu.inst 2040 # number of overall MSHR hits
346system.cpu.icache.overall_mshr_hits::total 2040 # number of overall MSHR hits
347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 232709 # number of ReadReq MSHR misses
348system.cpu.icache.ReadReq_mshr_misses::total 232709 # number of ReadReq MSHR misses
349system.cpu.icache.demand_mshr_misses::cpu.inst 232709 # number of demand (read+write) MSHR misses
350system.cpu.icache.demand_mshr_misses::total 232709 # number of demand (read+write) MSHR misses
351system.cpu.icache.overall_mshr_misses::cpu.inst 232709 # number of overall MSHR misses
352system.cpu.icache.overall_mshr_misses::total 232709 # number of overall MSHR misses
353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 952455000 # number of ReadReq MSHR miss cycles
354system.cpu.icache.ReadReq_mshr_miss_latency::total 952455000 # number of ReadReq MSHR miss cycles
355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 952455000 # number of demand (read+write) MSHR miss cycles
356system.cpu.icache.demand_mshr_miss_latency::total 952455000 # number of demand (read+write) MSHR miss cycles
357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 952455000 # number of overall MSHR miss cycles
358system.cpu.icache.overall_mshr_miss_latency::total 952455000 # number of overall MSHR miss cycles
359system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for ReadReq accesses
360system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for demand accesses
361system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for overall accesses
362system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4092.901435 # average ReadReq mshr miss latency
363system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency
364system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency
| 338system.cpu.icache.writebacks::writebacks 8 # number of writebacks
339system.cpu.icache.writebacks::total 8 # number of writebacks
340system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2528 # number of ReadReq MSHR hits
341system.cpu.icache.ReadReq_mshr_hits::total 2528 # number of ReadReq MSHR hits
342system.cpu.icache.demand_mshr_hits::cpu.inst 2528 # number of demand (read+write) MSHR hits
343system.cpu.icache.demand_mshr_hits::total 2528 # number of demand (read+write) MSHR hits
344system.cpu.icache.overall_mshr_hits::cpu.inst 2528 # number of overall MSHR hits
345system.cpu.icache.overall_mshr_hits::total 2528 # number of overall MSHR hits
346system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221970 # number of ReadReq MSHR misses
347system.cpu.icache.ReadReq_mshr_misses::total 221970 # number of ReadReq MSHR misses
348system.cpu.icache.demand_mshr_misses::cpu.inst 221970 # number of demand (read+write) MSHR misses
349system.cpu.icache.demand_mshr_misses::total 221970 # number of demand (read+write) MSHR misses
350system.cpu.icache.overall_mshr_misses::cpu.inst 221970 # number of overall MSHR misses
351system.cpu.icache.overall_mshr_misses::total 221970 # number of overall MSHR misses
352system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915300500 # number of ReadReq MSHR miss cycles
353system.cpu.icache.ReadReq_mshr_miss_latency::total 915300500 # number of ReadReq MSHR miss cycles
354system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915300500 # number of demand (read+write) MSHR miss cycles
355system.cpu.icache.demand_mshr_miss_latency::total 915300500 # number of demand (read+write) MSHR miss cycles
356system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915300500 # number of overall MSHR miss cycles
357system.cpu.icache.overall_mshr_miss_latency::total 915300500 # number of overall MSHR miss cycles
358system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001210 # mshr miss rate for ReadReq accesses
359system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001210 # mshr miss rate for demand accesses
360system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001210 # mshr miss rate for overall accesses
361system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4123.532459 # average ReadReq mshr miss latency
362system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4123.532459 # average overall mshr miss latency
363system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4123.532459 # average overall mshr miss latency
|
365system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 364system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
366system.cpu.dcache.replacements 2529316 # number of replacements
367system.cpu.dcache.tagsinuse 4087.520068 # Cycle average of tags in use
368system.cpu.dcache.total_refs 427611101 # Total number of references to valid blocks.
369system.cpu.dcache.sampled_refs 2533412 # Sample count of references to valid blocks.
370system.cpu.dcache.avg_refs 168.788614 # Average number of references to valid blocks.
371system.cpu.dcache.warmup_cycle 2115074000 # Cycle when the warmup percentage was hit.
372system.cpu.dcache.occ_blocks::cpu.data 4087.520068 # Average occupied blocks per requestor
373system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy
374system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy
375system.cpu.dcache.ReadReq_hits::cpu.data 278887188 # number of ReadReq hits
376system.cpu.dcache.ReadReq_hits::total 278887188 # number of ReadReq hits
377system.cpu.dcache.WriteReq_hits::cpu.data 148162157 # number of WriteReq hits
378system.cpu.dcache.WriteReq_hits::total 148162157 # number of WriteReq hits
379system.cpu.dcache.demand_hits::cpu.data 427049345 # number of demand (read+write) hits
380system.cpu.dcache.demand_hits::total 427049345 # number of demand (read+write) hits
381system.cpu.dcache.overall_hits::cpu.data 427049345 # number of overall hits
382system.cpu.dcache.overall_hits::total 427049345 # number of overall hits
383system.cpu.dcache.ReadReq_misses::cpu.data 2665882 # number of ReadReq misses
384system.cpu.dcache.ReadReq_misses::total 2665882 # number of ReadReq misses
385system.cpu.dcache.WriteReq_misses::cpu.data 998044 # number of WriteReq misses
386system.cpu.dcache.WriteReq_misses::total 998044 # number of WriteReq misses
387system.cpu.dcache.demand_misses::cpu.data 3663926 # number of demand (read+write) misses
388system.cpu.dcache.demand_misses::total 3663926 # number of demand (read+write) misses
389system.cpu.dcache.overall_misses::cpu.data 3663926 # number of overall misses
390system.cpu.dcache.overall_misses::total 3663926 # number of overall misses
391system.cpu.dcache.ReadReq_miss_latency::cpu.data 39487902000 # number of ReadReq miss cycles
392system.cpu.dcache.ReadReq_miss_latency::total 39487902000 # number of ReadReq miss cycles
393system.cpu.dcache.WriteReq_miss_latency::cpu.data 20586128000 # number of WriteReq miss cycles
394system.cpu.dcache.WriteReq_miss_latency::total 20586128000 # number of WriteReq miss cycles
395system.cpu.dcache.demand_miss_latency::cpu.data 60074030000 # number of demand (read+write) miss cycles
396system.cpu.dcache.demand_miss_latency::total 60074030000 # number of demand (read+write) miss cycles
397system.cpu.dcache.overall_miss_latency::cpu.data 60074030000 # number of overall miss cycles
398system.cpu.dcache.overall_miss_latency::total 60074030000 # number of overall miss cycles
399system.cpu.dcache.ReadReq_accesses::cpu.data 281553070 # number of ReadReq accesses(hits+misses)
400system.cpu.dcache.ReadReq_accesses::total 281553070 # number of ReadReq accesses(hits+misses)
| 365system.cpu.dcache.replacements 2526943 # number of replacements
366system.cpu.dcache.tagsinuse 4087.013788 # Cycle average of tags in use
367system.cpu.dcache.total_refs 415067708 # Total number of references to valid blocks.
368system.cpu.dcache.sampled_refs 2531039 # Sample count of references to valid blocks.
369system.cpu.dcache.avg_refs 163.991036 # Average number of references to valid blocks.
370system.cpu.dcache.warmup_cycle 2117980000 # Cycle when the warmup percentage was hit.
371system.cpu.dcache.occ_blocks::cpu.data 4087.013788 # Average occupied blocks per requestor
372system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy
373system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy
374system.cpu.dcache.ReadReq_hits::cpu.data 266225231 # number of ReadReq hits
375system.cpu.dcache.ReadReq_hits::total 266225231 # number of ReadReq hits
376system.cpu.dcache.WriteReq_hits::cpu.data 148171071 # number of WriteReq hits
377system.cpu.dcache.WriteReq_hits::total 148171071 # number of WriteReq hits
378system.cpu.dcache.demand_hits::cpu.data 414396302 # number of demand (read+write) hits
379system.cpu.dcache.demand_hits::total 414396302 # number of demand (read+write) hits
380system.cpu.dcache.overall_hits::cpu.data 414396302 # number of overall hits
381system.cpu.dcache.overall_hits::total 414396302 # number of overall hits
382system.cpu.dcache.ReadReq_misses::cpu.data 2666540 # number of ReadReq misses
383system.cpu.dcache.ReadReq_misses::total 2666540 # number of ReadReq misses
384system.cpu.dcache.WriteReq_misses::cpu.data 989130 # number of WriteReq misses
385system.cpu.dcache.WriteReq_misses::total 989130 # number of WriteReq misses
386system.cpu.dcache.demand_misses::cpu.data 3655670 # number of demand (read+write) misses
387system.cpu.dcache.demand_misses::total 3655670 # number of demand (read+write) misses
388system.cpu.dcache.overall_misses::cpu.data 3655670 # number of overall misses
389system.cpu.dcache.overall_misses::total 3655670 # number of overall misses
390system.cpu.dcache.ReadReq_miss_latency::cpu.data 38988147500 # number of ReadReq miss cycles
391system.cpu.dcache.ReadReq_miss_latency::total 38988147500 # number of ReadReq miss cycles
392system.cpu.dcache.WriteReq_miss_latency::cpu.data 20140670500 # number of WriteReq miss cycles
393system.cpu.dcache.WriteReq_miss_latency::total 20140670500 # number of WriteReq miss cycles
394system.cpu.dcache.demand_miss_latency::cpu.data 59128818000 # number of demand (read+write) miss cycles
395system.cpu.dcache.demand_miss_latency::total 59128818000 # number of demand (read+write) miss cycles
396system.cpu.dcache.overall_miss_latency::cpu.data 59128818000 # number of overall miss cycles
397system.cpu.dcache.overall_miss_latency::total 59128818000 # number of overall miss cycles
398system.cpu.dcache.ReadReq_accesses::cpu.data 268891771 # number of ReadReq accesses(hits+misses)
399system.cpu.dcache.ReadReq_accesses::total 268891771 # number of ReadReq accesses(hits+misses)
|
401system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
402system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
| 400system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
401system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
403system.cpu.dcache.demand_accesses::cpu.data 430713271 # number of demand (read+write) accesses
404system.cpu.dcache.demand_accesses::total 430713271 # number of demand (read+write) accesses
405system.cpu.dcache.overall_accesses::cpu.data 430713271 # number of overall (read+write) accesses
406system.cpu.dcache.overall_accesses::total 430713271 # number of overall (read+write) accesses
407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009468 # miss rate for ReadReq accesses
408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006691 # miss rate for WriteReq accesses
409system.cpu.dcache.demand_miss_rate::cpu.data 0.008507 # miss rate for demand accesses
410system.cpu.dcache.overall_miss_rate::cpu.data 0.008507 # miss rate for overall accesses
411system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14812.321776 # average ReadReq miss latency
412system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20626.473382 # average WriteReq miss latency
413system.cpu.dcache.demand_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency
414system.cpu.dcache.overall_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency
| 402system.cpu.dcache.demand_accesses::cpu.data 418051972 # number of demand (read+write) accesses
403system.cpu.dcache.demand_accesses::total 418051972 # number of demand (read+write) accesses
404system.cpu.dcache.overall_accesses::cpu.data 418051972 # number of overall (read+write) accesses
405system.cpu.dcache.overall_accesses::total 418051972 # number of overall (read+write) accesses
406system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009917 # miss rate for ReadReq accesses
407system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006631 # miss rate for WriteReq accesses
408system.cpu.dcache.demand_miss_rate::cpu.data 0.008745 # miss rate for demand accesses
409system.cpu.dcache.overall_miss_rate::cpu.data 0.008745 # miss rate for overall accesses
410system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822 # average ReadReq miss latency
411system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500 # average WriteReq miss latency
412system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency
413system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency
|
415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
420system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
421system.cpu.dcache.fast_writes 0 # number of fast writes performed
422system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
418system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
419system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
420system.cpu.dcache.fast_writes 0 # number of fast writes performed
421system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
423system.cpu.dcache.writebacks::writebacks 2229932 # number of writebacks
424system.cpu.dcache.writebacks::total 2229932 # number of writebacks
425system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902993 # number of ReadReq MSHR hits
426system.cpu.dcache.ReadReq_mshr_hits::total 902993 # number of ReadReq MSHR hits
427system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6453 # number of WriteReq MSHR hits
428system.cpu.dcache.WriteReq_mshr_hits::total 6453 # number of WriteReq MSHR hits
429system.cpu.dcache.demand_mshr_hits::cpu.data 909446 # number of demand (read+write) MSHR hits
430system.cpu.dcache.demand_mshr_hits::total 909446 # number of demand (read+write) MSHR hits
431system.cpu.dcache.overall_mshr_hits::cpu.data 909446 # number of overall MSHR hits
432system.cpu.dcache.overall_mshr_hits::total 909446 # number of overall MSHR hits
433system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762889 # number of ReadReq MSHR misses
434system.cpu.dcache.ReadReq_mshr_misses::total 1762889 # number of ReadReq MSHR misses
435system.cpu.dcache.WriteReq_mshr_misses::cpu.data 991591 # number of WriteReq MSHR misses
436system.cpu.dcache.WriteReq_mshr_misses::total 991591 # number of WriteReq MSHR misses
437system.cpu.dcache.demand_mshr_misses::cpu.data 2754480 # number of demand (read+write) MSHR misses
438system.cpu.dcache.demand_mshr_misses::total 2754480 # number of demand (read+write) MSHR misses
439system.cpu.dcache.overall_mshr_misses::cpu.data 2754480 # number of overall MSHR misses
440system.cpu.dcache.overall_mshr_misses::total 2754480 # number of overall MSHR misses
441system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14966916500 # number of ReadReq MSHR miss cycles
442system.cpu.dcache.ReadReq_mshr_miss_latency::total 14966916500 # number of ReadReq MSHR miss cycles
443system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17535799000 # number of WriteReq MSHR miss cycles
444system.cpu.dcache.WriteReq_mshr_miss_latency::total 17535799000 # number of WriteReq MSHR miss cycles
445system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32502715500 # number of demand (read+write) MSHR miss cycles
446system.cpu.dcache.demand_mshr_miss_latency::total 32502715500 # number of demand (read+write) MSHR miss cycles
447system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32502715500 # number of overall MSHR miss cycles
448system.cpu.dcache.overall_mshr_miss_latency::total 32502715500 # number of overall MSHR miss cycles
449system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006261 # mshr miss rate for ReadReq accesses
450system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006648 # mshr miss rate for WriteReq accesses
451system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for demand accesses
452system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for overall accesses
453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8489.993698 # average ReadReq mshr miss latency
454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17684.508028 # average WriteReq mshr miss latency
455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency
456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency
| 422system.cpu.dcache.writebacks::writebacks 2228961 # number of writebacks
423system.cpu.dcache.writebacks::total 2228961 # number of writebacks
424system.cpu.dcache.ReadReq_mshr_hits::cpu.data 905583 # number of ReadReq MSHR hits
425system.cpu.dcache.ReadReq_mshr_hits::total 905583 # number of ReadReq MSHR hits
426system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9205 # number of WriteReq MSHR hits
427system.cpu.dcache.WriteReq_mshr_hits::total 9205 # number of WriteReq MSHR hits
428system.cpu.dcache.demand_mshr_hits::cpu.data 914788 # number of demand (read+write) MSHR hits
429system.cpu.dcache.demand_mshr_hits::total 914788 # number of demand (read+write) MSHR hits
430system.cpu.dcache.overall_mshr_hits::cpu.data 914788 # number of overall MSHR hits
431system.cpu.dcache.overall_mshr_hits::total 914788 # number of overall MSHR hits
432system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760957 # number of ReadReq MSHR misses
433system.cpu.dcache.ReadReq_mshr_misses::total 1760957 # number of ReadReq MSHR misses
434system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979925 # number of WriteReq MSHR misses
435system.cpu.dcache.WriteReq_mshr_misses::total 979925 # number of WriteReq MSHR misses
436system.cpu.dcache.demand_mshr_misses::cpu.data 2740882 # number of demand (read+write) MSHR misses
437system.cpu.dcache.demand_mshr_misses::total 2740882 # number of demand (read+write) MSHR misses
438system.cpu.dcache.overall_mshr_misses::cpu.data 2740882 # number of overall MSHR misses
439system.cpu.dcache.overall_mshr_misses::total 2740882 # number of overall MSHR misses
440system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14913752500 # number of ReadReq MSHR miss cycles
441system.cpu.dcache.ReadReq_mshr_miss_latency::total 14913752500 # number of ReadReq MSHR miss cycles
442system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17128067500 # number of WriteReq MSHR miss cycles
443system.cpu.dcache.WriteReq_mshr_miss_latency::total 17128067500 # number of WriteReq MSHR miss cycles
444system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32041820000 # number of demand (read+write) MSHR miss cycles
445system.cpu.dcache.demand_mshr_miss_latency::total 32041820000 # number of demand (read+write) MSHR miss cycles
446system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32041820000 # number of overall MSHR miss cycles
447system.cpu.dcache.overall_mshr_miss_latency::total 32041820000 # number of overall MSHR miss cycles
448system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006549 # mshr miss rate for ReadReq accesses
449system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006570 # mshr miss rate for WriteReq accesses
450system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8469.117928 # average ReadReq mshr miss latency
453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.957573 # average WriteReq mshr miss latency
454system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11690.331798 # average overall mshr miss latency
455system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11690.331798 # average overall mshr miss latency
|
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 456system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
458system.cpu.l2cache.replacements 575774 # number of replacements
459system.cpu.l2cache.tagsinuse 21621.732877 # Cycle average of tags in use
460system.cpu.l2cache.total_refs 3195554 # Total number of references to valid blocks.
461system.cpu.l2cache.sampled_refs 594946 # Sample count of references to valid blocks.
462system.cpu.l2cache.avg_refs 5.371166 # Average number of references to valid blocks.
463system.cpu.l2cache.warmup_cycle 268816776000 # Cycle when the warmup percentage was hit.
464system.cpu.l2cache.occ_blocks::writebacks 13783.482177 # Average occupied blocks per requestor
465system.cpu.l2cache.occ_blocks::cpu.inst 57.596580 # Average occupied blocks per requestor
466system.cpu.l2cache.occ_blocks::cpu.data 7780.654120 # Average occupied blocks per requestor
467system.cpu.l2cache.occ_percent::writebacks 0.420638 # Average percentage of cache occupancy
468system.cpu.l2cache.occ_percent::cpu.inst 0.001758 # Average percentage of cache occupancy
469system.cpu.l2cache.occ_percent::cpu.data 0.237447 # Average percentage of cache occupancy
470system.cpu.l2cache.occ_percent::total 0.659843 # Average percentage of cache occupancy
471system.cpu.l2cache.ReadReq_hits::cpu.inst 6132 # number of ReadReq hits
472system.cpu.l2cache.ReadReq_hits::cpu.data 1428148 # number of ReadReq hits
473system.cpu.l2cache.ReadReq_hits::total 1434280 # number of ReadReq hits
474system.cpu.l2cache.Writeback_hits::writebacks 2229936 # number of Writeback hits
475system.cpu.l2cache.Writeback_hits::total 2229936 # number of Writeback hits
476system.cpu.l2cache.UpgradeReq_hits::cpu.data 1289 # number of UpgradeReq hits
477system.cpu.l2cache.UpgradeReq_hits::total 1289 # number of UpgradeReq hits
478system.cpu.l2cache.ReadExReq_hits::cpu.data 524029 # number of ReadExReq hits
479system.cpu.l2cache.ReadExReq_hits::total 524029 # number of ReadExReq hits
480system.cpu.l2cache.demand_hits::cpu.inst 6132 # number of demand (read+write) hits
481system.cpu.l2cache.demand_hits::cpu.data 1952177 # number of demand (read+write) hits
482system.cpu.l2cache.demand_hits::total 1958309 # number of demand (read+write) hits
483system.cpu.l2cache.overall_hits::cpu.inst 6132 # number of overall hits
484system.cpu.l2cache.overall_hits::cpu.data 1952177 # number of overall hits
485system.cpu.l2cache.overall_hits::total 1958309 # number of overall hits
486system.cpu.l2cache.ReadReq_misses::cpu.inst 5424 # number of ReadReq misses
487system.cpu.l2cache.ReadReq_misses::cpu.data 334032 # number of ReadReq misses
488system.cpu.l2cache.ReadReq_misses::total 339456 # number of ReadReq misses
489system.cpu.l2cache.UpgradeReq_misses::cpu.data 219771 # number of UpgradeReq misses
490system.cpu.l2cache.UpgradeReq_misses::total 219771 # number of UpgradeReq misses
491system.cpu.l2cache.ReadExReq_misses::cpu.data 247125 # number of ReadExReq misses
492system.cpu.l2cache.ReadExReq_misses::total 247125 # number of ReadExReq misses
493system.cpu.l2cache.demand_misses::cpu.inst 5424 # number of demand (read+write) misses
494system.cpu.l2cache.demand_misses::cpu.data 581157 # number of demand (read+write) misses
495system.cpu.l2cache.demand_misses::total 586581 # number of demand (read+write) misses
496system.cpu.l2cache.overall_misses::cpu.inst 5424 # number of overall misses
497system.cpu.l2cache.overall_misses::cpu.data 581157 # number of overall misses
498system.cpu.l2cache.overall_misses::total 586581 # number of overall misses
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500system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11408936500 # number of ReadReq miss cycles
501system.cpu.l2cache.ReadReq_miss_latency::total 11594725000 # number of ReadReq miss cycles
502system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9650000 # number of UpgradeReq miss cycles
503system.cpu.l2cache.UpgradeReq_miss_latency::total 9650000 # number of UpgradeReq miss cycles
504system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8467808500 # number of ReadExReq miss cycles
505system.cpu.l2cache.ReadExReq_miss_latency::total 8467808500 # number of ReadExReq miss cycles
506system.cpu.l2cache.demand_miss_latency::cpu.inst 185788500 # number of demand (read+write) miss cycles
507system.cpu.l2cache.demand_miss_latency::cpu.data 19876745000 # number of demand (read+write) miss cycles
508system.cpu.l2cache.demand_miss_latency::total 20062533500 # number of demand (read+write) miss cycles
509system.cpu.l2cache.overall_miss_latency::cpu.inst 185788500 # number of overall miss cycles
510system.cpu.l2cache.overall_miss_latency::cpu.data 19876745000 # number of overall miss cycles
511system.cpu.l2cache.overall_miss_latency::total 20062533500 # number of overall miss cycles
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513system.cpu.l2cache.ReadReq_accesses::cpu.data 1762180 # number of ReadReq accesses(hits+misses)
514system.cpu.l2cache.ReadReq_accesses::total 1773736 # number of ReadReq accesses(hits+misses)
515system.cpu.l2cache.Writeback_accesses::writebacks 2229936 # number of Writeback accesses(hits+misses)
516system.cpu.l2cache.Writeback_accesses::total 2229936 # number of Writeback accesses(hits+misses)
517system.cpu.l2cache.UpgradeReq_accesses::cpu.data 221060 # number of UpgradeReq accesses(hits+misses)
518system.cpu.l2cache.UpgradeReq_accesses::total 221060 # number of UpgradeReq accesses(hits+misses)
519system.cpu.l2cache.ReadExReq_accesses::cpu.data 771154 # number of ReadExReq accesses(hits+misses)
520system.cpu.l2cache.ReadExReq_accesses::total 771154 # number of ReadExReq accesses(hits+misses)
521system.cpu.l2cache.demand_accesses::cpu.inst 11556 # number of demand (read+write) accesses
522system.cpu.l2cache.demand_accesses::cpu.data 2533334 # number of demand (read+write) accesses
523system.cpu.l2cache.demand_accesses::total 2544890 # number of demand (read+write) accesses
524system.cpu.l2cache.overall_accesses::cpu.inst 11556 # number of overall (read+write) accesses
525system.cpu.l2cache.overall_accesses::cpu.data 2533334 # number of overall (read+write) accesses
526system.cpu.l2cache.overall_accesses::total 2544890 # number of overall (read+write) accesses
527system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.469367 # miss rate for ReadReq accesses
528system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189556 # miss rate for ReadReq accesses
529system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994169 # miss rate for UpgradeReq accesses
530system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320461 # miss rate for ReadExReq accesses
531system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469367 # miss rate for demand accesses
532system.cpu.l2cache.demand_miss_rate::cpu.data 0.229404 # miss rate for demand accesses
533system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469367 # miss rate for overall accesses
534system.cpu.l2cache.overall_miss_rate::cpu.data 0.229404 # miss rate for overall accesses
535system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.042035 # average ReadReq miss latency
536system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34155.220159 # average ReadReq miss latency
537system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 43.909342 # average UpgradeReq miss latency
538system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34265.284775 # average ReadExReq miss latency
539system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency
540system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency
541system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency
| 457system.cpu.l2cache.replacements 574923 # number of replacements
458system.cpu.l2cache.tagsinuse 21610.762617 # Cycle average of tags in use
459system.cpu.l2cache.total_refs 3193774 # Total number of references to valid blocks.
460system.cpu.l2cache.sampled_refs 594114 # Sample count of references to valid blocks.
461system.cpu.l2cache.avg_refs 5.375692 # Average number of references to valid blocks.
462system.cpu.l2cache.warmup_cycle 253017747000 # Cycle when the warmup percentage was hit.
463system.cpu.l2cache.occ_blocks::writebacks 13759.541955 # Average occupied blocks per requestor
464system.cpu.l2cache.occ_blocks::cpu.inst 63.216767 # Average occupied blocks per requestor
465system.cpu.l2cache.occ_blocks::cpu.data 7788.003895 # Average occupied blocks per requestor
466system.cpu.l2cache.occ_percent::writebacks 0.419908 # Average percentage of cache occupancy
467system.cpu.l2cache.occ_percent::cpu.inst 0.001929 # Average percentage of cache occupancy
468system.cpu.l2cache.occ_percent::cpu.data 0.237671 # Average percentage of cache occupancy
469system.cpu.l2cache.occ_percent::total 0.659508 # Average percentage of cache occupancy
470system.cpu.l2cache.ReadReq_hits::cpu.inst 6104 # number of ReadReq hits
471system.cpu.l2cache.ReadReq_hits::cpu.data 1427022 # number of ReadReq hits
472system.cpu.l2cache.ReadReq_hits::total 1433126 # number of ReadReq hits
473system.cpu.l2cache.Writeback_hits::writebacks 2228969 # number of Writeback hits
474system.cpu.l2cache.Writeback_hits::total 2228969 # number of Writeback hits
475system.cpu.l2cache.UpgradeReq_hits::cpu.data 1305 # number of UpgradeReq hits
476system.cpu.l2cache.UpgradeReq_hits::total 1305 # number of UpgradeReq hits
477system.cpu.l2cache.ReadExReq_hits::cpu.data 524074 # number of ReadExReq hits
478system.cpu.l2cache.ReadExReq_hits::total 524074 # number of ReadExReq hits
479system.cpu.l2cache.demand_hits::cpu.inst 6104 # number of demand (read+write) hits
480system.cpu.l2cache.demand_hits::cpu.data 1951096 # number of demand (read+write) hits
481system.cpu.l2cache.demand_hits::total 1957200 # number of demand (read+write) hits
482system.cpu.l2cache.overall_hits::cpu.inst 6104 # number of overall hits
483system.cpu.l2cache.overall_hits::cpu.data 1951096 # number of overall hits
484system.cpu.l2cache.overall_hits::total 1957200 # number of overall hits
485system.cpu.l2cache.ReadReq_misses::cpu.inst 5916 # number of ReadReq misses
486system.cpu.l2cache.ReadReq_misses::cpu.data 332816 # number of ReadReq misses
487system.cpu.l2cache.ReadReq_misses::total 338732 # number of ReadReq misses
488system.cpu.l2cache.UpgradeReq_misses::cpu.data 208530 # number of UpgradeReq misses
489system.cpu.l2cache.UpgradeReq_misses::total 208530 # number of UpgradeReq misses
490system.cpu.l2cache.ReadExReq_misses::cpu.data 247038 # number of ReadExReq misses
491system.cpu.l2cache.ReadExReq_misses::total 247038 # number of ReadExReq misses
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501system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9919500 # number of UpgradeReq miss cycles
502system.cpu.l2cache.UpgradeReq_miss_latency::total 9919500 # number of UpgradeReq miss cycles
503system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8463656500 # number of ReadExReq miss cycles
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505system.cpu.l2cache.demand_miss_latency::cpu.inst 202632500 # number of demand (read+write) miss cycles
506system.cpu.l2cache.demand_miss_latency::cpu.data 19826489500 # number of demand (read+write) miss cycles
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509system.cpu.l2cache.overall_miss_latency::cpu.data 19826489500 # number of overall miss cycles
510system.cpu.l2cache.overall_miss_latency::total 20029122000 # number of overall miss cycles
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512system.cpu.l2cache.ReadReq_accesses::cpu.data 1759838 # number of ReadReq accesses(hits+misses)
513system.cpu.l2cache.ReadReq_accesses::total 1771858 # number of ReadReq accesses(hits+misses)
514system.cpu.l2cache.Writeback_accesses::writebacks 2228969 # number of Writeback accesses(hits+misses)
515system.cpu.l2cache.Writeback_accesses::total 2228969 # number of Writeback accesses(hits+misses)
516system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209835 # number of UpgradeReq accesses(hits+misses)
517system.cpu.l2cache.UpgradeReq_accesses::total 209835 # number of UpgradeReq accesses(hits+misses)
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519system.cpu.l2cache.ReadExReq_accesses::total 771112 # number of ReadExReq accesses(hits+misses)
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521system.cpu.l2cache.demand_accesses::cpu.data 2530950 # number of demand (read+write) accesses
522system.cpu.l2cache.demand_accesses::total 2542970 # number of demand (read+write) accesses
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524system.cpu.l2cache.overall_accesses::cpu.data 2530950 # number of overall (read+write) accesses
525system.cpu.l2cache.overall_accesses::total 2542970 # number of overall (read+write) accesses
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527system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189117 # miss rate for ReadReq accesses
528system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993781 # miss rate for UpgradeReq accesses
529system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320366 # miss rate for ReadExReq accesses
530system.cpu.l2cache.demand_miss_rate::cpu.inst 0.492180 # miss rate for demand accesses
531system.cpu.l2cache.demand_miss_rate::cpu.data 0.229105 # miss rate for demand accesses
532system.cpu.l2cache.overall_miss_rate::cpu.inst 0.492180 # miss rate for overall accesses
533system.cpu.l2cache.overall_miss_rate::cpu.data 0.229105 # miss rate for overall accesses
534system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.605815 # average ReadReq miss latency
535system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.486587 # average ReadReq miss latency
536system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.568695 # average UpgradeReq miss latency
537system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34260.544936 # average ReadExReq miss latency
538system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency
539system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency
540system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency
541system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency
|
543system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
544system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
545system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
546system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
547system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
548system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
549system.cpu.l2cache.fast_writes 0 # number of fast writes performed
550system.cpu.l2cache.cache_copies 0 # number of cache copies performed
| 542system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
543system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
544system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
545system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
546system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
547system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
548system.cpu.l2cache.fast_writes 0 # number of fast writes performed
549system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
551system.cpu.l2cache.writebacks::writebacks 411540 # number of writebacks
552system.cpu.l2cache.writebacks::total 411540 # number of writebacks
553system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5424 # number of ReadReq MSHR misses
554system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334032 # number of ReadReq MSHR misses
555system.cpu.l2cache.ReadReq_mshr_misses::total 339456 # number of ReadReq MSHR misses
556system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 219771 # number of UpgradeReq MSHR misses
557system.cpu.l2cache.UpgradeReq_mshr_misses::total 219771 # number of UpgradeReq MSHR misses
558system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247125 # number of ReadExReq MSHR misses
559system.cpu.l2cache.ReadExReq_mshr_misses::total 247125 # number of ReadExReq MSHR misses
560system.cpu.l2cache.demand_mshr_misses::cpu.inst 5424 # number of demand (read+write) MSHR misses
561system.cpu.l2cache.demand_mshr_misses::cpu.data 581157 # number of demand (read+write) MSHR misses
562system.cpu.l2cache.demand_mshr_misses::total 586581 # number of demand (read+write) MSHR misses
563system.cpu.l2cache.overall_mshr_misses::cpu.inst 5424 # number of overall MSHR misses
564system.cpu.l2cache.overall_mshr_misses::cpu.data 581157 # number of overall MSHR misses
565system.cpu.l2cache.overall_mshr_misses::total 586581 # number of overall MSHR misses
566system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168319500 # number of ReadReq MSHR miss cycles
567system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10361694000 # number of ReadReq MSHR miss cycles
568system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10530013500 # number of ReadReq MSHR miss cycles
569system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6813351000 # number of UpgradeReq MSHR miss cycles
570system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6813351000 # number of UpgradeReq MSHR miss cycles
571system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7661828500 # number of ReadExReq MSHR miss cycles
572system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7661828500 # number of ReadExReq MSHR miss cycles
573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168319500 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18023522500 # number of demand (read+write) MSHR miss cycles
575system.cpu.l2cache.demand_mshr_miss_latency::total 18191842000 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168319500 # number of overall MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18023522500 # number of overall MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::total 18191842000 # number of overall MSHR miss cycles
579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for ReadReq accesses
580system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189556 # mshr miss rate for ReadReq accesses
581system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994169 # mshr miss rate for UpgradeReq accesses
582system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320461 # mshr miss rate for ReadExReq accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for demand accesses
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for overall accesses
587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31032.356195 # average ReadReq mshr miss latency
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.063946 # average ReadReq mshr miss latency
589system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31002.047586 # average UpgradeReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31003.858371 # average ReadExReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency
| 550system.cpu.l2cache.writebacks::writebacks 411215 # number of writebacks
551system.cpu.l2cache.writebacks::total 411215 # number of writebacks
552system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5916 # number of ReadReq MSHR misses
553system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332816 # number of ReadReq MSHR misses
554system.cpu.l2cache.ReadReq_mshr_misses::total 338732 # number of ReadReq MSHR misses
555system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208530 # number of UpgradeReq MSHR misses
556system.cpu.l2cache.UpgradeReq_mshr_misses::total 208530 # number of UpgradeReq MSHR misses
557system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247038 # number of ReadExReq MSHR misses
558system.cpu.l2cache.ReadExReq_mshr_misses::total 247038 # number of ReadExReq MSHR misses
559system.cpu.l2cache.demand_mshr_misses::cpu.inst 5916 # number of demand (read+write) MSHR misses
560system.cpu.l2cache.demand_mshr_misses::cpu.data 579854 # number of demand (read+write) MSHR misses
561system.cpu.l2cache.demand_mshr_misses::total 585770 # number of demand (read+write) MSHR misses
562system.cpu.l2cache.overall_mshr_misses::cpu.inst 5916 # number of overall MSHR misses
563system.cpu.l2cache.overall_mshr_misses::cpu.data 579854 # number of overall MSHR misses
564system.cpu.l2cache.overall_mshr_misses::total 585770 # number of overall MSHR misses
565system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183580000 # number of ReadReq MSHR miss cycles
566system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10325106000 # number of ReadReq MSHR miss cycles
567system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10508686000 # number of ReadReq MSHR miss cycles
568system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6464792000 # number of UpgradeReq MSHR miss cycles
569system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6464792000 # number of UpgradeReq MSHR miss cycles
570system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658792000 # number of ReadExReq MSHR miss cycles
571system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658792000 # number of ReadExReq MSHR miss cycles
572system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183580000 # number of demand (read+write) MSHR miss cycles
573system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17983898000 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.demand_mshr_miss_latency::total 18167478000 # number of demand (read+write) MSHR miss cycles
575system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183580000 # number of overall MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17983898000 # number of overall MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::total 18167478000 # number of overall MSHR miss cycles
578system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for ReadReq accesses
579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189117 # mshr miss rate for ReadReq accesses
580system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993781 # mshr miss rate for UpgradeReq accesses
581system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320366 # mshr miss rate for ReadExReq accesses
582system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for demand accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for demand accesses
584system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for overall accesses
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for overall accesses
586system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31031.102096 # average ReadReq mshr miss latency
587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.466420 # average ReadReq mshr miss latency
588system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.735961 # average UpgradeReq mshr miss latency
589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.485448 # average ReadExReq mshr miss latency
590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency
592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency
|
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596
597---------- End Simulation Statistics ----------
| 594system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
595
596---------- End Simulation Statistics ----------
|