| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.482382 # Number of seconds simulated 4sim_ticks 482382057000 # Number of ticks simulated 5final_tick 482382057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.487015 # Number of seconds simulated 4sim_ticks 487015166000 # Number of ticks simulated 5final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 90853 # Simulator instruction rate (inst/s) 8host_op_rate 168124 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53003549 # Simulator tick rate (ticks/s) 10host_mem_usage 321140 # Number of bytes of host memory used 11host_seconds 9100.94 # Real time elapsed on the host | 7host_inst_rate 125191 # Simulator instruction rate (inst/s) 8host_op_rate 231667 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 73737953 # Simulator tick rate (ticks/s) 10host_mem_usage 321616 # Number of bytes of host memory used 11host_seconds 6604.67 # Real time elapsed on the host |
| 12sim_insts 826847303 # Number of instructions simulated 13sim_ops 1530082520 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 826847303 # Number of instructions simulated 13sim_ops 1530082520 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24650752 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24805888 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 385168 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 387592 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 321604 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 51102133 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 51423737 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 321604 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 321604 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 39204244 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 39204244 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 39204244 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 321604 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 51102133 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 90627981 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 387592 # Number of read requests accepted 41system.physmem.writeReqs 295491 # Number of write requests accepted 42system.physmem.readBursts 387592 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 24786816 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue 46system.physmem.bytesWritten 18910464 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 24805888 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 154176 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24645952 # Number of bytes read from this memory 19system.physmem.bytes_read::total 24800128 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 154176 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 154176 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18907840 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18907840 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2409 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 385093 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 387502 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 295435 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 295435 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 316573 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 50606128 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 50922702 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 316573 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 316573 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 38823924 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 38823924 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 38823924 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 316573 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 50606128 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 89746626 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 387502 # Number of read requests accepted 41system.physmem.writeReqs 295435 # Number of write requests accepted 42system.physmem.readBursts 387502 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 295435 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 24780416 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 19712 # Total number of bytes read from write queue 46system.physmem.bytesWritten 18906304 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 24800128 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 18907840 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 308 # Number of DRAM read bursts serviced by the write queue |
| 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 52system.physmem.perBankRdBursts::0 24694 # Per bank write bursts 53system.physmem.perBankRdBursts::1 26457 # Per bank write bursts 54system.physmem.perBankRdBursts::2 24696 # Per bank write bursts 55system.physmem.perBankRdBursts::3 24495 # Per bank write bursts 56system.physmem.perBankRdBursts::4 23285 # Per bank write bursts 57system.physmem.perBankRdBursts::5 23614 # Per bank write bursts 58system.physmem.perBankRdBursts::6 24693 # Per bank write bursts 59system.physmem.perBankRdBursts::7 24448 # Per bank write bursts 60system.physmem.perBankRdBursts::8 23844 # Per bank write bursts 61system.physmem.perBankRdBursts::9 23582 # Per bank write bursts 62system.physmem.perBankRdBursts::10 24812 # Per bank write bursts 63system.physmem.perBankRdBursts::11 24004 # Per bank write bursts 64system.physmem.perBankRdBursts::12 23312 # Per bank write bursts 65system.physmem.perBankRdBursts::13 22998 # Per bank write bursts 66system.physmem.perBankRdBursts::14 24024 # Per bank write bursts 67system.physmem.perBankRdBursts::15 24336 # Per bank write bursts 68system.physmem.perBankWrBursts::0 19003 # Per bank write bursts 69system.physmem.perBankWrBursts::1 19960 # Per bank write bursts 70system.physmem.perBankWrBursts::2 19024 # Per bank write bursts 71system.physmem.perBankWrBursts::3 18975 # Per bank write bursts 72system.physmem.perBankWrBursts::4 18152 # Per bank write bursts 73system.physmem.perBankWrBursts::5 18441 # Per bank write bursts 74system.physmem.perBankWrBursts::6 19161 # Per bank write bursts 75system.physmem.perBankWrBursts::7 19119 # Per bank write bursts 76system.physmem.perBankWrBursts::8 18726 # Per bank write bursts 77system.physmem.perBankWrBursts::9 17970 # Per bank write bursts 78system.physmem.perBankWrBursts::10 18928 # Per bank write bursts 79system.physmem.perBankWrBursts::11 17785 # Per bank write bursts 80system.physmem.perBankWrBursts::12 17418 # Per bank write bursts 81system.physmem.perBankWrBursts::13 16994 # Per bank write bursts 82system.physmem.perBankWrBursts::14 17838 # Per bank write bursts 83system.physmem.perBankWrBursts::15 17982 # Per bank write bursts | 52system.physmem.perBankRdBursts::0 24677 # Per bank write bursts 53system.physmem.perBankRdBursts::1 26454 # Per bank write bursts 54system.physmem.perBankRdBursts::2 24704 # Per bank write bursts 55system.physmem.perBankRdBursts::3 24551 # Per bank write bursts 56system.physmem.perBankRdBursts::4 23256 # Per bank write bursts 57system.physmem.perBankRdBursts::5 23627 # Per bank write bursts 58system.physmem.perBankRdBursts::6 24680 # Per bank write bursts 59system.physmem.perBankRdBursts::7 24455 # Per bank write bursts 60system.physmem.perBankRdBursts::8 23806 # Per bank write bursts 61system.physmem.perBankRdBursts::9 23529 # Per bank write bursts 62system.physmem.perBankRdBursts::10 24814 # Per bank write bursts 63system.physmem.perBankRdBursts::11 23994 # Per bank write bursts 64system.physmem.perBankRdBursts::12 23307 # Per bank write bursts 65system.physmem.perBankRdBursts::13 23001 # Per bank write bursts 66system.physmem.perBankRdBursts::14 24016 # Per bank write bursts 67system.physmem.perBankRdBursts::15 24323 # Per bank write bursts 68system.physmem.perBankWrBursts::0 19004 # Per bank write bursts 69system.physmem.perBankWrBursts::1 19961 # Per bank write bursts 70system.physmem.perBankWrBursts::2 19032 # Per bank write bursts 71system.physmem.perBankWrBursts::3 19001 # Per bank write bursts 72system.physmem.perBankWrBursts::4 18129 # Per bank write bursts 73system.physmem.perBankWrBursts::5 18443 # Per bank write bursts 74system.physmem.perBankWrBursts::6 19167 # Per bank write bursts 75system.physmem.perBankWrBursts::7 19127 # Per bank write bursts 76system.physmem.perBankWrBursts::8 18708 # Per bank write bursts 77system.physmem.perBankWrBursts::9 17947 # Per bank write bursts 78system.physmem.perBankWrBursts::10 18897 # Per bank write bursts 79system.physmem.perBankWrBursts::11 17782 # Per bank write bursts 80system.physmem.perBankWrBursts::12 17420 # Per bank write bursts 81system.physmem.perBankWrBursts::13 16998 # Per bank write bursts 82system.physmem.perBankWrBursts::14 17822 # Per bank write bursts 83system.physmem.perBankWrBursts::15 17973 # Per bank write bursts |
| 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 482381969500 # Total gap between requests | 86system.physmem.totGap 487015078500 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 93system.physmem.readPktSize::6 387592 # Read request sizes (log2) | 93system.physmem.readPktSize::6 387502 # Read request sizes (log2) |
| 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) | 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 100system.physmem.writePktSize::6 295491 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 381809 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 5176 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see | 100system.physmem.writePktSize::6 295435 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 381038 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 5759 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::15 6410 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 6707 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 17432 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 17622 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 17641 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 17648 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 17656 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 17701 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 17669 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 17671 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 17699 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 17719 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 17664 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 17663 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 17636 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::15 6008 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 6294 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 17484 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 17673 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 17693 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 17697 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 17692 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 17694 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 17700 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 17696 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 17699 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 17704 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 17708 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 17805 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 17713 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 17722 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see --- 8 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see --- 8 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 146280 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 298.722669 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 176.940489 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 324.258352 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 52888 36.16% 36.16% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 40462 27.66% 63.82% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 14063 9.61% 73.43% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 7664 5.24% 78.67% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 5102 3.49% 82.16% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 3857 2.64% 84.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 2918 1.99% 86.79% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 2773 1.90% 88.68% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 16553 11.32% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 146280 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 17634 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 21.962913 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 18.199318 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 216.461189 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 17628 99.97% 99.97% # Reads before turning the bus around for writes | 197system.physmem.bytesPerActivate::samples 146349 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 298.501363 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 176.437841 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 325.145824 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 53058 36.25% 36.25% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 40951 27.98% 64.24% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 13535 9.25% 73.48% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 7606 5.20% 78.68% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 5054 3.45% 82.14% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 3741 2.56% 84.69% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 2872 1.96% 86.65% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 2862 1.96% 88.61% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 16670 11.39% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 146349 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 17683 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 21.896002 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 18.141977 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 216.215491 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 17677 99.97% 99.97% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 17634 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 17633 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 16.755969 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 16.728033 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 0.977832 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16 10918 61.92% 61.92% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::17 278 1.58% 63.49% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 6268 35.55% 99.04% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::19 161 0.91% 99.95% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20 7 0.04% 99.99% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::total 17633 # Writes before turning the bus around for reads 233system.physmem.totQLat 4311135000 # Total ticks spent queuing 234system.physmem.totMemAccLat 11572897500 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 1936470000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 11131.43 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 17683 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 17683 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 16.705932 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 16.678736 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 0.966667 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16 11382 64.37% 64.37% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::17 280 1.58% 65.95% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 5890 33.31% 99.26% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::19 116 0.66% 99.92% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20 11 0.06% 99.98% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::21 2 0.01% 99.99% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::total 17683 # Writes before turning the bus around for reads 235system.physmem.totQLat 9773520500 # Total ticks spent queuing 236system.physmem.totMemAccLat 17033408000 # Total ticks spent from burst creation until serviced by the DRAM 237system.physmem.totBusLat 1935970000 # Total ticks spent in databus transfers 238system.physmem.avgQLat 25241.92 # Average queueing delay per DRAM burst |
| 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 239system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 238system.physmem.avgMemAccLat 29881.43 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 51.38 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 39.20 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 51.42 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 39.20 # Average system write bandwidth in MiByte/s | 240system.physmem.avgMemAccLat 43991.92 # Average memory access latency per DRAM burst 241system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s 242system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s 243system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s 244system.physmem.avgWrBWSys 38.82 # Average system write bandwidth in MiByte/s |
| 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 245system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 244system.physmem.busUtil 0.71 # Data bus utilization in percentage | 246system.physmem.busUtil 0.70 # Data bus utilization in percentage |
| 245system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads | 247system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads |
| 246system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 248system.physmem.avgWrQLen 21.28 # Average write queue length when enqueuing 249system.physmem.readRowHits 315765 # Number of row buffer hits during reads 250system.physmem.writeRowHits 220723 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes 253system.physmem.avgGap 706183.54 # Average gap between requests 254system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined 255system.physmem_0.actEnergy 566682480 # Energy for activate commands per rank (pJ) 256system.physmem_0.preEnergy 309201750 # Energy for precharge commands per rank (pJ) 257system.physmem_0.readEnergy 1531779600 # Energy for read commands per rank (pJ) 258system.physmem_0.writeEnergy 983877840 # Energy for write commands per rank (pJ) 259system.physmem_0.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) 260system.physmem_0.actBackEnergy 69780771990 # Energy for active background per rank (pJ) 261system.physmem_0.preBackEnergy 228217880250 # Energy for precharge background per rank (pJ) 262system.physmem_0.totalEnergy 332897011590 # Total energy per rank (pJ) 263system.physmem_0.averagePower 690.111043 # Core power per rank (mW) 264system.physmem_0.memoryStateTime::IDLE 379065618250 # Time in different power states 265system.physmem_0.memoryStateTime::REF 16107780000 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.physmem_0.memoryStateTime::ACT 87208649000 # Time in different power states 268system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.physmem_1.actEnergy 539164080 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 294186750 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 1489098000 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 930690000 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) 274system.physmem_1.actBackEnergy 67080778605 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 230586295500 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 332427030615 # Total energy per rank (pJ) 277system.physmem_1.averagePower 689.136751 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 383030551000 # Time in different power states 279system.physmem_1.memoryStateTime::REF 16107780000 # Time in different power states 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 281system.physmem_1.memoryStateTime::ACT 83243489000 # Time in different power states 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 283system.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 284system.cpu.branchPred.lookups 297919436 # Number of BP lookups 285system.cpu.branchPred.condPredicted 297919436 # Number of conditional branches predicted 286system.cpu.branchPred.condIncorrect 23611614 # Number of conditional branches incorrect 287system.cpu.branchPred.BTBLookups 229854393 # Number of BTB lookups | 248system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes 249system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 250system.physmem.avgWrQLen 20.86 # Average write queue length when enqueuing 251system.physmem.readRowHits 316194 # Number of row buffer hits during reads 252system.physmem.writeRowHits 220049 # Number of row buffer hits during writes 253system.physmem.readRowHitRate 81.66 # Row buffer hit rate for reads 254system.physmem.writeRowHitRate 74.48 # Row buffer hit rate for writes 255system.physmem.avgGap 713118.60 # Average gap between requests 256system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined 257system.physmem_0.actEnergy 536506740 # Energy for activate commands per rank (pJ) 258system.physmem_0.preEnergy 285137325 # Energy for precharge commands per rank (pJ) 259system.physmem_0.readEnergy 1402324560 # Energy for read commands per rank (pJ) 260system.physmem_0.writeEnergy 792730080 # Energy for write commands per rank (pJ) 261system.physmem_0.refreshEnergy 13527611760.000004 # Energy for refresh commands per rank (pJ) 262system.physmem_0.actBackEnergy 8827375680 # Energy for active background per rank (pJ) 263system.physmem_0.preBackEnergy 730358400 # Energy for precharge background per rank (pJ) 264system.physmem_0.actPowerDownEnergy 36195677160 # Energy for active power-down per rank (pJ) 265system.physmem_0.prePowerDownEnergy 16995876480 # Energy for precharge power-down per rank (pJ) 266system.physmem_0.selfRefreshEnergy 84126324885 # Energy for self refresh per rank (pJ) 267system.physmem_0.totalEnergy 163425034830 # Total energy per rank (pJ) 268system.physmem_0.averagePower 335.564568 # Core power per rank (mW) 269system.physmem_0.totalIdleTime 465742918500 # Total Idle time Per DRAM Rank 270system.physmem_0.memoryStateTime::IDLE 1151920500 # Time in different power states 271system.physmem_0.memoryStateTime::REF 5744978000 # Time in different power states 272system.physmem_0.memoryStateTime::SREF 342106910750 # Time in different power states 273system.physmem_0.memoryStateTime::PRE_PDN 44260034250 # Time in different power states 274system.physmem_0.memoryStateTime::ACT 14374729750 # Time in different power states 275system.physmem_0.memoryStateTime::ACT_PDN 79376592750 # Time in different power states 276system.physmem_1.actEnergy 508517940 # Energy for activate commands per rank (pJ) 277system.physmem_1.preEnergy 270257130 # Energy for precharge commands per rank (pJ) 278system.physmem_1.readEnergy 1362240600 # Energy for read commands per rank (pJ) 279system.physmem_1.writeEnergy 749315340 # Energy for write commands per rank (pJ) 280system.physmem_1.refreshEnergy 13073392800.000004 # Energy for refresh commands per rank (pJ) 281system.physmem_1.actBackEnergy 8818641570 # Energy for active background per rank (pJ) 282system.physmem_1.preBackEnergy 720149760 # Energy for precharge background per rank (pJ) 283system.physmem_1.actPowerDownEnergy 34369694130 # Energy for active power-down per rank (pJ) 284system.physmem_1.prePowerDownEnergy 16456043520 # Energy for precharge power-down per rank (pJ) 285system.physmem_1.selfRefreshEnergy 85412982225 # Energy for self refresh per rank (pJ) 286system.physmem_1.totalEnergy 161745926205 # Total energy per rank (pJ) 287system.physmem_1.averagePower 332.116816 # Core power per rank (mW) 288system.physmem_1.totalIdleTime 465789870750 # Total Idle time Per DRAM Rank 289system.physmem_1.memoryStateTime::IDLE 1150076250 # Time in different power states 290system.physmem_1.memoryStateTime::REF 5552712000 # Time in different power states 291system.physmem_1.memoryStateTime::SREF 347563722250 # Time in different power states 292system.physmem_1.memoryStateTime::PRE_PDN 42854288750 # Time in different power states 293system.physmem_1.memoryStateTime::ACT 14522378750 # Time in different power states 294system.physmem_1.memoryStateTime::ACT_PDN 75371988000 # Time in different power states 295system.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 296system.cpu.branchPred.lookups 298029097 # Number of BP lookups 297system.cpu.branchPred.condPredicted 298029097 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 23616389 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 229942542 # Number of BTB lookups |
| 288system.cpu.branchPred.BTBHits 0 # Number of BTB hits 289system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 290system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage | 300system.cpu.branchPred.BTBHits 0 # Number of BTB hits 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 302system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage |
| 291system.cpu.branchPred.usedRAS 40311454 # Number of times the RAS was used to get a target. 292system.cpu.branchPred.RASInCorrect 4410387 # Number of incorrect RAS predictions. 293system.cpu.branchPred.indirectLookups 229854393 # Number of indirect predictor lookups. 294system.cpu.branchPred.indirectHits 119921311 # Number of indirect target hits. 295system.cpu.branchPred.indirectMisses 109933082 # Number of indirect misses. 296system.cpu.branchPredindirectMispredicted 11586406 # Number of mispredicted indirect branches. | 303system.cpu.branchPred.usedRAS 40333391 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 4390674 # Number of incorrect RAS predictions. 305system.cpu.branchPred.indirectLookups 229942542 # Number of indirect predictor lookups. 306system.cpu.branchPred.indirectHits 119860888 # Number of indirect target hits. 307system.cpu.branchPred.indirectMisses 110081654 # Number of indirect misses. 308system.cpu.branchPredindirectMispredicted 11613915 # Number of mispredicted indirect branches. |
| 297system.cpu_clk_domain.clock 500 # Clock period in ticks | 309system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 298system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states | 310system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states |
| 299system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 311system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 300system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 301system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states | 312system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 313system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states |
| 302system.cpu.workload.num_syscalls 551 # Number of system calls | 314system.cpu.workload.num_syscalls 551 # Number of system calls |
| 303system.cpu.pwrStateResidencyTicks::ON 482382057000 # Cumulative time (in ticks) in various power states 304system.cpu.numCycles 964764115 # number of cpu cycles simulated | 315system.cpu.pwrStateResidencyTicks::ON 487015166000 # Cumulative time (in ticks) in various power states 316system.cpu.numCycles 974030333 # number of cpu cycles simulated |
| 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 317system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 318system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 307system.cpu.fetch.icacheStallCycles 229640733 # Number of cycles fetch is stalled on an Icache miss 308system.cpu.fetch.Insts 1587519909 # Number of instructions fetch has processed 309system.cpu.fetch.Branches 297919436 # Number of branches that fetch encountered 310system.cpu.fetch.predictedBranches 160232765 # Number of branches that fetch has predicted taken 311system.cpu.fetch.Cycles 710474501 # Number of cycles fetch has run and was not squashing or blocked 312system.cpu.fetch.SquashCycles 48125197 # Number of cycles fetch has spent squashing 313system.cpu.fetch.TlbCycles 1838 # Number of cycles fetch has spent waiting for tlb 314system.cpu.fetch.MiscStallCycles 31961 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 315system.cpu.fetch.PendingTrapStallCycles 395431 # Number of stall cycles due to pending traps 316system.cpu.fetch.PendingQuiesceStallCycles 7638 # Number of stall cycles due to pending quiesce instructions | 319system.cpu.fetch.icacheStallCycles 229618225 # Number of cycles fetch is stalled on an Icache miss 320system.cpu.fetch.Insts 1587637398 # Number of instructions fetch has processed 321system.cpu.fetch.Branches 298029097 # Number of branches that fetch encountered 322system.cpu.fetch.predictedBranches 160194279 # Number of branches that fetch has predicted taken 323system.cpu.fetch.Cycles 719695482 # Number of cycles fetch has run and was not squashing or blocked 324system.cpu.fetch.SquashCycles 48136797 # Number of cycles fetch has spent squashing 325system.cpu.fetch.TlbCycles 1337 # Number of cycles fetch has spent waiting for tlb 326system.cpu.fetch.MiscStallCycles 32063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 327system.cpu.fetch.PendingTrapStallCycles 398708 # Number of stall cycles due to pending traps 328system.cpu.fetch.PendingQuiesceStallCycles 8912 # Number of stall cycles due to pending quiesce instructions |
| 317system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR | 329system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR |
| 318system.cpu.fetch.CacheLines 216406816 # Number of cache lines fetched 319system.cpu.fetch.IcacheSquashes 6303131 # Number of outstanding Icache misses that were squashed | 330system.cpu.fetch.CacheLines 216378015 # Number of cache lines fetched 331system.cpu.fetch.IcacheSquashes 6307023 # Number of outstanding Icache misses that were squashed |
| 320system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed | 332system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed |
| 321system.cpu.fetch.rateDist::samples 964614734 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::mean 3.081549 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::stdev 3.494827 # Number of instructions fetched each cycle (Total) | 333system.cpu.fetch.rateDist::samples 973823159 # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::mean 3.052791 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::stdev 3.491297 # Number of instructions fetched each cycle (Total) |
| 324system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 336system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 325system.cpu.fetch.rateDist::0 473031835 49.04% 49.04% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::1 36413294 3.77% 52.81% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::2 36207947 3.75% 56.57% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::3 33239258 3.45% 60.01% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::4 28476947 2.95% 62.96% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::5 30017172 3.11% 66.08% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::6 40187194 4.17% 70.24% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::7 37484755 3.89% 74.13% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::8 249556332 25.87% 100.00% # Number of instructions fetched each cycle (Total) | 337system.cpu.fetch.rateDist::0 482221410 49.52% 49.52% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::1 36458558 3.74% 53.26% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::2 36184065 3.72% 56.98% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::3 33102262 3.40% 60.38% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::4 28599787 2.94% 63.31% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::5 29969705 3.08% 66.39% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::6 40168402 4.12% 70.52% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::7 37465076 3.85% 74.36% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::8 249653894 25.64% 100.00% # Number of instructions fetched each cycle (Total) |
| 334system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 346system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 337system.cpu.fetch.rateDist::total 964614734 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.branchRate 0.308800 # Number of branch fetches per cycle 339system.cpu.fetch.rate 1.645501 # Number of inst fetches per cycle 340system.cpu.decode.IdleCycles 165560291 # Number of cycles decode is idle 341system.cpu.decode.BlockedCycles 381637451 # Number of cycles decode is blocked 342system.cpu.decode.RunCycles 312327895 # Number of cycles decode is running 343system.cpu.decode.UnblockCycles 81026499 # Number of cycles decode is unblocking 344system.cpu.decode.SquashCycles 24062598 # Number of cycles decode is squashing 345system.cpu.decode.DecodedInsts 2744008679 # Number of instructions handled by decode 346system.cpu.rename.SquashCycles 24062598 # Number of cycles rename is squashing 347system.cpu.rename.IdleCycles 201558349 # Number of cycles rename is idle 348system.cpu.rename.BlockCycles 194036216 # Number of cycles rename is blocking 349system.cpu.rename.serializeStallCycles 13250 # count of cycles rename stalled for serializing inst 350system.cpu.rename.RunCycles 351418098 # Number of cycles rename is running 351system.cpu.rename.UnblockCycles 193526223 # Number of cycles rename is unblocking 352system.cpu.rename.RenamedInsts 2626516746 # Number of instructions processed by rename 353system.cpu.rename.ROBFullEvents 906315 # Number of times rename has blocked due to ROB full 354system.cpu.rename.IQFullEvents 120859920 # Number of times rename has blocked due to IQ full 355system.cpu.rename.LQFullEvents 22304361 # Number of times rename has blocked due to LQ full 356system.cpu.rename.SQFullEvents 41770089 # Number of times rename has blocked due to SQ full 357system.cpu.rename.RenamedOperands 2707207684 # Number of destination operands rename has renamed 358system.cpu.rename.RenameLookups 6591914084 # Number of register rename lookups that rename has made 359system.cpu.rename.int_rename_lookups 4206827635 # Number of integer rename lookups 360system.cpu.rename.fp_rename_lookups 2574467 # Number of floating rename lookups | 349system.cpu.fetch.rateDist::total 973823159 # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.branchRate 0.305975 # Number of branch fetches per cycle 351system.cpu.fetch.rate 1.629967 # Number of inst fetches per cycle 352system.cpu.decode.IdleCycles 165565722 # Number of cycles decode is idle 353system.cpu.decode.BlockedCycles 390830119 # Number of cycles decode is blocked 354system.cpu.decode.RunCycles 312240973 # Number of cycles decode is running 355system.cpu.decode.UnblockCycles 81117947 # Number of cycles decode is unblocking 356system.cpu.decode.SquashCycles 24068398 # Number of cycles decode is squashing 357system.cpu.decode.DecodedInsts 2744223716 # Number of instructions handled by decode 358system.cpu.rename.SquashCycles 24068398 # Number of cycles rename is squashing 359system.cpu.rename.IdleCycles 201650614 # Number of cycles rename is idle 360system.cpu.rename.BlockCycles 200101577 # Number of cycles rename is blocking 361system.cpu.rename.serializeStallCycles 12340 # count of cycles rename stalled for serializing inst 362system.cpu.rename.RunCycles 351328141 # Number of cycles rename is running 363system.cpu.rename.UnblockCycles 196662089 # Number of cycles rename is unblocking 364system.cpu.rename.RenamedInsts 2626762649 # Number of instructions processed by rename 365system.cpu.rename.ROBFullEvents 653926 # Number of times rename has blocked due to ROB full 366system.cpu.rename.IQFullEvents 121379246 # Number of times rename has blocked due to IQ full 367system.cpu.rename.LQFullEvents 22369281 # Number of times rename has blocked due to LQ full 368system.cpu.rename.SQFullEvents 44360312 # Number of times rename has blocked due to SQ full 369system.cpu.rename.RenamedOperands 2707190257 # Number of destination operands rename has renamed 370system.cpu.rename.RenameLookups 6592545635 # Number of register rename lookups that rename has made 371system.cpu.rename.int_rename_lookups 4207329612 # Number of integer rename lookups 372system.cpu.rename.fp_rename_lookups 2546306 # Number of floating rename lookups |
| 361system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed | 373system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed |
| 362system.cpu.rename.UndoneMaps 1090246112 # Number of HB maps that are undone due to squashing 363system.cpu.rename.serializingInsts 1066 # count of serializing insts renamed 364system.cpu.rename.tempSerializingInsts 982 # count of temporary serializing insts renamed 365system.cpu.rename.skidInsts 368286677 # count of insts added to the skid buffer 366system.cpu.memDep0.insertedLoads 608256588 # Number of loads inserted to the mem dependence unit. 367system.cpu.memDep0.insertedStores 244134978 # Number of stores inserted to the mem dependence unit. 368system.cpu.memDep0.conflictingLoads 253265740 # Number of conflicting loads. 369system.cpu.memDep0.conflictingStores 76368619 # Number of conflicting stores. 370system.cpu.iq.iqInstsAdded 2419508786 # Number of instructions added to the IQ (excludes non-spec) 371system.cpu.iq.iqNonSpecInstsAdded 132419 # Number of non-speculative instructions added to the IQ 372system.cpu.iq.iqInstsIssued 1999186857 # Number of instructions issued 373system.cpu.iq.iqSquashedInstsIssued 3656712 # Number of squashed instructions issued 374system.cpu.iq.iqSquashedInstsExamined 889558685 # Number of squashed instructions iterated over during squash; mainly for profiling 375system.cpu.iq.iqSquashedOperandsExamined 1510180986 # Number of squashed operands that are examined and possibly removed from graph 376system.cpu.iq.iqSquashedNonSpecRemoved 131867 # Number of squashed non-spec instructions that were removed 377system.cpu.iq.issued_per_cycle::samples 964614734 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::mean 2.072524 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::stdev 2.106121 # Number of insts issued each cycle | 374system.cpu.rename.UndoneMaps 1090228685 # Number of HB maps that are undone due to squashing 375system.cpu.rename.serializingInsts 1055 # count of serializing insts renamed 376system.cpu.rename.tempSerializingInsts 956 # count of temporary serializing insts renamed 377system.cpu.rename.skidInsts 369291247 # count of insts added to the skid buffer 378system.cpu.memDep0.insertedLoads 608349007 # Number of loads inserted to the mem dependence unit. 379system.cpu.memDep0.insertedStores 244126939 # Number of stores inserted to the mem dependence unit. 380system.cpu.memDep0.conflictingLoads 253380233 # Number of conflicting loads. 381system.cpu.memDep0.conflictingStores 76614927 # Number of conflicting stores. 382system.cpu.iq.iqInstsAdded 2419683470 # Number of instructions added to the IQ (excludes non-spec) 383system.cpu.iq.iqNonSpecInstsAdded 114601 # Number of non-speculative instructions added to the IQ 384system.cpu.iq.iqInstsIssued 1999301644 # Number of instructions issued 385system.cpu.iq.iqSquashedInstsIssued 3644555 # Number of squashed instructions issued 386system.cpu.iq.iqSquashedInstsExamined 889715551 # Number of squashed instructions iterated over during squash; mainly for profiling 387system.cpu.iq.iqSquashedOperandsExamined 1510079207 # Number of squashed operands that are examined and possibly removed from graph 388system.cpu.iq.iqSquashedNonSpecRemoved 114049 # Number of squashed non-spec instructions that were removed 389system.cpu.iq.issued_per_cycle::samples 973823159 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::mean 2.053044 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::stdev 2.105688 # Number of insts issued each cycle |
| 380system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 392system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 381system.cpu.iq.issued_per_cycle::0 336173556 34.85% 34.85% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::1 135262022 14.02% 48.87% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::2 129832579 13.46% 62.33% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::3 119015920 12.34% 74.67% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::4 98090682 10.17% 84.84% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::5 67084509 6.95% 91.79% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::6 45576707 4.72% 96.52% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::7 22663670 2.35% 98.87% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::8 10915089 1.13% 100.00% # Number of insts issued each cycle | 393system.cpu.iq.issued_per_cycle::0 345234545 35.45% 35.45% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::1 135418864 13.91% 49.36% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::2 129821558 13.33% 62.69% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::3 119307207 12.25% 74.94% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::4 97554322 10.02% 84.96% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::5 67238440 6.90% 91.86% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::6 45741413 4.70% 96.56% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::7 22594403 2.32% 98.88% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::8 10912407 1.12% 100.00% # Number of insts issued each cycle |
| 390system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 402system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 393system.cpu.iq.issued_per_cycle::total 964614734 # Number of insts issued each cycle | 405system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle |
| 394system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 406system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 395system.cpu.iq.fu_full::IntAlu 11249182 43.29% 43.29% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntMult 0 0.00% 43.29% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntDiv 0 0.00% 43.29% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.29% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.29% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.29% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatMult 0 0.00% 43.29% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.29% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.29% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.29% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.29% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.29% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.29% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.29% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.29% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMult 0 0.00% 43.29% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.29% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShift 0 0.00% 43.29% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.29% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.29% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.29% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.29% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.29% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.29% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.29% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.29% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.29% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.29% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.29% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemRead 11894821 45.77% 89.06% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemWrite 2844033 10.94% 100.00% # attempts to use FU when none available | 407system.cpu.iq.fu_full::IntAlu 11212757 43.22% 43.22% # attempts to use FU when none available 408system.cpu.iq.fu_full::IntMult 0 0.00% 43.22% # attempts to use FU when none available 409system.cpu.iq.fu_full::IntDiv 0 0.00% 43.22% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.22% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.22% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.22% # attempts to use FU when none available 413system.cpu.iq.fu_full::FloatMult 0 0.00% 43.22% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.22% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.22% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.22% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.22% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.22% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.22% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.22% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.22% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdMult 0 0.00% 43.22% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.22% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdShift 0 0.00% 43.22% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.22% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.22% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.22% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.22% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.22% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.22% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.22% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.22% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.22% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.22% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.22% # attempts to use FU when none available 436system.cpu.iq.fu_full::MemRead 11924633 45.96% 89.18% # attempts to use FU when none available 437system.cpu.iq.fu_full::MemWrite 2807188 10.82% 100.00% # attempts to use FU when none available |
| 426system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 427system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 438system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 439system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 428system.cpu.iq.FU_type_0::No_OpClass 2910415 0.15% 0.15% # Type of FU issued 429system.cpu.iq.FU_type_0::IntAlu 1333514799 66.70% 66.85% # Type of FU issued 430system.cpu.iq.FU_type_0::IntMult 358060 0.02% 66.87% # Type of FU issued 431system.cpu.iq.FU_type_0::IntDiv 4798571 0.24% 67.11% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 67.11% # Type of FU issued | 440system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued 441system.cpu.iq.FU_type_0::IntAlu 1333663160 66.71% 66.85% # Type of FU issued 442system.cpu.iq.FU_type_0::IntMult 357468 0.02% 66.87% # Type of FU issued 443system.cpu.iq.FU_type_0::IntDiv 4798486 0.24% 67.11% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Type of FU issued |
| 433system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued | 445system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued 446system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued |
| 435system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued | 447system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued |
| 437system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 450system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued | 449system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 462system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued |
| 458system.cpu.iq.FU_type_0::MemRead 471222917 23.57% 90.68% # Type of FU issued 459system.cpu.iq.FU_type_0::MemWrite 186382093 9.32% 100.00% # Type of FU issued | 470system.cpu.iq.FU_type_0::MemRead 471201648 23.57% 90.68% # Type of FU issued 471system.cpu.iq.FU_type_0::MemWrite 186365855 9.32% 100.00% # Type of FU issued |
| 460system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 472system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 473system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 462system.cpu.iq.FU_type_0::total 1999186857 # Type of FU issued 463system.cpu.iq.rate 2.072203 # Inst issue rate 464system.cpu.iq.fu_busy_cnt 25988036 # FU busy when requested 465system.cpu.iq.fu_busy_rate 0.012999 # FU busy rate (busy events/executed inst) 466system.cpu.iq.int_inst_queue_reads 4991322155 # Number of integer instruction queue reads 467system.cpu.iq.int_inst_queue_writes 3305635589 # Number of integer instruction queue writes 468system.cpu.iq.int_inst_queue_wakeup_accesses 1923777377 # Number of integer instruction queue wakeup accesses 469system.cpu.iq.fp_inst_queue_reads 1311041 # Number of floating instruction queue reads 470system.cpu.iq.fp_inst_queue_writes 4133688 # Number of floating instruction queue writes 471system.cpu.iq.fp_inst_queue_wakeup_accesses 240317 # Number of floating instruction queue wakeup accesses 472system.cpu.iq.int_alu_accesses 2021708405 # Number of integer alu accesses 473system.cpu.iq.fp_alu_accesses 556073 # Number of floating point alu accesses 474system.cpu.iew.lsq.thread0.forwLoads 179295064 # Number of loads that had data forwarded from stores | 474system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued 475system.cpu.iq.rate 2.052607 # Inst issue rate 476system.cpu.iq.fu_busy_cnt 25944578 # FU busy when requested 477system.cpu.iq.fu_busy_rate 0.012977 # FU busy rate (busy events/executed inst) 478system.cpu.iq.int_inst_queue_reads 5000714674 # Number of integer instruction queue reads 479system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes 480system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses 481system.cpu.iq.fp_inst_queue_reads 1300906 # Number of floating instruction queue reads 482system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes 483system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses 484system.cpu.iq.int_alu_accesses 2021778795 # Number of integer alu accesses 485system.cpu.iq.fp_alu_accesses 552407 # Number of floating point alu accesses 486system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores |
| 475system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 487system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 476system.cpu.iew.lsq.thread0.squashedLoads 224173511 # Number of loads squashed 477system.cpu.iew.lsq.thread0.ignoredResponses 339017 # Number of memory responses ignored because the instruction is squashed 478system.cpu.iew.lsq.thread0.memOrderViolation 636964 # Number of memory ordering violations 479system.cpu.iew.lsq.thread0.squashedStores 94976783 # Number of stores squashed | 488system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed 489system.cpu.iew.lsq.thread0.ignoredResponses 337750 # Number of memory responses ignored because the instruction is squashed 490system.cpu.iew.lsq.thread0.memOrderViolation 639215 # Number of memory ordering violations 491system.cpu.iew.lsq.thread0.squashedStores 94968744 # Number of stores squashed |
| 480system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 481system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 492system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 493system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 482system.cpu.iew.lsq.thread0.rescheduledLoads 31958 # Number of loads that were rescheduled 483system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked | 494system.cpu.iew.lsq.thread0.rescheduledLoads 31938 # Number of loads that were rescheduled 495system.cpu.iew.lsq.thread0.cacheBlocked 869 # Number of times an access to memory failed due to the cache being blocked |
| 484system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 496system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 485system.cpu.iew.iewSquashCycles 24062598 # Number of cycles IEW is squashing 486system.cpu.iew.iewBlockCycles 144797851 # Number of cycles IEW is blocking 487system.cpu.iew.iewUnblockCycles 6250562 # Number of cycles IEW is unblocking 488system.cpu.iew.iewDispatchedInsts 2419641205 # Number of instructions dispatched to IQ 489system.cpu.iew.iewDispSquashedInsts 1306710 # Number of squashed instructions skipped by dispatch 490system.cpu.iew.iewDispLoadInsts 608256824 # Number of dispatched load instructions 491system.cpu.iew.iewDispStoreInsts 244134978 # Number of dispatched store instructions 492system.cpu.iew.iewDispNonSpecInsts 45669 # Number of dispatched non-speculative instructions 493system.cpu.iew.iewIQFullEvents 1454928 # Number of times the IQ has become full, causing a stall 494system.cpu.iew.iewLSQFullEvents 3966770 # Number of times the LSQ has become full, causing a stall 495system.cpu.iew.memOrderViolationEvents 636964 # Number of memory order violations 496system.cpu.iew.predictedTakenIncorrect 8731316 # Number of branches that were predicted taken incorrectly 497system.cpu.iew.predictedNotTakenIncorrect 20649413 # Number of branches that were predicted not taken incorrectly 498system.cpu.iew.branchMispredicts 29380729 # Number of branch mispredicts detected at execute 499system.cpu.iew.iewExecutedInsts 1945668790 # Number of executed instructions 500system.cpu.iew.iewExecLoadInsts 456756594 # Number of load instructions executed 501system.cpu.iew.iewExecSquashedInsts 53518067 # Number of squashed instructions skipped in execute | 497system.cpu.iew.iewSquashCycles 24068398 # Number of cycles IEW is squashing 498system.cpu.iew.iewBlockCycles 149571445 # Number of cycles IEW is blocking 499system.cpu.iew.iewUnblockCycles 6693651 # Number of cycles IEW is unblocking 500system.cpu.iew.iewDispatchedInsts 2419798071 # Number of instructions dispatched to IQ 501system.cpu.iew.iewDispSquashedInsts 1305719 # Number of squashed instructions skipped by dispatch 502system.cpu.iew.iewDispLoadInsts 608349109 # Number of dispatched load instructions 503system.cpu.iew.iewDispStoreInsts 244126939 # Number of dispatched store instructions 504system.cpu.iew.iewDispNonSpecInsts 39730 # Number of dispatched non-speculative instructions 505system.cpu.iew.iewIQFullEvents 1462244 # Number of times the IQ has become full, causing a stall 506system.cpu.iew.iewLSQFullEvents 4395107 # Number of times the LSQ has become full, causing a stall 507system.cpu.iew.memOrderViolationEvents 639215 # Number of memory order violations 508system.cpu.iew.predictedTakenIncorrect 8704418 # Number of branches that were predicted taken incorrectly 509system.cpu.iew.predictedNotTakenIncorrect 20695714 # Number of branches that were predicted not taken incorrectly 510system.cpu.iew.branchMispredicts 29400132 # Number of branch mispredicts detected at execute 511system.cpu.iew.iewExecutedInsts 1945833568 # Number of executed instructions 512system.cpu.iew.iewExecLoadInsts 456792637 # Number of load instructions executed 513system.cpu.iew.iewExecSquashedInsts 53468076 # Number of squashed instructions skipped in execute |
| 502system.cpu.iew.exec_swp 0 # number of swp insts executed 503system.cpu.iew.exec_nop 0 # number of nop insts executed | 514system.cpu.iew.exec_swp 0 # number of swp insts executed 515system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 504system.cpu.iew.exec_refs 635598570 # number of memory reference insts executed 505system.cpu.iew.exec_branches 185172751 # Number of branches executed 506system.cpu.iew.exec_stores 178841976 # Number of stores executed 507system.cpu.iew.exec_rate 2.016730 # Inst execution rate 508system.cpu.iew.wb_sent 1934534562 # cumulative count of insts sent to commit 509system.cpu.iew.wb_count 1924017694 # cumulative count of insts written-back 510system.cpu.iew.wb_producers 1456930726 # num instructions producing a value 511system.cpu.iew.wb_consumers 2203703226 # num instructions consuming a value 512system.cpu.iew.wb_rate 1.994288 # insts written-back per cycle 513system.cpu.iew.wb_fanout 0.661128 # average fanout of values written-back 514system.cpu.commit.commitSquashedInsts 889633438 # The number of squashed insts skipped by commit | 516system.cpu.iew.exec_refs 635592905 # number of memory reference insts executed 517system.cpu.iew.exec_branches 185215439 # Number of branches executed 518system.cpu.iew.exec_stores 178800268 # Number of stores executed 519system.cpu.iew.exec_rate 1.997714 # Inst execution rate 520system.cpu.iew.wb_sent 1934717341 # cumulative count of insts sent to commit 521system.cpu.iew.wb_count 1924191844 # cumulative count of insts written-back 522system.cpu.iew.wb_producers 1457208218 # num instructions producing a value 523system.cpu.iew.wb_consumers 2204046368 # num instructions consuming a value 524system.cpu.iew.wb_rate 1.975495 # insts written-back per cycle 525system.cpu.iew.wb_fanout 0.661151 # average fanout of values written-back 526system.cpu.commit.commitSquashedInsts 889791004 # The number of squashed insts skipped by commit |
| 515system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards | 527system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards |
| 516system.cpu.commit.branchMispredicts 23642184 # The number of times a branch was mispredicted 517system.cpu.commit.committed_per_cycle::samples 831915086 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::mean 1.839229 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::stdev 2.465352 # Number of insts commited each cycle | 528system.cpu.commit.branchMispredicts 23647177 # The number of times a branch was mispredicted 529system.cpu.commit.committed_per_cycle::samples 841074000 # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::mean 1.819201 # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::stdev 2.458814 # Number of insts commited each cycle |
| 520system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 532system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 521system.cpu.commit.committed_per_cycle::0 352165945 42.33% 42.33% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::1 184695932 22.20% 64.53% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::2 57945588 6.97% 71.50% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::3 87210863 10.48% 81.98% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::4 30437769 3.66% 85.64% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::5 26536432 3.19% 88.83% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::6 10472867 1.26% 90.09% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::7 9005135 1.08% 91.17% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::8 73444555 8.83% 100.00% # Number of insts commited each cycle | 533system.cpu.commit.committed_per_cycle::0 361210845 42.95% 42.95% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::1 184795052 21.97% 64.92% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::2 57840397 6.88% 71.79% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::3 87376864 10.39% 82.18% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::4 30415751 3.62% 85.80% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::5 26609914 3.16% 88.96% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::6 10385763 1.23% 90.20% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::7 9066382 1.08% 91.28% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::8 73373032 8.72% 100.00% # Number of insts commited each cycle |
| 530system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 542system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 533system.cpu.commit.committed_per_cycle::total 831915086 # Number of insts commited each cycle | 545system.cpu.commit.committed_per_cycle::total 841074000 # Number of insts commited each cycle |
| 534system.cpu.commit.committedInsts 826847303 # Number of instructions committed 535system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed 536system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 537system.cpu.commit.refs 533241508 # Number of memory references committed 538system.cpu.commit.loads 384083313 # Number of loads committed 539system.cpu.commit.membars 0 # Number of memory barriers committed 540system.cpu.commit.branches 149981740 # Number of branches committed 541system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 571system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction 574system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction 575system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction 576system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 578system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction | 546system.cpu.commit.committedInsts 826847303 # Number of instructions committed 547system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed 548system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 549system.cpu.commit.refs 533241508 # Number of memory references committed 550system.cpu.commit.loads 384083313 # Number of loads committed 551system.cpu.commit.membars 0 # Number of memory barriers committed 552system.cpu.commit.branches 149981740 # Number of branches committed 553system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 583system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction 584system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction 585system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction 586system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction 587system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction 588system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 589system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 590system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction |
| 579system.cpu.commit.bw_lim_events 73444555 # number cycles where commit BW limit reached 580system.cpu.rob.rob_reads 3178186489 # The number of ROB reads 581system.cpu.rob.rob_writes 4973800859 # The number of ROB writes 582system.cpu.timesIdled 2058 # Number of times that the entire CPU went into an idle state and unscheduled itself 583system.cpu.idleCycles 149381 # Total number of cycles that the CPU has spent unscheduled due to idling | 591system.cpu.commit.bw_lim_events 73373032 # number cycles where commit BW limit reached 592system.cpu.rob.rob_reads 3187574492 # The number of ROB reads 593system.cpu.rob.rob_writes 4974168269 # The number of ROB writes 594system.cpu.timesIdled 2040 # Number of times that the entire CPU went into an idle state and unscheduled itself 595system.cpu.idleCycles 207174 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 584system.cpu.committedInsts 826847303 # Number of Instructions Simulated 585system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated | 596system.cpu.committedInsts 826847303 # Number of Instructions Simulated 597system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated |
| 586system.cpu.cpi 1.166798 # CPI: Cycles Per Instruction 587system.cpu.cpi_total 1.166798 # CPI: Total CPI of All Threads 588system.cpu.ipc 0.857046 # IPC: Instructions Per Cycle 589system.cpu.ipc_total 0.857046 # IPC: Total IPC of All Threads 590system.cpu.int_regfile_reads 2928420991 # number of integer regfile reads 591system.cpu.int_regfile_writes 1576721018 # number of integer regfile writes 592system.cpu.fp_regfile_reads 241306 # number of floating regfile reads 593system.cpu.fp_regfile_writes 1 # number of floating regfile writes 594system.cpu.cc_regfile_reads 617864492 # number of cc regfile reads 595system.cpu.cc_regfile_writes 419924545 # number of cc regfile writes 596system.cpu.misc_regfile_reads 1064270268 # number of misc regfile reads | 598system.cpu.cpi 1.178005 # CPI: Cycles Per Instruction 599system.cpu.cpi_total 1.178005 # CPI: Total CPI of All Threads 600system.cpu.ipc 0.848893 # IPC: Instructions Per Cycle 601system.cpu.ipc_total 0.848893 # IPC: Total IPC of All Threads 602system.cpu.int_regfile_reads 2928663805 # number of integer regfile reads 603system.cpu.int_regfile_writes 1576907134 # number of integer regfile writes 604system.cpu.fp_regfile_reads 239166 # number of floating regfile reads 605system.cpu.fp_regfile_writes 5 # number of floating regfile writes 606system.cpu.cc_regfile_reads 617952960 # number of cc regfile reads 607system.cpu.cc_regfile_writes 419967877 # number of cc regfile writes 608system.cpu.misc_regfile_reads 1064297744 # number of misc regfile reads |
| 597system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 609system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 598system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 599system.cpu.dcache.tags.replacements 2546182 # number of replacements 600system.cpu.dcache.tags.tagsinuse 4087.922606 # Cycle average of tags in use 601system.cpu.dcache.tags.total_refs 421485651 # Total number of references to valid blocks. 602system.cpu.dcache.tags.sampled_refs 2550278 # Sample count of references to valid blocks. 603system.cpu.dcache.tags.avg_refs 165.270473 # Average number of references to valid blocks. 604system.cpu.dcache.tags.warmup_cycle 1898151500 # Cycle when the warmup percentage was hit. 605system.cpu.dcache.tags.occ_blocks::cpu.data 4087.922606 # Average occupied blocks per requestor 606system.cpu.dcache.tags.occ_percent::cpu.data 0.998028 # Average percentage of cache occupancy 607system.cpu.dcache.tags.occ_percent::total 0.998028 # Average percentage of cache occupancy | 610system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 611system.cpu.dcache.tags.replacements 2546002 # number of replacements 612system.cpu.dcache.tags.tagsinuse 4087.987212 # Cycle average of tags in use 613system.cpu.dcache.tags.total_refs 420920584 # Total number of references to valid blocks. 614system.cpu.dcache.tags.sampled_refs 2550098 # Sample count of references to valid blocks. 615system.cpu.dcache.tags.avg_refs 165.060552 # Average number of references to valid blocks. 616system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. 617system.cpu.dcache.tags.occ_blocks::cpu.data 4087.987212 # Average occupied blocks per requestor 618system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy 619system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy |
| 608system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 609system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id | 620system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 621system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 622system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id |
| 611system.cpu.dcache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::3 3454 # Occupied blocks per task id | 623system.cpu.dcache.tags.age_task_id_blocks_1024::2 600 # Occupied blocks per task id 624system.cpu.dcache.tags.age_task_id_blocks_1024::3 3453 # Occupied blocks per task id |
| 613system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 614system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 625system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 626system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 615system.cpu.dcache.tags.tag_accesses 852234240 # Number of tag accesses 616system.cpu.dcache.tags.data_accesses 852234240 # Number of data accesses 617system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 618system.cpu.dcache.ReadReq_hits::cpu.data 273116230 # number of ReadReq hits 619system.cpu.dcache.ReadReq_hits::total 273116230 # number of ReadReq hits 620system.cpu.dcache.WriteReq_hits::cpu.data 148366946 # number of WriteReq hits 621system.cpu.dcache.WriteReq_hits::total 148366946 # number of WriteReq hits 622system.cpu.dcache.demand_hits::cpu.data 421483176 # number of demand (read+write) hits 623system.cpu.dcache.demand_hits::total 421483176 # number of demand (read+write) hits 624system.cpu.dcache.overall_hits::cpu.data 421483176 # number of overall hits 625system.cpu.dcache.overall_hits::total 421483176 # number of overall hits 626system.cpu.dcache.ReadReq_misses::cpu.data 2567540 # number of ReadReq misses 627system.cpu.dcache.ReadReq_misses::total 2567540 # number of ReadReq misses 628system.cpu.dcache.WriteReq_misses::cpu.data 791265 # number of WriteReq misses 629system.cpu.dcache.WriteReq_misses::total 791265 # number of WriteReq misses 630system.cpu.dcache.demand_misses::cpu.data 3358805 # number of demand (read+write) misses 631system.cpu.dcache.demand_misses::total 3358805 # number of demand (read+write) misses 632system.cpu.dcache.overall_misses::cpu.data 3358805 # number of overall misses 633system.cpu.dcache.overall_misses::total 3358805 # number of overall misses 634system.cpu.dcache.ReadReq_miss_latency::cpu.data 57574934000 # number of ReadReq miss cycles 635system.cpu.dcache.ReadReq_miss_latency::total 57574934000 # number of ReadReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::cpu.data 24743790498 # number of WriteReq miss cycles 637system.cpu.dcache.WriteReq_miss_latency::total 24743790498 # number of WriteReq miss cycles 638system.cpu.dcache.demand_miss_latency::cpu.data 82318724498 # number of demand (read+write) miss cycles 639system.cpu.dcache.demand_miss_latency::total 82318724498 # number of demand (read+write) miss cycles 640system.cpu.dcache.overall_miss_latency::cpu.data 82318724498 # number of overall miss cycles 641system.cpu.dcache.overall_miss_latency::total 82318724498 # number of overall miss cycles 642system.cpu.dcache.ReadReq_accesses::cpu.data 275683770 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.ReadReq_accesses::total 275683770 # number of ReadReq accesses(hits+misses) | 627system.cpu.dcache.tags.tag_accesses 851091222 # Number of tag accesses 628system.cpu.dcache.tags.data_accesses 851091222 # Number of data accesses 629system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 630system.cpu.dcache.ReadReq_hits::cpu.data 272551011 # number of ReadReq hits 631system.cpu.dcache.ReadReq_hits::total 272551011 # number of ReadReq hits 632system.cpu.dcache.WriteReq_hits::cpu.data 148366737 # number of WriteReq hits 633system.cpu.dcache.WriteReq_hits::total 148366737 # number of WriteReq hits 634system.cpu.dcache.demand_hits::cpu.data 420917748 # number of demand (read+write) hits 635system.cpu.dcache.demand_hits::total 420917748 # number of demand (read+write) hits 636system.cpu.dcache.overall_hits::cpu.data 420917748 # number of overall hits 637system.cpu.dcache.overall_hits::total 420917748 # number of overall hits 638system.cpu.dcache.ReadReq_misses::cpu.data 2561340 # number of ReadReq misses 639system.cpu.dcache.ReadReq_misses::total 2561340 # number of ReadReq misses 640system.cpu.dcache.WriteReq_misses::cpu.data 791474 # number of WriteReq misses 641system.cpu.dcache.WriteReq_misses::total 791474 # number of WriteReq misses 642system.cpu.dcache.demand_misses::cpu.data 3352814 # number of demand (read+write) misses 643system.cpu.dcache.demand_misses::total 3352814 # number of demand (read+write) misses 644system.cpu.dcache.overall_misses::cpu.data 3352814 # number of overall misses 645system.cpu.dcache.overall_misses::total 3352814 # number of overall misses 646system.cpu.dcache.ReadReq_miss_latency::cpu.data 63063270500 # number of ReadReq miss cycles 647system.cpu.dcache.ReadReq_miss_latency::total 63063270500 # number of ReadReq miss cycles 648system.cpu.dcache.WriteReq_miss_latency::cpu.data 26380612500 # number of WriteReq miss cycles 649system.cpu.dcache.WriteReq_miss_latency::total 26380612500 # number of WriteReq miss cycles 650system.cpu.dcache.demand_miss_latency::cpu.data 89443883000 # number of demand (read+write) miss cycles 651system.cpu.dcache.demand_miss_latency::total 89443883000 # number of demand (read+write) miss cycles 652system.cpu.dcache.overall_miss_latency::cpu.data 89443883000 # number of overall miss cycles 653system.cpu.dcache.overall_miss_latency::total 89443883000 # number of overall miss cycles 654system.cpu.dcache.ReadReq_accesses::cpu.data 275112351 # number of ReadReq accesses(hits+misses) 655system.cpu.dcache.ReadReq_accesses::total 275112351 # number of ReadReq accesses(hits+misses) |
| 644system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) | 656system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) 657system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) |
| 646system.cpu.dcache.demand_accesses::cpu.data 424841981 # number of demand (read+write) accesses 647system.cpu.dcache.demand_accesses::total 424841981 # number of demand (read+write) accesses 648system.cpu.dcache.overall_accesses::cpu.data 424841981 # number of overall (read+write) accesses 649system.cpu.dcache.overall_accesses::total 424841981 # number of overall (read+write) accesses 650system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009313 # miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_miss_rate::total 0.009313 # miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses 654system.cpu.dcache.demand_miss_rate::cpu.data 0.007906 # miss rate for demand accesses 655system.cpu.dcache.demand_miss_rate::total 0.007906 # miss rate for demand accesses 656system.cpu.dcache.overall_miss_rate::cpu.data 0.007906 # miss rate for overall accesses 657system.cpu.dcache.overall_miss_rate::total 0.007906 # miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428 # average ReadReq miss latency 659system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428 # average ReadReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323 # average WriteReq miss latency 661system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323 # average WriteReq miss latency 662system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency 663system.cpu.dcache.demand_avg_miss_latency::total 24508.336893 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency 665system.cpu.dcache.overall_avg_miss_latency::total 24508.336893 # average overall miss latency 666system.cpu.dcache.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked 667system.cpu.dcache.blocked_cycles::no_targets 1268 # number of cycles access was blocked 668system.cpu.dcache.blocked::no_mshrs 857 # number of cycles access was blocked 669system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked 670system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.301050 # average number of cycles each access was blocked 671system.cpu.dcache.avg_blocked_cycles::no_targets 105.666667 # average number of cycles each access was blocked 672system.cpu.dcache.writebacks::writebacks 2337859 # number of writebacks 673system.cpu.dcache.writebacks::total 2337859 # number of writebacks 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 801102 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 801102 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5848 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 5848 # number of WriteReq MSHR hits 678system.cpu.dcache.demand_mshr_hits::cpu.data 806950 # number of demand (read+write) MSHR hits 679system.cpu.dcache.demand_mshr_hits::total 806950 # number of demand (read+write) MSHR hits 680system.cpu.dcache.overall_mshr_hits::cpu.data 806950 # number of overall MSHR hits 681system.cpu.dcache.overall_mshr_hits::total 806950 # number of overall MSHR hits 682system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766438 # number of ReadReq MSHR misses 683system.cpu.dcache.ReadReq_mshr_misses::total 1766438 # number of ReadReq MSHR misses 684system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785417 # number of WriteReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::total 785417 # number of WriteReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.data 2551855 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 2551855 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 2551855 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 2551855 # number of overall MSHR misses 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33894644000 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 33894644000 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23857134999 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 23857134999 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57751778999 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::total 57751778999 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57751778999 # number of overall MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::total 57751778999 # number of overall MSHR miss cycles 698system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006407 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006407 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.006007 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.006007 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19188.131143 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19188.131143 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30375.119203 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30375.119203 # average WriteReq mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency 714system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 715system.cpu.icache.tags.replacements 4041 # number of replacements 716system.cpu.icache.tags.tagsinuse 1081.856161 # Cycle average of tags in use 717system.cpu.icache.tags.total_refs 216396902 # Total number of references to valid blocks. 718system.cpu.icache.tags.sampled_refs 5745 # Sample count of references to valid blocks. 719system.cpu.icache.tags.avg_refs 37666.997737 # Average number of references to valid blocks. | 658system.cpu.dcache.demand_accesses::cpu.data 424270562 # number of demand (read+write) accesses 659system.cpu.dcache.demand_accesses::total 424270562 # number of demand (read+write) accesses 660system.cpu.dcache.overall_accesses::cpu.data 424270562 # number of overall (read+write) accesses 661system.cpu.dcache.overall_accesses::total 424270562 # number of overall (read+write) accesses 662system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses 663system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses 664system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses 665system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses 666system.cpu.dcache.demand_miss_rate::cpu.data 0.007903 # miss rate for demand accesses 667system.cpu.dcache.demand_miss_rate::total 0.007903 # miss rate for demand accesses 668system.cpu.dcache.overall_miss_rate::cpu.data 0.007903 # miss rate for overall accesses 669system.cpu.dcache.overall_miss_rate::total 0.007903 # miss rate for overall accesses 670system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24621.202378 # average ReadReq miss latency 671system.cpu.dcache.ReadReq_avg_miss_latency::total 24621.202378 # average ReadReq miss latency 672system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33330.990658 # average WriteReq miss latency 673system.cpu.dcache.WriteReq_avg_miss_latency::total 33330.990658 # average WriteReq miss latency 674system.cpu.dcache.demand_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency 675system.cpu.dcache.demand_avg_miss_latency::total 26677.257671 # average overall miss latency 676system.cpu.dcache.overall_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency 677system.cpu.dcache.overall_avg_miss_latency::total 26677.257671 # average overall miss latency 678system.cpu.dcache.blocked_cycles::no_mshrs 10639 # number of cycles access was blocked 679system.cpu.dcache.blocked_cycles::no_targets 11942 # number of cycles access was blocked 680system.cpu.dcache.blocked::no_mshrs 928 # number of cycles access was blocked 681system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked 682system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.464440 # average number of cycles each access was blocked 683system.cpu.dcache.avg_blocked_cycles::no_targets 918.615385 # average number of cycles each access was blocked 684system.cpu.dcache.writebacks::writebacks 2338096 # number of writebacks 685system.cpu.dcache.writebacks::total 2338096 # number of writebacks 686system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794970 # number of ReadReq MSHR hits 687system.cpu.dcache.ReadReq_mshr_hits::total 794970 # number of ReadReq MSHR hits 688system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5921 # number of WriteReq MSHR hits 689system.cpu.dcache.WriteReq_mshr_hits::total 5921 # number of WriteReq MSHR hits 690system.cpu.dcache.demand_mshr_hits::cpu.data 800891 # number of demand (read+write) MSHR hits 691system.cpu.dcache.demand_mshr_hits::total 800891 # number of demand (read+write) MSHR hits 692system.cpu.dcache.overall_mshr_hits::cpu.data 800891 # number of overall MSHR hits 693system.cpu.dcache.overall_mshr_hits::total 800891 # number of overall MSHR hits 694system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766370 # number of ReadReq MSHR misses 695system.cpu.dcache.ReadReq_mshr_misses::total 1766370 # number of ReadReq MSHR misses 696system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785553 # number of WriteReq MSHR misses 697system.cpu.dcache.WriteReq_mshr_misses::total 785553 # number of WriteReq MSHR misses 698system.cpu.dcache.demand_mshr_misses::cpu.data 2551923 # number of demand (read+write) MSHR misses 699system.cpu.dcache.demand_mshr_misses::total 2551923 # number of demand (read+write) MSHR misses 700system.cpu.dcache.overall_mshr_misses::cpu.data 2551923 # number of overall MSHR misses 701system.cpu.dcache.overall_mshr_misses::total 2551923 # number of overall MSHR misses 702system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37596158000 # number of ReadReq MSHR miss cycles 703system.cpu.dcache.ReadReq_mshr_miss_latency::total 37596158000 # number of ReadReq MSHR miss cycles 704system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25486712000 # number of WriteReq MSHR miss cycles 705system.cpu.dcache.WriteReq_mshr_miss_latency::total 25486712000 # number of WriteReq MSHR miss cycles 706system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63082870000 # number of demand (read+write) MSHR miss cycles 707system.cpu.dcache.demand_mshr_miss_latency::total 63082870000 # number of demand (read+write) MSHR miss cycles 708system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63082870000 # number of overall MSHR miss cycles 709system.cpu.dcache.overall_mshr_miss_latency::total 63082870000 # number of overall MSHR miss cycles 710system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses 711system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses 713system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses 715system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses 716system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses 717system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses 718system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21284.418327 # average ReadReq mshr miss latency 719system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21284.418327 # average ReadReq mshr miss latency 720system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32444.293383 # average WriteReq mshr miss latency 721system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32444.293383 # average WriteReq mshr miss latency 722system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency 723system.cpu.dcache.demand_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency 724system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency 725system.cpu.dcache.overall_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency 726system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 727system.cpu.icache.tags.replacements 3937 # number of replacements 728system.cpu.icache.tags.tagsinuse 1075.833508 # Cycle average of tags in use 729system.cpu.icache.tags.total_refs 216367909 # Total number of references to valid blocks. 730system.cpu.icache.tags.sampled_refs 5646 # Sample count of references to valid blocks. 731system.cpu.icache.tags.avg_refs 38322.335990 # Average number of references to valid blocks. |
| 720system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 732system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 721system.cpu.icache.tags.occ_blocks::cpu.inst 1081.856161 # Average occupied blocks per requestor 722system.cpu.icache.tags.occ_percent::cpu.inst 0.528250 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_percent::total 0.528250 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_task_id_blocks::1024 1704 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id | 733system.cpu.icache.tags.occ_blocks::cpu.inst 1075.833508 # Average occupied blocks per requestor 734system.cpu.icache.tags.occ_percent::cpu.inst 0.525309 # Average percentage of cache occupancy 735system.cpu.icache.tags.occ_percent::total 0.525309 # Average percentage of cache occupancy 736system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id 737system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id |
| 726system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id | 738system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id |
| 727system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id | 739system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id |
| 728system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id | 740system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id |
| 729system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id 730system.cpu.icache.tags.occ_task_id_percent::1024 0.832031 # Percentage of cache occupancy per task id 731system.cpu.icache.tags.tag_accesses 432820961 # Number of tag accesses 732system.cpu.icache.tags.data_accesses 432820961 # Number of data accesses 733system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 734system.cpu.icache.ReadReq_hits::cpu.inst 216397172 # number of ReadReq hits 735system.cpu.icache.ReadReq_hits::total 216397172 # number of ReadReq hits 736system.cpu.icache.demand_hits::cpu.inst 216397172 # number of demand (read+write) hits 737system.cpu.icache.demand_hits::total 216397172 # number of demand (read+write) hits 738system.cpu.icache.overall_hits::cpu.inst 216397172 # number of overall hits 739system.cpu.icache.overall_hits::total 216397172 # number of overall hits 740system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses 741system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses 742system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses 743system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses 744system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses 745system.cpu.icache.overall_misses::total 9643 # number of overall misses 746system.cpu.icache.ReadReq_miss_latency::cpu.inst 354601499 # number of ReadReq miss cycles 747system.cpu.icache.ReadReq_miss_latency::total 354601499 # number of ReadReq miss cycles 748system.cpu.icache.demand_miss_latency::cpu.inst 354601499 # number of demand (read+write) miss cycles 749system.cpu.icache.demand_miss_latency::total 354601499 # number of demand (read+write) miss cycles 750system.cpu.icache.overall_miss_latency::cpu.inst 354601499 # number of overall miss cycles 751system.cpu.icache.overall_miss_latency::total 354601499 # number of overall miss cycles 752system.cpu.icache.ReadReq_accesses::cpu.inst 216406815 # number of ReadReq accesses(hits+misses) 753system.cpu.icache.ReadReq_accesses::total 216406815 # number of ReadReq accesses(hits+misses) 754system.cpu.icache.demand_accesses::cpu.inst 216406815 # number of demand (read+write) accesses 755system.cpu.icache.demand_accesses::total 216406815 # number of demand (read+write) accesses 756system.cpu.icache.overall_accesses::cpu.inst 216406815 # number of overall (read+write) accesses 757system.cpu.icache.overall_accesses::total 216406815 # number of overall (read+write) accesses | 741system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id 742system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id 743system.cpu.icache.tags.tag_accesses 432763508 # Number of tag accesses 744system.cpu.icache.tags.data_accesses 432763508 # Number of data accesses 745system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 746system.cpu.icache.ReadReq_hits::cpu.inst 216368192 # number of ReadReq hits 747system.cpu.icache.ReadReq_hits::total 216368192 # number of ReadReq hits 748system.cpu.icache.demand_hits::cpu.inst 216368192 # number of demand (read+write) hits 749system.cpu.icache.demand_hits::total 216368192 # number of demand (read+write) hits 750system.cpu.icache.overall_hits::cpu.inst 216368192 # number of overall hits 751system.cpu.icache.overall_hits::total 216368192 # number of overall hits 752system.cpu.icache.ReadReq_misses::cpu.inst 9822 # number of ReadReq misses 753system.cpu.icache.ReadReq_misses::total 9822 # number of ReadReq misses 754system.cpu.icache.demand_misses::cpu.inst 9822 # number of demand (read+write) misses 755system.cpu.icache.demand_misses::total 9822 # number of demand (read+write) misses 756system.cpu.icache.overall_misses::cpu.inst 9822 # number of overall misses 757system.cpu.icache.overall_misses::total 9822 # number of overall misses 758system.cpu.icache.ReadReq_miss_latency::cpu.inst 562018500 # number of ReadReq miss cycles 759system.cpu.icache.ReadReq_miss_latency::total 562018500 # number of ReadReq miss cycles 760system.cpu.icache.demand_miss_latency::cpu.inst 562018500 # number of demand (read+write) miss cycles 761system.cpu.icache.demand_miss_latency::total 562018500 # number of demand (read+write) miss cycles 762system.cpu.icache.overall_miss_latency::cpu.inst 562018500 # number of overall miss cycles 763system.cpu.icache.overall_miss_latency::total 562018500 # number of overall miss cycles 764system.cpu.icache.ReadReq_accesses::cpu.inst 216378014 # number of ReadReq accesses(hits+misses) 765system.cpu.icache.ReadReq_accesses::total 216378014 # number of ReadReq accesses(hits+misses) 766system.cpu.icache.demand_accesses::cpu.inst 216378014 # number of demand (read+write) accesses 767system.cpu.icache.demand_accesses::total 216378014 # number of demand (read+write) accesses 768system.cpu.icache.overall_accesses::cpu.inst 216378014 # number of overall (read+write) accesses 769system.cpu.icache.overall_accesses::total 216378014 # number of overall (read+write) accesses |
| 758system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 759system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 760system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 761system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 762system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 763system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses | 770system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 771system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 772system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 773system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 774system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 775system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses |
| 764system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36772.944001 # average ReadReq miss latency 765system.cpu.icache.ReadReq_avg_miss_latency::total 36772.944001 # average ReadReq miss latency 766system.cpu.icache.demand_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency 767system.cpu.icache.demand_avg_miss_latency::total 36772.944001 # average overall miss latency 768system.cpu.icache.overall_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency 769system.cpu.icache.overall_avg_miss_latency::total 36772.944001 # average overall miss latency 770system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked | 776system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57220.372633 # average ReadReq miss latency 777system.cpu.icache.ReadReq_avg_miss_latency::total 57220.372633 # average ReadReq miss latency 778system.cpu.icache.demand_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency 779system.cpu.icache.demand_avg_miss_latency::total 57220.372633 # average overall miss latency 780system.cpu.icache.overall_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency 781system.cpu.icache.overall_avg_miss_latency::total 57220.372633 # average overall miss latency 782system.cpu.icache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked |
| 771system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 783system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 772system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked | 784system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked |
| 773system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 785system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 774system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked | 786system.cpu.icache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked |
| 775system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 787system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 776system.cpu.icache.writebacks::writebacks 4041 # number of writebacks 777system.cpu.icache.writebacks::total 4041 # number of writebacks 778system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2312 # number of ReadReq MSHR hits 779system.cpu.icache.ReadReq_mshr_hits::total 2312 # number of ReadReq MSHR hits 780system.cpu.icache.demand_mshr_hits::cpu.inst 2312 # number of demand (read+write) MSHR hits 781system.cpu.icache.demand_mshr_hits::total 2312 # number of demand (read+write) MSHR hits 782system.cpu.icache.overall_mshr_hits::cpu.inst 2312 # number of overall MSHR hits 783system.cpu.icache.overall_mshr_hits::total 2312 # number of overall MSHR hits 784system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7331 # number of ReadReq MSHR misses 785system.cpu.icache.ReadReq_mshr_misses::total 7331 # number of ReadReq MSHR misses 786system.cpu.icache.demand_mshr_misses::cpu.inst 7331 # number of demand (read+write) MSHR misses 787system.cpu.icache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses 788system.cpu.icache.overall_mshr_misses::cpu.inst 7331 # number of overall MSHR misses 789system.cpu.icache.overall_mshr_misses::total 7331 # number of overall MSHR misses 790system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251236999 # number of ReadReq MSHR miss cycles 791system.cpu.icache.ReadReq_mshr_miss_latency::total 251236999 # number of ReadReq MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251236999 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::total 251236999 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251236999 # number of overall MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::total 251236999 # number of overall MSHR miss cycles 796system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses 797system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses 798system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses 799system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses 800system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses 801system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34270.495021 # average ReadReq mshr miss latency 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34270.495021 # average ReadReq mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34270.495021 # average overall mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34270.495021 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency 808system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 809system.cpu.l2cache.tags.replacements 356021 # number of replacements 810system.cpu.l2cache.tags.tagsinuse 30615.396519 # Cycle average of tags in use 811system.cpu.l2cache.tags.total_refs 4712767 # Total number of references to valid blocks. 812system.cpu.l2cache.tags.sampled_refs 388789 # Sample count of references to valid blocks. 813system.cpu.l2cache.tags.avg_refs 12.121657 # Average number of references to valid blocks. 814system.cpu.l2cache.tags.warmup_cycle 82695006000 # Cycle when the warmup percentage was hit. 815system.cpu.l2cache.tags.occ_blocks::writebacks 70.818761 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.778038 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.data 30348.799719 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_percent::writebacks 0.002161 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005975 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.data 0.926172 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::total 0.934308 # Average percentage of cache occupancy | 788system.cpu.icache.writebacks::writebacks 3937 # number of writebacks 789system.cpu.icache.writebacks::total 3937 # number of writebacks 790system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2342 # number of ReadReq MSHR hits 791system.cpu.icache.ReadReq_mshr_hits::total 2342 # number of ReadReq MSHR hits 792system.cpu.icache.demand_mshr_hits::cpu.inst 2342 # number of demand (read+write) MSHR hits 793system.cpu.icache.demand_mshr_hits::total 2342 # number of demand (read+write) MSHR hits 794system.cpu.icache.overall_mshr_hits::cpu.inst 2342 # number of overall MSHR hits 795system.cpu.icache.overall_mshr_hits::total 2342 # number of overall MSHR hits 796system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7480 # number of ReadReq MSHR misses 797system.cpu.icache.ReadReq_mshr_misses::total 7480 # number of ReadReq MSHR misses 798system.cpu.icache.demand_mshr_misses::cpu.inst 7480 # number of demand (read+write) MSHR misses 799system.cpu.icache.demand_mshr_misses::total 7480 # number of demand (read+write) MSHR misses 800system.cpu.icache.overall_mshr_misses::cpu.inst 7480 # number of overall MSHR misses 801system.cpu.icache.overall_mshr_misses::total 7480 # number of overall MSHR misses 802system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 378895000 # number of ReadReq MSHR miss cycles 803system.cpu.icache.ReadReq_mshr_miss_latency::total 378895000 # number of ReadReq MSHR miss cycles 804system.cpu.icache.demand_mshr_miss_latency::cpu.inst 378895000 # number of demand (read+write) MSHR miss cycles 805system.cpu.icache.demand_mshr_miss_latency::total 378895000 # number of demand (read+write) MSHR miss cycles 806system.cpu.icache.overall_mshr_miss_latency::cpu.inst 378895000 # number of overall MSHR miss cycles 807system.cpu.icache.overall_mshr_miss_latency::total 378895000 # number of overall MSHR miss cycles 808system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for ReadReq accesses 809system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000035 # mshr miss rate for ReadReq accesses 810system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for demand accesses 811system.cpu.icache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses 812system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for overall accesses 813system.cpu.icache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses 814system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50654.411765 # average ReadReq mshr miss latency 815system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50654.411765 # average ReadReq mshr miss latency 816system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency 817system.cpu.icache.demand_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency 818system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency 819system.cpu.icache.overall_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency 820system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 821system.cpu.l2cache.tags.replacements 355911 # number of replacements 822system.cpu.l2cache.tags.tagsinuse 30630.560827 # Cycle average of tags in use 823system.cpu.l2cache.tags.total_refs 4712762 # Total number of references to valid blocks. 824system.cpu.l2cache.tags.sampled_refs 388679 # Sample count of references to valid blocks. 825system.cpu.l2cache.tags.avg_refs 12.125075 # Average number of references to valid blocks. 826system.cpu.l2cache.tags.warmup_cycle 82947046000 # Cycle when the warmup percentage was hit. 827system.cpu.l2cache.tags.occ_blocks::writebacks 71.927824 # Average occupied blocks per requestor 828system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.909939 # Average occupied blocks per requestor 829system.cpu.l2cache.tags.occ_blocks::cpu.data 30366.723064 # Average occupied blocks per requestor 830system.cpu.l2cache.tags.occ_percent::writebacks 0.002195 # Average percentage of cache occupancy 831system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005857 # Average percentage of cache occupancy 832system.cpu.l2cache.tags.occ_percent::cpu.data 0.926719 # Average percentage of cache occupancy 833system.cpu.l2cache.tags.occ_percent::total 0.934771 # Average percentage of cache occupancy |
| 822system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id | 834system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id |
| 823system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::2 165 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31150 # Occupied blocks per task id | 835system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 836system.cpu.l2cache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id 837system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1402 # Occupied blocks per task id 838system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31132 # Occupied blocks per task id |
| 828system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 839system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 829system.cpu.l2cache.tags.tag_accesses 41201341 # Number of tag accesses 830system.cpu.l2cache.tags.data_accesses 41201341 # Number of data accesses 831system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 832system.cpu.l2cache.WritebackDirty_hits::writebacks 2337859 # number of WritebackDirty hits 833system.cpu.l2cache.WritebackDirty_hits::total 2337859 # number of WritebackDirty hits 834system.cpu.l2cache.WritebackClean_hits::writebacks 3935 # number of WritebackClean hits 835system.cpu.l2cache.WritebackClean_hits::total 3935 # number of WritebackClean hits 836system.cpu.l2cache.UpgradeReq_hits::cpu.data 1572 # number of UpgradeReq hits 837system.cpu.l2cache.UpgradeReq_hits::total 1572 # number of UpgradeReq hits 838system.cpu.l2cache.ReadExReq_hits::cpu.data 577284 # number of ReadExReq hits 839system.cpu.l2cache.ReadExReq_hits::total 577284 # number of ReadExReq hits 840system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3232 # number of ReadCleanReq hits 841system.cpu.l2cache.ReadCleanReq_hits::total 3232 # number of ReadCleanReq hits 842system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587825 # number of ReadSharedReq hits 843system.cpu.l2cache.ReadSharedReq_hits::total 1587825 # number of ReadSharedReq hits 844system.cpu.l2cache.demand_hits::cpu.inst 3232 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::cpu.data 2165109 # number of demand (read+write) hits 846system.cpu.l2cache.demand_hits::total 2168341 # number of demand (read+write) hits 847system.cpu.l2cache.overall_hits::cpu.inst 3232 # number of overall hits 848system.cpu.l2cache.overall_hits::cpu.data 2165109 # number of overall hits 849system.cpu.l2cache.overall_hits::total 2168341 # number of overall hits | 840system.cpu.l2cache.tags.tag_accesses 41200319 # Number of tag accesses 841system.cpu.l2cache.tags.data_accesses 41200319 # Number of data accesses 842system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 843system.cpu.l2cache.WritebackDirty_hits::writebacks 2338096 # number of WritebackDirty hits 844system.cpu.l2cache.WritebackDirty_hits::total 2338096 # number of WritebackDirty hits 845system.cpu.l2cache.WritebackClean_hits::writebacks 3847 # number of WritebackClean hits 846system.cpu.l2cache.WritebackClean_hits::total 3847 # number of WritebackClean hits 847system.cpu.l2cache.UpgradeReq_hits::cpu.data 1820 # number of UpgradeReq hits 848system.cpu.l2cache.UpgradeReq_hits::total 1820 # number of UpgradeReq hits 849system.cpu.l2cache.ReadExReq_hits::cpu.data 577163 # number of ReadExReq hits 850system.cpu.l2cache.ReadExReq_hits::total 577163 # number of ReadExReq hits 851system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3171 # number of ReadCleanReq hits 852system.cpu.l2cache.ReadCleanReq_hits::total 3171 # number of ReadCleanReq hits 853system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587839 # number of ReadSharedReq hits 854system.cpu.l2cache.ReadSharedReq_hits::total 1587839 # number of ReadSharedReq hits 855system.cpu.l2cache.demand_hits::cpu.inst 3171 # number of demand (read+write) hits 856system.cpu.l2cache.demand_hits::cpu.data 2165002 # number of demand (read+write) hits 857system.cpu.l2cache.demand_hits::total 2168173 # number of demand (read+write) hits 858system.cpu.l2cache.overall_hits::cpu.inst 3171 # number of overall hits 859system.cpu.l2cache.overall_hits::cpu.data 2165002 # number of overall hits 860system.cpu.l2cache.overall_hits::total 2168173 # number of overall hits |
| 850system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 851system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses | 861system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 862system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses |
| 852system.cpu.l2cache.ReadExReq_misses::cpu.data 206802 # number of ReadExReq misses 853system.cpu.l2cache.ReadExReq_misses::total 206802 # number of ReadExReq misses 854system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2424 # number of ReadCleanReq misses 855system.cpu.l2cache.ReadCleanReq_misses::total 2424 # number of ReadCleanReq misses 856system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178367 # number of ReadSharedReq misses 857system.cpu.l2cache.ReadSharedReq_misses::total 178367 # number of ReadSharedReq misses 858system.cpu.l2cache.demand_misses::cpu.inst 2424 # number of demand (read+write) misses 859system.cpu.l2cache.demand_misses::cpu.data 385169 # number of demand (read+write) misses 860system.cpu.l2cache.demand_misses::total 387593 # number of demand (read+write) misses 861system.cpu.l2cache.overall_misses::cpu.inst 2424 # number of overall misses 862system.cpu.l2cache.overall_misses::cpu.data 385169 # number of overall misses 863system.cpu.l2cache.overall_misses::total 387593 # number of overall misses 864system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 61000 # number of UpgradeReq miss cycles 865system.cpu.l2cache.UpgradeReq_miss_latency::total 61000 # number of UpgradeReq miss cycles 866system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16603167500 # number of ReadExReq miss cycles 867system.cpu.l2cache.ReadExReq_miss_latency::total 16603167500 # number of ReadExReq miss cycles 868system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 203550000 # number of ReadCleanReq miss cycles 869system.cpu.l2cache.ReadCleanReq_miss_latency::total 203550000 # number of ReadCleanReq miss cycles 870system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14526809000 # number of ReadSharedReq miss cycles 871system.cpu.l2cache.ReadSharedReq_miss_latency::total 14526809000 # number of ReadSharedReq miss cycles 872system.cpu.l2cache.demand_miss_latency::cpu.inst 203550000 # number of demand (read+write) miss cycles 873system.cpu.l2cache.demand_miss_latency::cpu.data 31129976500 # number of demand (read+write) miss cycles 874system.cpu.l2cache.demand_miss_latency::total 31333526500 # number of demand (read+write) miss cycles 875system.cpu.l2cache.overall_miss_latency::cpu.inst 203550000 # number of overall miss cycles 876system.cpu.l2cache.overall_miss_latency::cpu.data 31129976500 # number of overall miss cycles 877system.cpu.l2cache.overall_miss_latency::total 31333526500 # number of overall miss cycles 878system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337859 # number of WritebackDirty accesses(hits+misses) 879system.cpu.l2cache.WritebackDirty_accesses::total 2337859 # number of WritebackDirty accesses(hits+misses) 880system.cpu.l2cache.WritebackClean_accesses::writebacks 3935 # number of WritebackClean accesses(hits+misses) 881system.cpu.l2cache.WritebackClean_accesses::total 3935 # number of WritebackClean accesses(hits+misses) 882system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1577 # number of UpgradeReq accesses(hits+misses) 883system.cpu.l2cache.UpgradeReq_accesses::total 1577 # number of UpgradeReq accesses(hits+misses) 884system.cpu.l2cache.ReadExReq_accesses::cpu.data 784086 # number of ReadExReq accesses(hits+misses) 885system.cpu.l2cache.ReadExReq_accesses::total 784086 # number of ReadExReq accesses(hits+misses) 886system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5656 # number of ReadCleanReq accesses(hits+misses) 887system.cpu.l2cache.ReadCleanReq_accesses::total 5656 # number of ReadCleanReq accesses(hits+misses) 888system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766192 # number of ReadSharedReq accesses(hits+misses) 889system.cpu.l2cache.ReadSharedReq_accesses::total 1766192 # number of ReadSharedReq accesses(hits+misses) 890system.cpu.l2cache.demand_accesses::cpu.inst 5656 # number of demand (read+write) accesses 891system.cpu.l2cache.demand_accesses::cpu.data 2550278 # number of demand (read+write) accesses 892system.cpu.l2cache.demand_accesses::total 2555934 # number of demand (read+write) accesses 893system.cpu.l2cache.overall_accesses::cpu.inst 5656 # number of overall (read+write) accesses 894system.cpu.l2cache.overall_accesses::cpu.data 2550278 # number of overall (read+write) accesses 895system.cpu.l2cache.overall_accesses::total 2555934 # number of overall (read+write) accesses 896system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003171 # miss rate for UpgradeReq accesses 897system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003171 # miss rate for UpgradeReq accesses 898system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263749 # miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadExReq_miss_rate::total 0.263749 # miss rate for ReadExReq accesses 900system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.428571 # miss rate for ReadCleanReq accesses 901system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.428571 # miss rate for ReadCleanReq accesses 902system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100990 # miss rate for ReadSharedReq accesses 903system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100990 # miss rate for ReadSharedReq accesses 904system.cpu.l2cache.demand_miss_rate::cpu.inst 0.428571 # miss rate for demand accesses 905system.cpu.l2cache.demand_miss_rate::cpu.data 0.151030 # miss rate for demand accesses 906system.cpu.l2cache.demand_miss_rate::total 0.151644 # miss rate for demand accesses 907system.cpu.l2cache.overall_miss_rate::cpu.inst 0.428571 # miss rate for overall accesses 908system.cpu.l2cache.overall_miss_rate::cpu.data 0.151030 # miss rate for overall accesses 909system.cpu.l2cache.overall_miss_rate::total 0.151644 # miss rate for overall accesses 910system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12200 # average UpgradeReq miss latency 911system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12200 # average UpgradeReq miss latency 912system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80285.333314 # average ReadExReq miss latency 913system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80285.333314 # average ReadExReq miss latency 914system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83972.772277 # average ReadCleanReq miss latency 915system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83972.772277 # average ReadCleanReq miss latency 916system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81443.366766 # average ReadSharedReq miss latency 917system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81443.366766 # average ReadSharedReq miss latency 918system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83972.772277 # average overall miss latency 919system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80821.604283 # average overall miss latency 920system.cpu.l2cache.demand_avg_miss_latency::total 80841.311634 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83972.772277 # average overall miss latency 922system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80821.604283 # average overall miss latency 923system.cpu.l2cache.overall_avg_miss_latency::total 80841.311634 # average overall miss latency | 863system.cpu.l2cache.ReadExReq_misses::cpu.data 206795 # number of ReadExReq misses 864system.cpu.l2cache.ReadExReq_misses::total 206795 # number of ReadExReq misses 865system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2409 # number of ReadCleanReq misses 866system.cpu.l2cache.ReadCleanReq_misses::total 2409 # number of ReadCleanReq misses 867system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178301 # number of ReadSharedReq misses 868system.cpu.l2cache.ReadSharedReq_misses::total 178301 # number of ReadSharedReq misses 869system.cpu.l2cache.demand_misses::cpu.inst 2409 # number of demand (read+write) misses 870system.cpu.l2cache.demand_misses::cpu.data 385096 # number of demand (read+write) misses 871system.cpu.l2cache.demand_misses::total 387505 # number of demand (read+write) misses 872system.cpu.l2cache.overall_misses::cpu.inst 2409 # number of overall misses 873system.cpu.l2cache.overall_misses::cpu.data 385096 # number of overall misses 874system.cpu.l2cache.overall_misses::total 387505 # number of overall misses 875system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 # number of UpgradeReq miss cycles 876system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 # number of UpgradeReq miss cycles 877system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18229359500 # number of ReadExReq miss cycles 878system.cpu.l2cache.ReadExReq_miss_latency::total 18229359500 # number of ReadExReq miss cycles 879system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 331268000 # number of ReadCleanReq miss cycles 880system.cpu.l2cache.ReadCleanReq_miss_latency::total 331268000 # number of ReadCleanReq miss cycles 881system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18228771500 # number of ReadSharedReq miss cycles 882system.cpu.l2cache.ReadSharedReq_miss_latency::total 18228771500 # number of ReadSharedReq miss cycles 883system.cpu.l2cache.demand_miss_latency::cpu.inst 331268000 # number of demand (read+write) miss cycles 884system.cpu.l2cache.demand_miss_latency::cpu.data 36458131000 # number of demand (read+write) miss cycles 885system.cpu.l2cache.demand_miss_latency::total 36789399000 # number of demand (read+write) miss cycles 886system.cpu.l2cache.overall_miss_latency::cpu.inst 331268000 # number of overall miss cycles 887system.cpu.l2cache.overall_miss_latency::cpu.data 36458131000 # number of overall miss cycles 888system.cpu.l2cache.overall_miss_latency::total 36789399000 # number of overall miss cycles 889system.cpu.l2cache.WritebackDirty_accesses::writebacks 2338096 # number of WritebackDirty accesses(hits+misses) 890system.cpu.l2cache.WritebackDirty_accesses::total 2338096 # number of WritebackDirty accesses(hits+misses) 891system.cpu.l2cache.WritebackClean_accesses::writebacks 3847 # number of WritebackClean accesses(hits+misses) 892system.cpu.l2cache.WritebackClean_accesses::total 3847 # number of WritebackClean accesses(hits+misses) 893system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 894system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) 895system.cpu.l2cache.ReadExReq_accesses::cpu.data 783958 # number of ReadExReq accesses(hits+misses) 896system.cpu.l2cache.ReadExReq_accesses::total 783958 # number of ReadExReq accesses(hits+misses) 897system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5580 # number of ReadCleanReq accesses(hits+misses) 898system.cpu.l2cache.ReadCleanReq_accesses::total 5580 # number of ReadCleanReq accesses(hits+misses) 899system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766140 # number of ReadSharedReq accesses(hits+misses) 900system.cpu.l2cache.ReadSharedReq_accesses::total 1766140 # number of ReadSharedReq accesses(hits+misses) 901system.cpu.l2cache.demand_accesses::cpu.inst 5580 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::cpu.data 2550098 # number of demand (read+write) accesses 903system.cpu.l2cache.demand_accesses::total 2555678 # number of demand (read+write) accesses 904system.cpu.l2cache.overall_accesses::cpu.inst 5580 # number of overall (read+write) accesses 905system.cpu.l2cache.overall_accesses::cpu.data 2550098 # number of overall (read+write) accesses 906system.cpu.l2cache.overall_accesses::total 2555678 # number of overall (read+write) accesses 907system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002740 # miss rate for UpgradeReq accesses 908system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002740 # miss rate for UpgradeReq accesses 909system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263783 # miss rate for ReadExReq accesses 910system.cpu.l2cache.ReadExReq_miss_rate::total 0.263783 # miss rate for ReadExReq accesses 911system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.431720 # miss rate for ReadCleanReq accesses 912system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.431720 # miss rate for ReadCleanReq accesses 913system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100955 # miss rate for ReadSharedReq accesses 914system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100955 # miss rate for ReadSharedReq accesses 915system.cpu.l2cache.demand_miss_rate::cpu.inst 0.431720 # miss rate for demand accesses 916system.cpu.l2cache.demand_miss_rate::cpu.data 0.151012 # miss rate for demand accesses 917system.cpu.l2cache.demand_miss_rate::total 0.151625 # miss rate for demand accesses 918system.cpu.l2cache.overall_miss_rate::cpu.inst 0.431720 # miss rate for overall accesses 919system.cpu.l2cache.overall_miss_rate::cpu.data 0.151012 # miss rate for overall accesses 920system.cpu.l2cache.overall_miss_rate::total 0.151625 # miss rate for overall accesses 921system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6100 # average UpgradeReq miss latency 922system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6100 # average UpgradeReq miss latency 923system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88151.838778 # average ReadExReq miss latency 924system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88151.838778 # average ReadExReq miss latency 925system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 137512.660855 # average ReadCleanReq miss latency 926system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 137512.660855 # average ReadCleanReq miss latency 927system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102235.946517 # average ReadSharedReq miss latency 928system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102235.946517 # average ReadSharedReq miss latency 929system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 137512.660855 # average overall miss latency 930system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94672.837422 # average overall miss latency 931system.cpu.l2cache.demand_avg_miss_latency::total 94939.159495 # average overall miss latency 932system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 137512.660855 # average overall miss latency 933system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94672.837422 # average overall miss latency 934system.cpu.l2cache.overall_avg_miss_latency::total 94939.159495 # average overall miss latency |
| 924system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 925system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 926system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 927system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 928system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 929system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 935system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 936system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 937system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 938system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 939system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 940system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 930system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks 931system.cpu.l2cache.writebacks::total 295491 # number of writebacks | 941system.cpu.l2cache.writebacks::writebacks 295435 # number of writebacks 942system.cpu.l2cache.writebacks::total 295435 # number of writebacks |
| 932system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 933system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 934system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 935system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses | 943system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 944system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 945system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 946system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses |
| 936system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206802 # number of ReadExReq MSHR misses 937system.cpu.l2cache.ReadExReq_mshr_misses::total 206802 # number of ReadExReq MSHR misses 938system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2424 # number of ReadCleanReq MSHR misses 939system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2424 # number of ReadCleanReq MSHR misses 940system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178367 # number of ReadSharedReq MSHR misses 941system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178367 # number of ReadSharedReq MSHR misses 942system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses 943system.cpu.l2cache.demand_mshr_misses::cpu.data 385169 # number of demand (read+write) MSHR misses 944system.cpu.l2cache.demand_mshr_misses::total 387593 # number of demand (read+write) MSHR misses 945system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses 946system.cpu.l2cache.overall_mshr_misses::cpu.data 385169 # number of overall MSHR misses 947system.cpu.l2cache.overall_mshr_misses::total 387593 # number of overall MSHR misses | 947system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206795 # number of ReadExReq MSHR misses 948system.cpu.l2cache.ReadExReq_mshr_misses::total 206795 # number of ReadExReq MSHR misses 949system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2409 # number of ReadCleanReq MSHR misses 950system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2409 # number of ReadCleanReq MSHR misses 951system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178301 # number of ReadSharedReq MSHR misses 952system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178301 # number of ReadSharedReq MSHR misses 953system.cpu.l2cache.demand_mshr_misses::cpu.inst 2409 # number of demand (read+write) MSHR misses 954system.cpu.l2cache.demand_mshr_misses::cpu.data 385096 # number of demand (read+write) MSHR misses 955system.cpu.l2cache.demand_mshr_misses::total 387505 # number of demand (read+write) MSHR misses 956system.cpu.l2cache.overall_mshr_misses::cpu.inst 2409 # number of overall MSHR misses 957system.cpu.l2cache.overall_mshr_misses::cpu.data 385096 # number of overall MSHR misses 958system.cpu.l2cache.overall_mshr_misses::total 387505 # number of overall MSHR misses |
| 948system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles 949system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles | 959system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles 960system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles |
| 950system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14535147500 # number of ReadExReq MSHR miss cycles 951system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14535147500 # number of ReadExReq MSHR miss cycles 952system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179310000 # number of ReadCleanReq MSHR miss cycles 953system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179310000 # number of ReadCleanReq MSHR miss cycles 954system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12743139000 # number of ReadSharedReq MSHR miss cycles 955system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12743139000 # number of ReadSharedReq MSHR miss cycles 956system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179310000 # number of demand (read+write) MSHR miss cycles 957system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27278286500 # number of demand (read+write) MSHR miss cycles 958system.cpu.l2cache.demand_mshr_miss_latency::total 27457596500 # number of demand (read+write) MSHR miss cycles 959system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179310000 # number of overall MSHR miss cycles 960system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27278286500 # number of overall MSHR miss cycles 961system.cpu.l2cache.overall_mshr_miss_latency::total 27457596500 # number of overall MSHR miss cycles | 961system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16161409500 # number of ReadExReq MSHR miss cycles 962system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16161409500 # number of ReadExReq MSHR miss cycles 963system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307178000 # number of ReadCleanReq MSHR miss cycles 964system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307178000 # number of ReadCleanReq MSHR miss cycles 965system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16445761500 # number of ReadSharedReq MSHR miss cycles 966system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16445761500 # number of ReadSharedReq MSHR miss cycles 967system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307178000 # number of demand (read+write) MSHR miss cycles 968system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32607171000 # number of demand (read+write) MSHR miss cycles 969system.cpu.l2cache.demand_mshr_miss_latency::total 32914349000 # number of demand (read+write) MSHR miss cycles 970system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307178000 # number of overall MSHR miss cycles 971system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32607171000 # number of overall MSHR miss cycles 972system.cpu.l2cache.overall_mshr_miss_latency::total 32914349000 # number of overall MSHR miss cycles |
| 962system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 963system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 973system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 974system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 964system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for UpgradeReq accesses 965system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003171 # mshr miss rate for UpgradeReq accesses 966system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263749 # mshr miss rate for ReadExReq accesses 967system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263749 # mshr miss rate for ReadExReq accesses 968system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for ReadCleanReq accesses 969system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428571 # mshr miss rate for ReadCleanReq accesses 970system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100990 # mshr miss rate for ReadSharedReq accesses 971system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100990 # mshr miss rate for ReadSharedReq accesses 972system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for demand accesses 973system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for demand accesses 974system.cpu.l2cache.demand_mshr_miss_rate::total 0.151644 # mshr miss rate for demand accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for overall accesses 977system.cpu.l2cache.overall_mshr_miss_rate::total 0.151644 # mshr miss rate for overall accesses | 975system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002740 # mshr miss rate for UpgradeReq accesses 976system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002740 # mshr miss rate for UpgradeReq accesses 977system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263783 # mshr miss rate for ReadExReq accesses 978system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263783 # mshr miss rate for ReadExReq accesses 979system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for ReadCleanReq accesses 980system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.431720 # mshr miss rate for ReadCleanReq accesses 981system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100955 # mshr miss rate for ReadSharedReq accesses 982system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100955 # mshr miss rate for ReadSharedReq accesses 983system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for demand accesses 984system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for demand accesses 985system.cpu.l2cache.demand_mshr_miss_rate::total 0.151625 # mshr miss rate for demand accesses 986system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for overall accesses 987system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for overall accesses 988system.cpu.l2cache.overall_mshr_miss_rate::total 0.151625 # mshr miss rate for overall accesses |
| 978system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency 979system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency | 989system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency 990system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency |
| 980system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70285.333314 # average ReadExReq mshr miss latency 981system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70285.333314 # average ReadExReq mshr miss latency 982system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73972.772277 # average ReadCleanReq mshr miss latency 983system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73972.772277 # average ReadCleanReq mshr miss latency 984system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766 # average ReadSharedReq mshr miss latency 985system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766 # average ReadSharedReq mshr miss latency 986system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency 987system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency 988system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency 989system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency 990system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency 991system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency 992system.cpu.toL2Bus.snoop_filter.tot_requests 5109409 # Total number of requests made to the snoop filter. 993system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551871 # Number of requests hitting in the snoop filter with a single holder of the requested data. 994system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7932 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 995system.cpu.toL2Bus.snoop_filter.tot_snoops 2949 # Total number of snoops made to the snoop filter. 996system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 991system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78151.838778 # average ReadExReq mshr miss latency 992system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78151.838778 # average ReadExReq mshr miss latency 993system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 127512.660855 # average ReadCleanReq mshr miss latency 994system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 127512.660855 # average ReadCleanReq mshr miss latency 995system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517 # average ReadSharedReq mshr miss latency 996system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517 # average ReadSharedReq mshr miss latency 997system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency 998system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency 999system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency 1000system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency 1001system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency 1002system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency 1003system.cpu.toL2Bus.snoop_filter.tot_requests 5109342 # Total number of requests made to the snoop filter. 1004system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551824 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1005system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1006system.cpu.toL2Bus.snoop_filter.tot_snoops 2956 # Total number of snoops made to the snoop filter. 1007system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 997system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1008system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 998system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 999system.cpu.toL2Bus.trans_dist::ReadResp 1773523 # Transaction distribution 1000system.cpu.toL2Bus.trans_dist::WritebackDirty 2633350 # Transaction distribution 1001system.cpu.toL2Bus.trans_dist::WritebackClean 4041 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::CleanEvict 268853 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::UpgradeReq 1577 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::UpgradeResp 1577 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::ReadExReq 784086 # Transaction distribution 1006system.cpu.toL2Bus.trans_dist::ReadExResp 784086 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::ReadCleanReq 7331 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766192 # Transaction distribution 1009system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17028 # Packet count per connected master and slave (bytes) 1010system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649892 # Packet count per connected master and slave (bytes) 1011system.cpu.toL2Bus.pkt_count::total 7666920 # Packet count per connected master and slave (bytes) 1012system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 620608 # Cumulative packet size per connected master and slave (bytes) 1013system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312840768 # Cumulative packet size per connected master and slave (bytes) 1014system.cpu.toL2Bus.pkt_size::total 313461376 # Cumulative packet size per connected master and slave (bytes) 1015system.cpu.toL2Bus.snoops 357696 # Total snoops (count) 1016system.cpu.toL2Bus.snoopTraffic 19018624 # Total snoop traffic (bytes) 1017system.cpu.toL2Bus.snoop_fanout::samples 2915207 # Request fanout histogram 1018system.cpu.toL2Bus.snoop_fanout::mean 0.004295 # Request fanout histogram 1019system.cpu.toL2Bus.snoop_fanout::stdev 0.065414 # Request fanout histogram | 1009system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 1010system.cpu.toL2Bus.trans_dist::ReadResp 1773620 # Transaction distribution 1011system.cpu.toL2Bus.trans_dist::WritebackDirty 2633531 # Transaction distribution 1012system.cpu.toL2Bus.trans_dist::WritebackClean 3937 # Transaction distribution 1013system.cpu.toL2Bus.trans_dist::CleanEvict 268382 # Transaction distribution 1014system.cpu.toL2Bus.trans_dist::UpgradeReq 1825 # Transaction distribution 1015system.cpu.toL2Bus.trans_dist::UpgradeResp 1825 # Transaction distribution 1016system.cpu.toL2Bus.trans_dist::ReadExReq 783958 # Transaction distribution 1017system.cpu.toL2Bus.trans_dist::ReadExResp 783958 # Transaction distribution 1018system.cpu.toL2Bus.trans_dist::ReadCleanReq 7480 # Transaction distribution 1019system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766140 # Transaction distribution 1020system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16997 # Packet count per connected master and slave (bytes) 1021system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649848 # Packet count per connected master and slave (bytes) 1022system.cpu.toL2Bus.pkt_count::total 7666845 # Packet count per connected master and slave (bytes) 1023system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609088 # Cumulative packet size per connected master and slave (bytes) 1024system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312844416 # Cumulative packet size per connected master and slave (bytes) 1025system.cpu.toL2Bus.pkt_size::total 313453504 # Cumulative packet size per connected master and slave (bytes) 1026system.cpu.toL2Bus.snoops 357811 # Total snoops (count) 1027system.cpu.toL2Bus.snoopTraffic 19029440 # Total snoop traffic (bytes) 1028system.cpu.toL2Bus.snoop_fanout::samples 2915314 # Request fanout histogram 1029system.cpu.toL2Bus.snoop_fanout::mean 0.004397 # Request fanout histogram 1030system.cpu.toL2Bus.snoop_fanout::stdev 0.066180 # Request fanout histogram |
| 1020system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1031system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1021system.cpu.toL2Bus.snoop_fanout::0 2902688 99.57% 99.57% # Request fanout histogram 1022system.cpu.toL2Bus.snoop_fanout::1 12516 0.43% 100.00% # Request fanout histogram | 1032system.cpu.toL2Bus.snoop_fanout::0 2902498 99.56% 99.56% # Request fanout histogram 1033system.cpu.toL2Bus.snoop_fanout::1 12813 0.44% 100.00% # Request fanout histogram |
| 1023system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 1024system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1025system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1026system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1034system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 1035system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1036system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1037system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1027system.cpu.toL2Bus.snoop_fanout::total 2915207 # Request fanout histogram 1028system.cpu.toL2Bus.reqLayer0.occupancy 4896659390 # Layer occupancy (ticks) | 1038system.cpu.toL2Bus.snoop_fanout::total 2915314 # Request fanout histogram 1039system.cpu.toL2Bus.reqLayer0.occupancy 4896765876 # Layer occupancy (ticks) |
| 1029system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) | 1040system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 1030system.cpu.toL2Bus.respLayer0.occupancy 10998496 # Layer occupancy (ticks) | 1041system.cpu.toL2Bus.respLayer0.occupancy 11220998 # Layer occupancy (ticks) |
| 1031system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1042system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1032system.cpu.toL2Bus.respLayer1.occupancy 3826206608 # Layer occupancy (ticks) | 1043system.cpu.toL2Bus.respLayer1.occupancy 3826059624 # Layer occupancy (ticks) |
| 1033system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | 1044system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 1034system.membus.snoop_filter.tot_requests 740700 # Total number of requests made to the snoop filter. 1035system.membus.snoop_filter.hit_single_requests 353605 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1045system.membus.snoop_filter.tot_requests 740486 # Total number of requests made to the snoop filter. 1046system.membus.snoop_filter.hit_single_requests 353479 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1036system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1037system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1038system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1039system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1047system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1048system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1049system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1050system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1040system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states 1041system.membus.trans_dist::ReadResp 180791 # Transaction distribution 1042system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution 1043system.membus.trans_dist::CleanEvict 57611 # Transaction distribution 1044system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1045system.membus.trans_dist::ReadExReq 206801 # Transaction distribution 1046system.membus.trans_dist::ReadExResp 206801 # Transaction distribution 1047system.membus.trans_dist::ReadSharedReq 180791 # Transaction distribution 1048system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128292 # Packet count per connected master and slave (bytes) 1049system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128292 # Packet count per connected master and slave (bytes) 1050system.membus.pkt_count::total 1128292 # Packet count per connected master and slave (bytes) 1051system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43717312 # Cumulative packet size per connected master and slave (bytes) 1052system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43717312 # Cumulative packet size per connected master and slave (bytes) 1053system.membus.pkt_size::total 43717312 # Cumulative packet size per connected master and slave (bytes) | 1051system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states 1052system.membus.trans_dist::ReadResp 180710 # Transaction distribution 1053system.membus.trans_dist::WritebackDirty 295435 # Transaction distribution 1054system.membus.trans_dist::CleanEvict 57541 # Transaction distribution 1055system.membus.trans_dist::UpgradeReq 8 # Transaction distribution 1056system.membus.trans_dist::ReadExReq 206792 # Transaction distribution 1057system.membus.trans_dist::ReadExResp 206792 # Transaction distribution 1058system.membus.trans_dist::ReadSharedReq 180710 # Transaction distribution 1059system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127988 # Packet count per connected master and slave (bytes) 1060system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127988 # Packet count per connected master and slave (bytes) 1061system.membus.pkt_count::total 1127988 # Packet count per connected master and slave (bytes) 1062system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43707968 # Cumulative packet size per connected master and slave (bytes) 1063system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43707968 # Cumulative packet size per connected master and slave (bytes) 1064system.membus.pkt_size::total 43707968 # Cumulative packet size per connected master and slave (bytes) |
| 1054system.membus.snoops 0 # Total snoops (count) 1055system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1065system.membus.snoops 0 # Total snoops (count) 1066system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1056system.membus.snoop_fanout::samples 387598 # Request fanout histogram | 1067system.membus.snoop_fanout::samples 387510 # Request fanout histogram |
| 1057system.membus.snoop_fanout::mean 0 # Request fanout histogram 1058system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1059system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1068system.membus.snoop_fanout::mean 0 # Request fanout histogram 1069system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1070system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1060system.membus.snoop_fanout::0 387598 100.00% 100.00% # Request fanout histogram | 1071system.membus.snoop_fanout::0 387510 100.00% 100.00% # Request fanout histogram |
| 1061system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1062system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1063system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1064system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1072system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1073system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1074system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1075system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1065system.membus.snoop_fanout::total 387598 # Request fanout histogram 1066system.membus.reqLayer0.occupancy 1995849000 # Layer occupancy (ticks) | 1076system.membus.snoop_fanout::total 387510 # Request fanout histogram 1077system.membus.reqLayer0.occupancy 1995365000 # Layer occupancy (ticks) |
| 1067system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) | 1078system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) |
| 1068system.membus.respLayer1.occupancy 2051150500 # Layer occupancy (ticks) | 1079system.membus.respLayer1.occupancy 2050434250 # Layer occupancy (ticks) |
| 1069system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1070 1071---------- End Simulation Statistics ---------- | 1080system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1081 1082---------- End Simulation Statistics ---------- |